CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FSP_S_TEST_CONFIG Struct Reference

CoffeeLake Intel Firmware

CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide
FSP_S_TEST_CONFIG Struct Reference

Fsp S Test Configuration. More...

#include <FspsUpd.h>

Public Attributes

UINT32 Signature
 Offset 0x07AD.
 
UINT8 ChapDeviceEnable
 Offset 0x07B1 - Enable/Disable Device 7 Enable: Device 7 enabled, Disable (Default): Device 7 disabled $EN_DIS.
 
UINT8 SkipPamLock
 Offset 0x07B2 - Skip PAM register lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS.
 
UINT8 EdramTestMode
 Offset 0x07B3 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode.
 
UINT8 DmiExtSync
 Offset 0x07B4 - DMI Extended Sync Control Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control $EN_DIS.
 
UINT8 DmiIot
 Offset 0x07B5 - DMI IOT Control Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control $EN_DIS.
 
UINT8 PegMaxPayload [4]
 Offset 0x07B6 - PEG Max Payload size per root port 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B.
 
UINT8 RenderStandby
 Offset 0x07BA - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS.
 
UINT8 PmSupport
 Offset 0x07BB - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS.
 
UINT8 CdynmaxClampEnable
 Offset 0x07BC - Enable/Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp $EN_DIS.
 
UINT8 VtdDisable
 Offset 0x07BD - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS.
 
UINT8 GtFreqMax
 Offset 0x07BE - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, 0x18: 1200 Mhz.
 
UINT8 DisableTurboGt
 Offset 0x07BF - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS.
 
UINT8 SaPostMemTestRsvd [11]
 Offset 0x07C0 - SaPostMemTestRsvd Reserved for SA Post-Mem Test $EN_DIS.
 
UINT8 OneCoreRatioLimit
 Offset 0x07CB - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
 
UINT8 TwoCoreRatioLimit
 Offset 0x07CC - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
 
UINT8 ThreeCoreRatioLimit
 Offset 0x07CD - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
 
UINT8 FourCoreRatioLimit
 Offset 0x07CE - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
 
UINT8 Hwp
 Offset 0x07CF - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. More...
 
UINT8 HdcControl
 Offset 0x07D0 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. More...
 
UINT8 PowerLimit1Time
 Offset 0x07D1 - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. More...
 
UINT8 PowerLimit2
 Offset 0x07D2 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. More...
 
UINT8 TurboPowerLimitLock
 Offset 0x07D3 - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS.
 
UINT8 PowerLimit3Time
 Offset 0x07D4 - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms.
 
UINT8 PowerLimit3DutyCycle
 Offset 0x07D5 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100.
 
UINT8 PowerLimit3Lock
 Offset 0x07D6 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS.
 
UINT8 PowerLimit4Lock
 Offset 0x07D7 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS.
 
UINT8 TccActivationOffset
 Offset 0x07D8 - TCC Activation Offset TCC Activation Offset. More...
 
UINT8 TccOffsetClamp
 Offset 0x07D9 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. More...
 
UINT8 TccOffsetLock
 Offset 0x07DA - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. More...
 
UINT8 NumberOfEntries
 Offset 0x07DB - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. More...
 
UINT8 Custom1PowerLimit1Time
 Offset 0x07DC - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. More...
 
UINT8 Custom1TurboActivationRatio
 Offset 0x07DD - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. More...
 
UINT8 Custom1ConfigTdpControl
 Offset 0x07DE - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. More...
 
UINT8 Custom2PowerLimit1Time
 Offset 0x07DF - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. More...
 
UINT8 Custom2TurboActivationRatio
 Offset 0x07E0 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. More...
 
UINT8 Custom2ConfigTdpControl
 Offset 0x07E1 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. More...
 
UINT8 Custom3PowerLimit1Time
 Offset 0x07E2 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. More...
 
UINT8 Custom3TurboActivationRatio
 Offset 0x07E3 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. More...
 
UINT8 Custom3ConfigTdpControl
 Offset 0x07E4 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. More...
 
UINT8 ConfigTdpLock
 Offset 0x07E5 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS.
 
UINT8 ConfigTdpBios
 Offset 0x07E6 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. More...
 
UINT8 PsysPowerLimit1
 Offset 0x07E7 - PL1 Enable value PL1 Enable value to limit average platform power. More...
 
UINT8 PsysPowerLimit1Time
 Offset 0x07E8 - PL1 timewindow PL1 timewindow in seconds. More...
 
UINT8 PsysPowerLimit2
 Offset 0x07E9 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power. More...
 
UINT8 MlcStreamerPrefetcher
 Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. More...
 
UINT8 MlcSpatialPrefetcher
 Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS.
 
UINT8 MonitorMwaitEnable
 Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. More...
 
UINT8 MachineCheckEnable
 Offset 0x07ED - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. More...
 
UINT8 DebugInterfaceEnable
 Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features. More...
 
UINT8 DebugInterfaceLockEnable
 Offset 0x07EF - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: Disable; 1: Enable. More...
 
UINT8 ApIdleManner
 Offset 0x07F0 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. More...
 
UINT8 ProcessorTraceOutputScheme
 Offset 0x07F1 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. More...
 
UINT8 ProcessorTraceEnable
 Offset 0x07F2 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. More...
 
UINT64 ProcessorTraceMemBase
 Offset 0x07F3 - Base of memory region allocated for Processor Trace Base address of memory region allocated for Processor Trace. More...
 
UINT32 ProcessorTraceMemLength
 Offset 0x07FB - Memory region allocation for Processor Trace Length in bytes of memory region allocated for Processor Trace. More...
 
UINT8 VoltageOptimization
 Offset 0x07FF - Enable or Disable Voltage Optimization feature Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable $EN_DIS.
 
UINT8 Eist
 Offset 0x0800 - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. More...
 
UINT8 EnergyEfficientPState
 Offset 0x0801 - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. More...
 
UINT8 EnergyEfficientTurbo
 Offset 0x0802 - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. More...
 
UINT8 TStates
 Offset 0x0803 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. More...
 
UINT8 BiProcHot
 Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS.
 
UINT8 DisableProcHotOut
 Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. More...
 
UINT8 ProcHotResponse
 Offset 0x0806 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. More...
 
UINT8 DisableVrThermalAlert
 Offset 0x0807 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. More...
 
UINT8 AutoThermalReporting
 Offset 0x0808 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. More...
 
UINT8 ThermalMonitor
 Offset 0x0809 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS.
 
UINT8 Cx
 Offset 0x080A - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). More...
 
UINT8 PmgCstCfgCtrlLock
 Offset 0x080B - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. More...
 
UINT8 C1e
 Offset 0x080C - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. More...
 
UINT8 PkgCStateDemotion
 Offset 0x080D - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion. More...
 
UINT8 PkgCStateUnDemotion
 Offset 0x080E - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion. More...
 
UINT8 CStatePreWake
 Offset 0x080F - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. More...
 
UINT8 TimedMwait
 Offset 0x0810 - Enable or Disable TimedMwait Support. More...
 
UINT8 CstCfgCtrIoMwaitRedirection
 Offset 0x0811 - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. More...
 
UINT8 PkgCStateLimit
 Offset 0x0812 - Set the Max Pkg Cstate Set the Max Pkg Cstate. More...
 
UINT8 CstateLatencyControl0TimeUnit
 Offset 0x0813 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
 
UINT8 CstateLatencyControl1TimeUnit
 Offset 0x0814 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
 
UINT8 CstateLatencyControl2TimeUnit
 Offset 0x0815 - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
 
UINT8 CstateLatencyControl3TimeUnit
 Offset 0x0816 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
 
UINT8 CstateLatencyControl4TimeUnit
 Offset 0x0817 - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
 
UINT8 CstateLatencyControl5TimeUnit
 Offset 0x0818 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns.
 
UINT8 PpmIrmSetting
 Offset 0x0819 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
 
UINT8 ProcHotLock
 Offset 0x081A - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS.
 
UINT8 ConfigTdpLevel
 Offset 0x081B - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate.
 
UINT8 RaceToHalt
 Offset 0x081C - Race To Halt Enable/Disable Race To Halt feature. More...
 
UINT8 MaxRatio
 Offset 0x081D - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F.
 
UINT8 StateRatio [40]
 Offset 0x081E - P-state ratios for custom P-state table P-state ratios for custom P-state table. More...
 
UINT8 StateRatioMax16 [16]
 Offset 0x0846 - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. More...
 
UINT16 PsysPmax
 Offset 0x0856 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. More...
 
UINT16 CstateLatencyControl0Irtl
 Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0 Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF.
 
UINT16 CstateLatencyControl1Irtl
 Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF.
 
UINT16 CstateLatencyControl2Irtl
 Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF.
 
UINT16 CstateLatencyControl3Irtl
 Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF.
 
UINT16 CstateLatencyControl4Irtl
 Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF.
 
UINT16 CstateLatencyControl5Irtl
 Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF.
 
UINT32 PowerLimit1
 Offset 0x0864 - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. More...
 
UINT32 PowerLimit2Power
 Offset 0x0868 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. More...
 
UINT32 PowerLimit3
 Offset 0x086C - Package PL3 power limit Package PL3 power limit. More...
 
UINT32 PowerLimit4
 Offset 0x0870 - Package PL4 power limit Package PL4 power limit. More...
 
UINT32 TccOffsetTimeWindowForRatl
 Offset 0x0874 - Tcc Offset Time Window for RATL Package PL4 power limit. More...
 
UINT32 Custom1PowerLimit1
 Offset 0x0878 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. More...
 
UINT32 Custom1PowerLimit2
 Offset 0x087C - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. More...
 
UINT32 Custom2PowerLimit1
 Offset 0x0880 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. More...
 
UINT32 Custom2PowerLimit2
 Offset 0x0884 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. More...
 
UINT32 Custom3PowerLimit1
 Offset 0x0888 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. More...
 
UINT32 Custom3PowerLimit2
 Offset 0x088C - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. More...
 
UINT32 PsysPowerLimit1Power
 Offset 0x0890 - Platform PL1 power Platform PL1 power. More...
 
UINT32 PsysPowerLimit2Power
 Offset 0x0894 - Platform PL2 power Platform PL2 power. More...
 
UINT8 ThreeStrikeCounterDisable
 Offset 0x0898 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. More...
 
UINT8 HwpInterruptControl
 Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. More...
 
UINT8 FiveCoreRatioLimit
 Offset 0x089A - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
 
UINT8 SixCoreRatioLimit
 Offset 0x089B - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
 
UINT8 SevenCoreRatioLimit
 Offset 0x089C - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
 
UINT8 EightCoreRatioLimit
 Offset 0x089D - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. More...
 
UINT8 EnableItbm
 Offset 0x089E - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. More...
 
UINT8 EnableItbmDriver
 Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled $EN_DIS.
 
UINT8 C1StateAutoDemotion
 Offset 0x08A0 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion. More...
 
UINT8 C1StateUnDemotion
 Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion. More...
 
UINT8 CpuWakeUpTimer
 Offset 0x08A2 - CpuWakeUpTimer Enable long CPU Wakeup Timer. More...
 
UINT8 MinRingRatioLimit
 Offset 0x08A3 - Minimum Ring ratio limit override Minimum Ring ratio limit override. More...
 
UINT8 MaxRingRatioLimit
 Offset 0x08A4 - Minimum Ring ratio limit override Maximum Ring ratio limit override. More...
 
UINT8 C3StateAutoDemotion
 Offset 0x08A5 - Enable or Disable C3 Cstate Demotion Enable or Disable C3 Cstate Demotion. More...
 
UINT8 C3StateUnDemotion
 Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion Enable or Disable C3 Cstate UnDemotion. More...
 
UINT8 ReservedCpuPostMemTest [19]
 Offset 0x08A7 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS.
 
UINT8 SgxSinitDataFromTpm
 Offset 0x08BA - SgxSinitDataFromTpm SgxSinitDataFromTpm default values.
 
UINT8 EndOfPostMessage
 Offset 0x08BB - End of Post message Test, Send End of Post message. More...
 
UINT8 DisableD0I3SettingForHeci
 Offset 0x08BC - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS.
 
UINT16 PchHdaResetWaitTimer
 Offset 0x08BD - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of microseconds. More...
 
UINT8 PchLockDownGlobalSmi
 Offset 0x08BF - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. More...
 
UINT8 PchLockDownBiosInterface
 Offset 0x08C0 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. More...
 
UINT8 PchUnlockGpioPads
 Offset 0x08C1 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. More...
 
UINT8 PchSbiUnlock
 Offset 0x08C2 - PCH Unlock SBI access Deprecated $EN_DIS.
 
UINT8 PchSbAccessUnlock
 Offset 0x08C3 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. More...
 
UINT16 PcieRpLtrMaxSnoopLatency [24]
 Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency.
 
UINT16 PcieRpLtrMaxNoSnoopLatency [24]
 Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency.
 
UINT8 PcieRpSnoopLatencyOverrideMode [24]
 Offset 0x0924 - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode.
 
UINT8 PcieRpSnoopLatencyOverrideMultiplier [24]
 Offset 0x093C - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier.
 
UINT16 PcieRpSnoopLatencyOverrideValue [24]
 Offset 0x0954 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value.
 
UINT8 PcieRpNonSnoopLatencyOverrideMode [24]
 Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
 
UINT8 PcieRpNonSnoopLatencyOverrideMultiplier [24]
 Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
 
UINT16 PcieRpNonSnoopLatencyOverrideValue [24]
 Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value.
 
UINT8 PcieRpSlotPowerLimitScale [24]
 Offset 0x09E4 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. More...
 
UINT16 PcieRpSlotPowerLimitValue [24]
 Offset 0x09FC - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. More...
 
UINT8 PcieRpUptp [24]
 Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization. More...
 
UINT8 PcieRpDptp [24]
 Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization. More...
 
UINT8 PcieEnablePort8xhDecode
 Offset 0x0A5C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. More...
 
UINT8 PchPciePort8xhDecodePortIndex
 Offset 0x0A5D - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
 
UINT8 PchPmDisableEnergyReport
 Offset 0x0A5E - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. More...
 
UINT8 SataTestMode
 Offset 0x0A5F - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. More...
 
UINT8 PchXhciOcLock
 Offset 0x0A60 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. More...
 
UINT8 UnusedUpdSpace24 [17]
 Offset 0x0A61.
 
UINT8 SkipPostBootSai
 Offset 0x0A72 - Skip POSTBOOT SAI Deprecated $EN_DIS.
 
UINT8 MctpBroadcastCycle
 Offset 0x0A73 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. More...
 
UINT8 ReservedFspsTestUpd [12]
 Offset 0x0A74.
 

Detailed Description

Fsp S Test Configuration.

Definition at line 2358 of file FspsUpd.h.

Member Data Documentation

UINT8 FSP_S_TEST_CONFIG::ApIdleManner

Offset 0x07F0 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop.

1: HALT loop, 2: MWAIT loop, 3: RUN loop

Definition at line 2681 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::AutoThermalReporting

Offset 0x0808 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2767 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C1e

Offset 0x080C - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states.

0: Disable; 1: Enable $EN_DIS

Definition at line 2791 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C1StateAutoDemotion

Offset 0x08A0 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion.

Disable; 1: Enable $EN_DIS

Definition at line 3083 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C1StateUnDemotion

Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion.

Disable; 1: Enable $EN_DIS

Definition at line 3089 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C3StateAutoDemotion

Offset 0x08A5 - Enable or Disable C3 Cstate Demotion Enable or Disable C3 Cstate Demotion.

Disable; 1: Enable $EN_DIS

Definition at line 3114 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::C3StateUnDemotion

Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion Enable or Disable C3 Cstate UnDemotion.

Disable; 1: Enable $EN_DIS

Definition at line 3120 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ConfigTdpBios

Offset 0x07E6 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2620 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::CpuWakeUpTimer

Offset 0x08A2 - CpuWakeUpTimer Enable long CPU Wakeup Timer.

When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable $EN_DIS

Definition at line 3096 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::CStatePreWake

Offset 0x080F - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake.

0: Disable; 1: Enable $EN_DIS

Definition at line 2809 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::CstCfgCtrIoMwaitRedirection

Offset 0x0811 - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2821 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom1ConfigTdpControl

Offset 0x07DE - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1.

Valid Range is 0 to 2

Definition at line 2576 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom1PowerLimit1

Offset 0x0878 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2982 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom1PowerLimit1Time

Offset 0x07DC - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1.

Valid Range 0 to 128, 0 = AUTO

Definition at line 2566 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom1PowerLimit2

Offset 0x087C - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2988 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom1TurboActivationRatio

Offset 0x07DD - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1.

Valid Range 0 to 255

Definition at line 2571 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom2ConfigTdpControl

Offset 0x07E1 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1.

Valid Range is 0 to 2

Definition at line 2592 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom2PowerLimit1

Offset 0x0880 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2994 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom2PowerLimit1Time

Offset 0x07DF - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2.

Valid Range 0 to 128, 0 = AUTO

Definition at line 2582 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom2PowerLimit2

Offset 0x0884 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 3000 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom2TurboActivationRatio

Offset 0x07E0 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2.

Valid Range 0 to 255

Definition at line 2587 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom3ConfigTdpControl

Offset 0x07E4 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1.

Valid Range is 0 to 2

Definition at line 2608 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom3PowerLimit1

Offset 0x0888 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 3006 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom3PowerLimit1Time

Offset 0x07E2 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3.

Valid Range 0 to 128, 0 = AUTO

Definition at line 2598 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::Custom3PowerLimit2

Offset 0x088C - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 3012 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Custom3TurboActivationRatio

Offset 0x07E3 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3.

Valid Range 0 to 255

Definition at line 2603 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Cx

Offset 0x080A - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states).

0: Disable; 1: Enable $EN_DIS

Definition at line 2779 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DebugInterfaceEnable

Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features.

Deprecated:
Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS

Definition at line 2669 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DebugInterfaceLockEnable

Offset 0x07EF - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2675 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DisableProcHotOut

Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2749 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::DisableVrThermalAlert

Offset 0x0807 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2761 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EightCoreRatioLimit

Offset 0x089D - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF

Definition at line 3065 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Eist

Offset 0x0800 - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology.

0: Disable; 1: Enable $EN_DIS

Definition at line 2717 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EnableItbm

Offset 0x089E - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0.

0: Disabled; 1: Enabled $EN_DIS

Definition at line 3071 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EndOfPostMessage

Offset 0x08BB - End of Post message Test, Send End of Post message.

Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved

Definition at line 3138 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EnergyEfficientPState

Offset 0x0801 - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode.

Disable; 1: Enable $EN_DIS

Definition at line 2724 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::EnergyEfficientTurbo

Offset 0x0802 - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode.

Disable; 1: Enable $EN_DIS

Definition at line 2731 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::FiveCoreRatioLimit

Offset 0x089A - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF

Definition at line 3044 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::FourCoreRatioLimit

Offset 0x07CE - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2477 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::HdcControl

Offset 0x07D0 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration.

0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS

Definition at line 2490 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::Hwp

Offset 0x07CF - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support.

0: Disable; 1: Enable; 2-3:Reserved $EN_DIS

Definition at line 2484 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::HwpInterruptControl

Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 3037 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MachineCheckEnable

Offset 0x07ED - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2663 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MaxRingRatioLimit

Offset 0x08A4 - Minimum Ring ratio limit override Maximum Ring ratio limit override.

0: Hardware defaults. Range: 0 - Max turbo ratio limit

Definition at line 3108 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MctpBroadcastCycle

Offset 0x0A73 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable.

$EN_DIS

Definition at line 3288 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MinRingRatioLimit

Offset 0x08A3 - Minimum Ring ratio limit override Minimum Ring ratio limit override.

0: Hardware defaults. Range: 0 - Max turbo ratio limit

Definition at line 3102 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MlcStreamerPrefetcher

Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2645 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::MonitorMwaitEnable

Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2657 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::NumberOfEntries

Offset 0x07DB - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states.

At least 2 states must be present

Definition at line 2560 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::OneCoreRatioLimit

Offset 0x07CB - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 255

Definition at line 2459 of file FspsUpd.h.

UINT16 FSP_S_TEST_CONFIG::PchHdaResetWaitTimer

Offset 0x08BD - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of microseconds.

Default is 600.

Definition at line 3150 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchLockDownBiosInterface

Offset 0x08C0 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.

$EN_DIS

Definition at line 3162 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchLockDownGlobalSmi

Offset 0x08BF - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.

$EN_DIS

Definition at line 3156 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchPmDisableEnergyReport

Offset 0x0A5E - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature.

$EN_DIS

Definition at line 3259 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchSbAccessUnlock

Offset 0x08C3 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g.

PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS

Definition at line 3181 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchUnlockGpioPads

Offset 0x08C1 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose.

$EN_DIS

Definition at line 3168 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PchXhciOcLock

Offset 0x0A60 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.

$EN_DIS

Definition at line 3272 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieEnablePort8xhDecode

Offset 0x0A5C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled.

0: Disable; 1: Enable. $EN_DIS

Definition at line 3248 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieRpDptp[24]

Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization.

Used for all lanes. Default is 7.

Definition at line 3241 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieRpSlotPowerLimitScale[24]

Offset 0x09E4 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value.

Leave as 0 to set to default.

Definition at line 3226 of file FspsUpd.h.

UINT16 FSP_S_TEST_CONFIG::PcieRpSlotPowerLimitValue[24]

Offset 0x09FC - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot.

Leave as 0 to set to default.

Definition at line 3231 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PcieRpUptp[24]

Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization.

Used for all lanes. Default is 5.

Definition at line 3236 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PkgCStateDemotion

Offset 0x080D - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion.

0: Disable; 1: Enable $EN_DIS

Definition at line 2797 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PkgCStateLimit

Offset 0x0812 - Set the Max Pkg Cstate Set the Max Pkg Cstate.

Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto

Definition at line 2828 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PkgCStateUnDemotion

Offset 0x080E - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion.

0: Disable; 1: Enable $EN_DIS

Definition at line 2803 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PmgCstCfgCtrlLock

Offset 0x080B - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2785 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit1

Offset 0x0864 - Package Long duration turbo mode power limit Package Long duration turbo mode power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125

Definition at line 2952 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PowerLimit1Time

Offset 0x07D1 - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds.

0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128

Definition at line 2497 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PowerLimit2

Offset 0x07D2 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode.

0 : Disable; 1: Enable $EN_DIS

Definition at line 2503 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit2Power

Offset 0x0868 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2958 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit3

Offset 0x086C - Package PL3 power limit Package PL3 power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 2964 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PowerLimit4

Offset 0x0870 - Package PL4 power limit Package PL4 power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125

Definition at line 2970 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ProcessorTraceEnable

Offset 0x07F2 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2693 of file FspsUpd.h.

UINT64 FSP_S_TEST_CONFIG::ProcessorTraceMemBase

Offset 0x07F3 - Base of memory region allocated for Processor Trace Base address of memory region allocated for Processor Trace.

Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable

Definition at line 2699 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::ProcessorTraceMemLength

Offset 0x07FB - Memory region allocation for Processor Trace Length in bytes of memory region allocated for Processor Trace.

Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable

Definition at line 2705 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ProcessorTraceOutputScheme

Offset 0x07F1 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output.

0: Single Range Output, 1: ToPA Output

Definition at line 2687 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ProcHotResponse

Offset 0x0806 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2755 of file FspsUpd.h.

UINT16 FSP_S_TEST_CONFIG::PsysPmax

Offset 0x0856 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax.

0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W

Definition at line 2916 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PsysPowerLimit1

Offset 0x07E7 - PL1 Enable value PL1 Enable value to limit average platform power.

0: Disable; 1: Enable. $EN_DIS

Definition at line 2626 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PsysPowerLimit1Power

Offset 0x0890 - Platform PL1 power Platform PL1 power.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 3018 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PsysPowerLimit1Time

Offset 0x07E8 - PL1 timewindow PL1 timewindow in seconds.

0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128

Definition at line 2632 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::PsysPowerLimit2

Offset 0x07E9 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.

0: Disable; 1: Enable. $EN_DIS

Definition at line 2639 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::PsysPowerLimit2Power

Offset 0x0894 - Platform PL2 power Platform PL2 power.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125

Definition at line 3024 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::RaceToHalt

Offset 0x081C - Race To Halt Enable/Disable Race To Halt feature.

RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable $EN_DIS

Definition at line 2889 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::SataTestMode

Offset 0x0A5F - PCH Sata Test Mode Allow entrance to the PCH SATA test modes.

$EN_DIS

Definition at line 3265 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::SevenCoreRatioLimit

Offset 0x089C - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF

Definition at line 3058 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::SixCoreRatioLimit

Offset 0x089B - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF

Definition at line 3051 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::StateRatio[40]

Offset 0x081E - P-state ratios for custom P-state table P-state ratios for custom P-state table.

NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F

Definition at line 2901 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::StateRatioMax16[16]

Offset 0x0846 - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table.

This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and up to the top 16 values of the StateRatio table will be used instead. Valid Range of each entry is 0 to 0x7F

Definition at line 2910 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TccActivationOffset

Offset 0x07D8 - TCC Activation Offset TCC Activation Offset.

Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, For all other SKUs the recommended default are 0

Definition at line 2539 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TccOffsetClamp

Offset 0x07D9 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled.

$EN_DIS

Definition at line 2547 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TccOffsetLock

Offset 0x07DA - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled.

$EN_DIS

Definition at line 2554 of file FspsUpd.h.

UINT32 FSP_S_TEST_CONFIG::TccOffsetTimeWindowForRatl

Offset 0x0874 - Tcc Offset Time Window for RATL Package PL4 power limit.

Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125

Definition at line 2976 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ThreeCoreRatioLimit

Offset 0x07CD - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2471 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::ThreeStrikeCounterDisable

Offset 0x0898 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True.

0: False, 1: True

Definition at line 3031 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TimedMwait

Offset 0x0810 - Enable or Disable TimedMwait Support.

Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS

Definition at line 2815 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TStates

Offset 0x0803 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable.

$EN_DIS

Definition at line 2737 of file FspsUpd.h.

UINT8 FSP_S_TEST_CONFIG::TwoCoreRatioLimit

Offset 0x07CC - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255.

This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255

Definition at line 2465 of file FspsUpd.h.


The documentation for this struct was generated from the following file:
Generated on Wed Aug 22 2018 17:48:56 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by   doxygen 1.8.10