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CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide
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UPD PORTING GUIDE
5 UPD porting guide
UPD porting guide:
| UPD | Dependency | Description | Value |
|---|---|---|---|
| EnableSgx | CoffeeLake Platform | Temporary workaround | 2 |
| PchTraceHubMode | CoffeeLake Pch A0 | BIOS workaround for TraceHub power gating issue on PCH A0 | 2 |
| PchTraceHubMemReg0Size | CoffeeLake Pch A0 | BIOS workaround for TraceHub power gating issue on PCH A0 | 3 |
| PchTraceHubMemReg1Size | CoffeeLake Pch A0 | BIOS workaround for TraceHub power gating issue on PCH A0 | 3 |
| CstateLatencyControl1Irtl | Server platform | Server platform should has different setting | 0x6B |
| PchPcieHsioRxSetCtleEnable | Board design | Different board requires different value | tune |
| PchPcieHsioRxSetCtle | Board design | Different board requires different value | tune |
| PchSataHsioRxGen3EqBoostMagEnable | Board design | Different board requires different value | tune |
| PchSataHsioRxGen3EqBoostMag | Board design | Different board requires different value | tune |
| PchSataHsioTxGen1DownscaleAmpEnable | Board design | Different board requires different value | tune |
| PchSataHsioTxGen1DownscaleAmp | Board design | Different board requires different value | tune |
| PchSataHsioTxGen2DownscaleAmpEnable | Board design | Different board requires different value | tune |
| PchSataHsioTxGen2DownscaleAmp | Board design | Different board requires different value | tune |
| PchNumRsvdSmbusAddresses | Board design | Different board requires different value | tune |
| RsvdSmbusAddressTablePtr | Board design | Different board requires different value | tune |
| BiosSize | Board design | Different board requires different value | tune |
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by
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