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UINT32 | Signature |
| | Offset 0x0520.
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| |
|
UINT8 | SkipExtGfxScan |
| | Offset 0x0524 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS.
|
| |
| UINT8 | BdatEnable |
| | Offset 0x0525 - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. More...
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| |
| UINT8 | ScanExtGfxForLegacyOpRom |
| | Offset 0x0526 - Detect External Graphics device for LegacyOpROM Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). More...
|
| |
| UINT8 | LockPTMregs |
| | Offset 0x0527 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. More...
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| |
|
UINT8 | DmiMaxLinkSpeed |
| | Offset 0x0528 - DMI Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3.
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| |
| UINT8 | DmiGen3EqPh2Enable |
| | Offset 0x0529 - DMI Equalization Phase 2 DMI Equalization Phase 2. More...
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| |
| UINT8 | DmiGen3EqPh3Method |
| | Offset 0x052A - DMI Gen3 Equalization Phase3 DMI Gen3 Equalization Phase3. More...
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| |
| UINT8 | Peg0Gen3EqPh2Enable |
| | Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0. More...
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| |
| UINT8 | Peg1Gen3EqPh2Enable |
| | Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1. More...
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| |
| UINT8 | Peg2Gen3EqPh2Enable |
| | Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2. More...
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| |
| UINT8 | Peg3Gen3EqPh2Enable |
| | Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3. More...
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| |
| UINT8 | Peg0Gen3EqPh3Method |
| | Offset 0x052F - Phase3 EQ method on the PEG 0:1:0. More...
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| |
| UINT8 | Peg1Gen3EqPh3Method |
| | Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1. More...
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| |
| UINT8 | Peg2Gen3EqPh3Method |
| | Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2. More...
|
| |
| UINT8 | Peg3Gen3EqPh3Method |
| | Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3. More...
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| |
| UINT8 | PegGen3ProgramStaticEq |
| | Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program PEG Gen3 EQ Phase1 Static Presets. More...
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| |
| UINT8 | Gen3SwEqAlwaysAttempt |
| | Offset 0x0534 - PEG Gen3 SwEq Always Attempt Gen3 Software Equalization will be executed every boot. More...
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| |
| UINT8 | Gen3SwEqNumberOfPresets |
| | Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq Select number of TxEq presets to test in the PCIe/DMI SwEq. More...
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| |
| UINT8 | Gen3SwEqEnableVocTest |
| | Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. More...
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| |
|
UINT8 | PegRxCemTestingMode |
| | Offset 0x0537 - PCIe Rx Compliance Testing Mode Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing $EN_DIS.
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| |
| UINT8 | PegRxCemLoopbackLane |
| | Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled the specificied Lane (0 - 15) will be used for RxCEMLoopback. More...
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| |
| UINT8 | PegGenerateBdatMarginTable |
| | Offset 0x0539 - Generate PCIe BDAT Margin Table Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. More...
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| |
| UINT8 | PegRxCemNonProtocolAwareness |
| | Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. More...
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| |
|
UINT8 | PegGen3RxCtleOverride |
| | Offset 0x053B - PCIe Override RxCTLE Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified $EN_DIS.
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| |
|
UINT8 | PegGen3Rsvd |
| | Offset 0x053C - Rsvd Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified $EN_DIS.
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| |
| UINT8 | PegGen3RootPortPreset [20] |
| | Offset 0x053D - PEG Gen3 Root port preset values per lane Used for programming PEG Gen3 preset values per lane. More...
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| |
| UINT8 | PegGen3EndPointPreset [20] |
| | Offset 0x0551 - PEG Gen3 End port preset values per lane Used for programming PEG Gen3 preset values per lane. More...
|
| |
| UINT8 | PegGen3EndPointHint [20] |
| | Offset 0x0565 - PEG Gen3 End port Hint values per lane Used for programming PEG Gen3 Hint values per lane. More...
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| |
|
UINT8 | UnusedUpdSpace8 |
| | Offset 0x0579.
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| |
| UINT16 | Gen3SwEqJitterDwellTime |
| | Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. More...
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| |
| UINT16 | Gen3SwEqJitterErrorTarget |
| | Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 1. More...
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| |
| UINT16 | Gen3SwEqVocDwellTime |
| | Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 10000. More...
|
| |
| UINT16 | Gen3SwEqVocErrorTarget |
| | Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 2. More...
|
| |
| UINT8 | PanelPowerEnable |
| | Offset 0x0582 - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). More...
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| |
| UINT8 | BdatTestType |
| | Offset 0x0583 - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACPI table. More...
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| |
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UINT8 | SaPreMemTestRsvd [12] |
| | Offset 0x0584 - SaPreMemTestRsvd Reserved for SA Pre-Mem Test $EN_DIS.
|
| |
| UINT16 | TotalFlashSize |
| | Offset 0x0590 - TotalFlashSize Enable/Disable. More...
|
| |
| UINT16 | BiosSize |
| | Offset 0x0592 - BiosSize Enable/Disable. More...
|
| |
| UINT8 | TxtAcheckRequest |
| | Offset 0x0594 - TxtAcheckRequest Enable/Disable. More...
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| |
|
UINT8 | SecurityTestRsvd [3] |
| | Offset 0x0595 - SecurityTestRsvd Reserved for SA Pre-Mem Test $EN_DIS.
|
| |
| UINT8 | SmbusDynamicPowerGating |
| | Offset 0x0598 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. More...
|
| |
| UINT8 | WdtDisableAndLock |
| | Offset 0x0599 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers. More...
|
| |
| UINT8 | SmbusSpdWriteDisable |
| | Offset 0x059A - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. More...
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| |
|
UINT8 | ChipsetInitMessage |
| | Offset 0x059B - ChipsetInit HECI message DEPRECATED $EN_DIS.
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| |
| UINT8 | BypassPhySyncReset |
| | Offset 0x059C - Bypass ChipsetInit sync reset. More...
|
| |
|
UINT8 | DidInitStat |
| | Offset 0x059D - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value $EN_DIS.
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| |
|
UINT8 | DisableCpuReplacedPolling |
| | Offset 0x059E - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop $EN_DIS.
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| |
|
UINT8 | SendDidMsg |
| | Offset 0x059F - ME DID Message Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent) $EN_DIS.
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| |
| UINT8 | DisableHeciRetry |
| | Offset 0x05A0 - Retry mechanism for HECI APIs Test, 0: disable, 1: enable, Enable/Disable HECI retry. More...
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| |
| UINT8 | DisableMessageCheck |
| | Offset 0x05A1 - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check. More...
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| |
| UINT8 | SkipMbpHob |
| | Offset 0x05A2 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. More...
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| |
| UINT8 | HeciCommunication2 |
| | Offset 0x05A3 - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. More...
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| |
| UINT8 | KtDeviceEnable |
| | Offset 0x05A4 - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device. More...
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| |
| UINT8 | tRd2RdSG |
| | Offset 0x05A5 - tRd2RdSG Delay between Read-to-Read commands in the same Bank Group. More...
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| |
| UINT8 | tRd2RdDG |
| | Offset 0x05A6 - tRd2RdDG Delay between Read-to-Read commands in different Bank Group for DDR4. More...
|
| |
| UINT8 | tRd2RdDR |
| | Offset 0x05A7 - tRd2RdDR Delay between Read-to-Read commands in different Ranks. More...
|
| |
| UINT8 | tRd2RdDD |
| | Offset 0x05A8 - tRd2RdDD Delay between Read-to-Read commands in different DIMMs. More...
|
| |
| UINT8 | tWr2RdSG |
| | Offset 0x05A9 - tWr2RdSG Delay between Write-to-Read commands in the same Bank Group. More...
|
| |
| UINT8 | tWr2RdDG |
| | Offset 0x05AA - tWr2RdDG Delay between Write-to-Read commands in different Bank Group for DDR4. More...
|
| |
| UINT8 | tWr2RdDR |
| | Offset 0x05AB - tWr2RdDR Delay between Write-to-Read commands in different Ranks. More...
|
| |
| UINT8 | tWr2RdDD |
| | Offset 0x05AC - tWr2RdDD Delay between Write-to-Read commands in different DIMMs. More...
|
| |
| UINT8 | tWr2WrSG |
| | Offset 0x05AD - tWr2WrSG Delay between Write-to-Write commands in the same Bank Group. More...
|
| |
| UINT8 | tWr2WrDG |
| | Offset 0x05AE - tWr2WrDG Delay between Write-to-Write commands in different Bank Group for DDR4. More...
|
| |
| UINT8 | tWr2WrDR |
| | Offset 0x05AF - tWr2WrDR Delay between Write-to-Write commands in different Ranks. More...
|
| |
| UINT8 | tWr2WrDD |
| | Offset 0x05B0 - tWr2WrDD Delay between Write-to-Write commands in different DIMMs. More...
|
| |
| UINT8 | tRd2WrSG |
| | Offset 0x05B1 - tRd2WrSG Delay between Read-to-Write commands in the same Bank Group. More...
|
| |
| UINT8 | tRd2WrDG |
| | Offset 0x05B2 - tRd2WrDG Delay between Read-to-Write commands in different Bank Group for DDR4. More...
|
| |
| UINT8 | tRd2WrDR |
| | Offset 0x05B3 - tRd2WrDR Delay between Read-to-Write commands in different Ranks. More...
|
| |
| UINT8 | tRd2WrDD |
| | Offset 0x05B4 - tRd2WrDD Delay between Read-to-Write commands in different DIMMs. More...
|
| |
| UINT8 | tRRD_L |
| | Offset 0x05B5 - tRRD_L Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. More...
|
| |
| UINT8 | tRRD_S |
| | Offset 0x05B6 - tRRD_S Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. More...
|
| |
| UINT8 | tWTR_L |
| | Offset 0x05B7 - tWTR_L Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. More...
|
| |
| UINT8 | tWTR_S |
| | Offset 0x05B8 - tWTR_S Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. More...
|
| |
|
UINT8 | ReservedFspmTestUpd [3] |
| | Offset 0x05B9.
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| |
1.8.10