CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FspsUpd.h Source File

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CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide
FspsUpd.h
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1 /** @file
2 
3 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
4 
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
7 
8 * Redistributions of source code must retain the above copyright notice, this
9  list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice, this
11  list of conditions and the following disclaimer in the documentation and/or
12  other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors may
14  be used to endorse or promote products derived from this software without
15  specific prior written permission.
16 
17  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27  THE POSSIBILITY OF SUCH DAMAGE.
28 
29  This file is automatically generated. Please do NOT modify !!!
30 
31 **/
32 
33 #ifndef __FSPSUPD_H__
34 #define __FSPSUPD_H__
35 
36 #include <FspUpd.h>
37 
38 #pragma pack(1)
39 
40 
41 ///
42 /// Azalia Header structure
43 ///
44 typedef struct {
45  UINT16 VendorId; ///< Codec Vendor ID
46  UINT16 DeviceId; ///< Codec Device ID
47  UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
48  UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
49  UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
50  UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
51 } AZALIA_HEADER;
52 
53 ///
54 /// Audio Azalia Verb Table structure
55 ///
56 typedef struct {
57  AZALIA_HEADER Header; ///< AZALIA PCH header
58  UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
59 } AUDIO_AZALIA_VERB_TABLE;
60 
61 ///
62 /// Refer to the definition of PCH_INT_PIN
63 ///
64 typedef enum {
65  SiPchNoInt, ///< No Interrupt Pin
66  SiPchIntA,
67  SiPchIntB,
68  SiPchIntC,
69  SiPchIntD
70 } SI_PCH_INT_PIN;
71 ///
72 /// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
73 ///
74 typedef struct {
75  UINT8 Device; ///< Device number
76  UINT8 Function; ///< Device function
77  UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
78  UINT8 Irq; ///< IRQ to be set for device.
79 } SI_PCH_DEVICE_INTERRUPT_CONFIG;
80 
81 #define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
82 
83 
84 /** Fsp S Configuration
85 **/
86 typedef struct {
87 
88 /** Offset 0x0020 - Logo Pointer
89  Points to PEI Display Logo Image
90 **/
91  UINT32 LogoPtr;
92 
93 /** Offset 0x0024 - Logo Size
94  Size of PEI Display Logo Image
95 **/
96  UINT32 LogoSize;
97 
98 /** Offset 0x0028 - Graphics Configuration Ptr
99  Points to VBT
100 **/
101  UINT32 GraphicsConfigPtr;
102 
103 /** Offset 0x002C - Enable Device 4
104  Enable/disable Device 4
105  $EN_DIS
106 **/
107  UINT8 Device4Enable;
108 
109 /** Offset 0x002D - Enable HD Audio DSP
110  Enable/disable HD Audio DSP feature.
111  $EN_DIS
112 **/
113  UINT8 PchHdaDspEnable;
114 
115 /** Offset 0x002E
116 **/
117  UINT8 UnusedUpdSpace0[3];
118 
119 /** Offset 0x0031 - Enable eMMC Controller
120  Enable/disable eMMC Controller.
121  $EN_DIS
122 **/
123  UINT8 ScsEmmcEnabled;
124 
125 /** Offset 0x0032 - Enable eMMC HS400 Mode
126  Enable eMMC HS400 Mode.
127  $EN_DIS
128 **/
129  UINT8 ScsEmmcHs400Enabled;
130 
131 /** Offset 0x0033 - Enable SdCard Controller
132  Enable/disable SD Card Controller.
133  $EN_DIS
134 **/
135  UINT8 ScsSdCardEnabled;
136 
137 /** Offset 0x0034 - Show SPI controller
138  Enable/disable to show SPI controller.
139  $EN_DIS
140 **/
141  UINT8 ShowSpiController;
142 
143 /** Offset 0x0035
144 **/
145  UINT8 UnusedUpdSpace1[3];
146 
147 /** Offset 0x0038 - MicrocodeRegionBase
148  Memory Base of Microcode Updates
149 **/
150  UINT32 MicrocodeRegionBase;
151 
152 /** Offset 0x003C - MicrocodeRegionSize
153  Size of Microcode Updates
154 **/
155  UINT32 MicrocodeRegionSize;
156 
157 /** Offset 0x0040 - Turbo Mode
158  Enable/Disable Turbo mode. 0: disable, 1: enable
159  $EN_DIS
160 **/
161  UINT8 TurboMode;
162 
163 /** Offset 0x0041 - Enable SATA SALP Support
164  Enable/disable SATA Aggressive Link Power Management.
165  $EN_DIS
166 **/
167  UINT8 SataSalpSupport;
168 
169 /** Offset 0x0042 - Enable SATA ports
170  Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
171  and so on.
172 **/
173  UINT8 SataPortsEnable[8];
174 
175 /** Offset 0x004A - Enable SATA DEVSLP Feature
176  Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
177  port, byte0 for port0, byte1 for port1, and so on.
178 **/
179  UINT8 SataPortsDevSlp[8];
180 
181 /** Offset 0x0052 - Enable USB2 ports
182  Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
183  port1, and so on.
184 **/
185  UINT8 PortUsb20Enable[16];
186 
187 /** Offset 0x0062 - Enable USB3 ports
188  Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
189  port1, and so on.
190 **/
191  UINT8 PortUsb30Enable[10];
192 
193 /** Offset 0x006C - Enable xDCI controller
194  Enable/disable to xDCI controller.
195  $EN_DIS
196 **/
197  UINT8 XdciEnable;
198 
199 /** Offset 0x006D
200 **/
201  UINT8 UnusedUpdSpace2[2];
202 
203 /** Offset 0x006F - Enable SerialIo Device Mode
204  0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable
205  SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device
206  mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1,
207  and so on.
208 **/
209  UINT8 SerialIoDevMode[12];
210 
211 /** Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
212  The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
213 **/
214  UINT32 DevIntConfigPtr;
215 
216 /** Offset 0x007F - Number of DevIntConfig Entry
217  Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
218  must not be NULL.
219 **/
220  UINT8 NumOfDevIntConfig;
221 
222 /** Offset 0x0080 - PIRQx to IRQx Map Config
223  PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
224  PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
225  8259 PCI mode.
226 **/
227  UINT8 PxRcConfig[8];
228 
229 /** Offset 0x0088 - Select GPIO IRQ Route
230  GPIO IRQ Select. The valid value is 14 or 15.
231 **/
232  UINT8 GpioIrqRoute;
233 
234 /** Offset 0x0089 - Select SciIrqSelect
235  SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
236 **/
237  UINT8 SciIrqSelect;
238 
239 /** Offset 0x008A - Select TcoIrqSelect
240  TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
241 **/
242  UINT8 TcoIrqSelect;
243 
244 /** Offset 0x008B - Enable/Disable Tco IRQ
245  Enable/disable TCO IRQ
246  $EN_DIS
247 **/
248  UINT8 TcoIrqEnable;
249 
250 /** Offset 0x008C - PCH HDA Verb Table Entry Number
251  Number of Entries in Verb Table.
252 **/
253  UINT8 PchHdaVerbTableEntryNum;
254 
255 /** Offset 0x008D - PCH HDA Verb Table Pointer
256  Pointer to Array of pointers to Verb Table.
257 **/
258  UINT32 PchHdaVerbTablePtr;
259 
260 /** Offset 0x0091 - PCH HDA Codec Sx Wake Capability
261  Capability to detect wake initiated by a codec in Sx
262 **/
263  UINT8 PchHdaCodecSxWakeCapability;
264 
265 /** Offset 0x0092 - Enable SATA
266  Enable/disable SATA controller.
267  $EN_DIS
268 **/
269  UINT8 SataEnable;
270 
271 /** Offset 0x0093 - SATA Mode
272  Select SATA controller working mode.
273  0:AHCI, 1:RAID
274 **/
275  UINT8 SataMode;
276 
277 /** Offset 0x0094 - USB Per Port HS Preemphasis Bias
278  USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
279  100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
280 **/
281  UINT8 Usb2AfePetxiset[16];
282 
283 /** Offset 0x00A4 - USB Per Port HS Transmitter Bias
284  USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
285  100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
286 **/
287  UINT8 Usb2AfeTxiset[16];
288 
289 /** Offset 0x00B4 - USB Per Port HS Transmitter Emphasis
290  USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
291  10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
292 **/
293  UINT8 Usb2AfePredeemp[16];
294 
295 /** Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis
296  USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
297  One byte for each port.
298 **/
299  UINT8 Usb2AfePehalfbit[16];
300 
301 /** Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
302  Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
303  in arrary can be between 0-1. One byte for each port.
304 **/
305  UINT8 Usb3HsioTxDeEmphEnable[10];
306 
307 /** Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
308  USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
309  <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
310 **/
311  UINT8 Usb3HsioTxDeEmph[10];
312 
313 /** Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
314  Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
315  in arrary can be between 0-1. One byte for each port.
316 **/
317  UINT8 Usb3HsioTxDownscaleAmpEnable[10];
318 
319 /** Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment
320  USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
321  = 00h</b>. One byte for each port.
322 **/
323  UINT8 Usb3HsioTxDownscaleAmp[10];
324 
325 /** Offset 0x00FC - Enable LAN
326  Enable/disable LAN controller.
327  $EN_DIS
328 **/
329  UINT8 PchLanEnable;
330 
331 /** Offset 0x00FD - Enable HD Audio Link
332  Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
333  $EN_DIS
334 **/
335  UINT8 PchHdaAudioLinkHda;
336 
337 /** Offset 0x00FE - Enable HD Audio DMIC0 Link
338  Enable/disable HD Audio DMIC0 link. Muxed with SNDW4.
339  $EN_DIS
340 **/
341  UINT8 PchHdaAudioLinkDmic0;
342 
343 /** Offset 0x00FF - Enable HD Audio DMIC1 Link
344  Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
345  $EN_DIS
346 **/
347  UINT8 PchHdaAudioLinkDmic1;
348 
349 /** Offset 0x0100 - Enable HD Audio SSP0 Link
350  Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.
351  $EN_DIS
352 **/
353  UINT8 PchHdaAudioLinkSsp0;
354 
355 /** Offset 0x0101 - Enable HD Audio SSP1 Link
356  Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.
357  $EN_DIS
358 **/
359  UINT8 PchHdaAudioLinkSsp1;
360 
361 /** Offset 0x0102 - Enable HD Audio SSP2 Link
362  Enable/disable HD Audio SSP2/I2S link.
363  $EN_DIS
364 **/
365  UINT8 PchHdaAudioLinkSsp2;
366 
367 /** Offset 0x0103 - Enable HD Audio SoundWire#1 Link
368  Enable/disable HD Audio SNDW1 link. Muxed with HDA.
369  $EN_DIS
370 **/
371  UINT8 PchHdaAudioLinkSndw1;
372 
373 /** Offset 0x0104 - Enable HD Audio SoundWire#2 Link
374  Enable/disable HD Audio SNDW2 link. Muxed with SSP1.
375  $EN_DIS
376 **/
377  UINT8 PchHdaAudioLinkSndw2;
378 
379 /** Offset 0x0105 - Enable HD Audio SoundWire#3 Link
380  Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.
381  $EN_DIS
382 **/
383  UINT8 PchHdaAudioLinkSndw3;
384 
385 /** Offset 0x0106 - Enable HD Audio SoundWire#4 Link
386  Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.
387  $EN_DIS
388 **/
389  UINT8 PchHdaAudioLinkSndw4;
390 
391 /** Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting
392  0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.
393  $EN_DIS
394 **/
395  UINT8 PchHdaSndwBufferRcomp;
396 
397 /** Offset 0x0108 - PTM for PCIE RP Mask
398  Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
399  One bit for each port, bit0 for port1, bit1 for port2, and so on.
400 **/
401  UINT32 PcieRpPtmMask;
402 
403 /** Offset 0x010C - DPC for PCIE RP Mask
404  Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
405  One bit for each port, bit0 for port1, bit1 for port2, and so on.
406 **/
407  UINT32 PcieRpDpcMask;
408 
409 /** Offset 0x0110 - DPC Extensions PCIE RP Mask
410  Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
411  for each port, bit0 for port1, bit1 for port2, and so on.
412 **/
413  UINT32 PcieRpDpcExtensionsMask;
414 
415 /** Offset 0x0114 - USB PDO Programming
416  Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
417  during later phase. 1: enable, 0: disable
418  $EN_DIS
419 **/
420  UINT8 UsbPdoProgramming;
421 
422 /** Offset 0x0115 - Power button debounce configuration
423  Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
424  be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
425 **/
426  UINT32 PmcPowerButtonDebounce;
427 
428 /** Offset 0x0119 - PCH eSPI Master and Slave BME enabled
429  PCH eSPI Master and Slave BME enabled
430  $EN_DIS
431 **/
432  UINT8 PchEspiBmeMasterSlaveEnabled;
433 
434 /** Offset 0x011A - PCH SATA use RST Legacy OROM
435  Use PCH SATA RST Legacy OROM when CSM is Enabled
436  $EN_DIS
437 **/
438  UINT8 SataRstLegacyOrom;
439 
440 /** Offset 0x011B - Trace Hub Memory Base
441  If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
442  trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
443  memory is configured properly.
444 **/
445  UINT32 TraceHubMemBase;
446 
447 /** Offset 0x011F - PMC Debug Message Enable
448  When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
449  will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
450  $EN_DIS
451 **/
452  UINT8 PmcDbgMsgEn;
453 
454 /** Offset 0x0120 - Pointer of ChipsetInit Binary
455  ChipsetInit Binary Pointer.
456 **/
457  UINT32 ChipsetInitBinPtr;
458 
459 /** Offset 0x0124 - Length of ChipsetInit Binary
460  ChipsetInit Binary Length.
461 **/
462  UINT32 ChipsetInitBinLen;
463 
464 /** Offset 0x0128 - PchPostMemRsvd
465  Reserved for PCH Post-Mem
466  $EN_DIS
467 **/
468  UINT8 PchPostMemRsvd[29];
469 
470 /** Offset 0x0145 - Enable Ufs Controller
471  Enable/disable Ufs 2.0 Controller.
472  $EN_DIS
473 **/
474  UINT8 ScsUfsEnabled;
475 
476 /** Offset 0x0146 - CNVi Configuration
477  This option allows for automatic detection of Connectivity Solution. [Auto Detection]
478  assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
479  0:Disable, 1:Auto
480 **/
481  UINT8 PchCnviMode;
482 
483 /** Offset 0x0147 - SdCard power enable polarity
484  Choose SD_PWREN# polarity
485  0: Active low, 1: Active high
486 **/
487  UINT8 SdCardPowerEnableActiveHigh;
488 
489 /** Offset 0x0148 - PCH USB2 PHY Power Gating enable
490  1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
491  Sus Well PG
492  $EN_DIS
493 **/
494  UINT8 PchUsb2PhySusPgEnable;
495 
496 /** Offset 0x0149 - PCH USB OverCurrent mapping enable
497  1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
498  mapping allow for NOA usage of OC pins
499  $EN_DIS
500 **/
501  UINT8 PchUsbOverCurrentEnable;
502 
503 /** Offset 0x014A
504 **/
505  UINT8 UnusedUpdSpace3;
506 
507 /** Offset 0x014B - CNVi MfUart1 Type
508  This option configures Uart type which connects to MfUart1
509  0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads
510 **/
511  UINT8 PchCnviMfUart1Type;
512 
513 /** Offset 0x014C - Espi Lgmr Memory Range decode
514  This option enables or disables espi lgmr
515  $EN_DIS
516 **/
517  UINT8 PchEspiLgmrEnable;
518 
519 /** Offset 0x014D - HECI3 state
520  The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
521  0: disable, 1: enable
522  $EN_DIS
523 **/
524  UINT8 Heci3Enabled;
525 
526 /** Offset 0x014E
527 **/
528  UINT8 UnusedUpdSpace4;
529 
530 /** Offset 0x014F - PCHHOT# pin
531  Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
532  $EN_DIS
533 **/
534  UINT8 PchHotEnable;
535 
536 /** Offset 0x0150 - SATA LED
537  SATA LED indicating SATA controller activity. 0: disable, 1: enable
538  $EN_DIS
539 **/
540  UINT8 SataLedEnable;
541 
542 /** Offset 0x0151 - VRAlert# Pin
543  When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
544  to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
545  $EN_DIS
546 **/
547  UINT8 PchPmVrAlert;
548 
549 /** Offset 0x0152 - SLP_S0 VM Dynamic Control
550  SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable
551  $EN_DIS
552 **/
553  UINT8 PchPmSlpS0VmRuntimeControl;
554 
555 /** Offset 0x0153 - SLP_S0 VM 0.70V Support
556  SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable
557  $EN_DIS
558 **/
559  UINT8 PchPmSlpS0Vm070VSupport;
560 
561 /** Offset 0x0154 - SLP_S0 VM 0.75V Support
562  SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable
563  $EN_DIS
564 **/
565  UINT8 PchPmSlpS0Vm075VSupport;
566 
567 /** Offset 0x0155 - AMT Switch
568  Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
569  $EN_DIS
570 **/
571  UINT8 AmtEnabled;
572 
573 /** Offset 0x0156 - WatchDog Timer Switch
574  Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer.
575  $EN_DIS
576 **/
577  UINT8 WatchDog;
578 
579 /** Offset 0x0157 - ASF Switch
580  Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality.
581  $EN_DIS
582 **/
583  UINT8 AsfEnabled;
584 
585 /** Offset 0x0158 - Manageability Mode set by Mebx
586  Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
587  $EN_DIS
588 **/
589  UINT8 ManageabilityMode;
590 
591 /** Offset 0x0159 - PET Progress
592  Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
593  PET Events.
594  $EN_DIS
595 **/
596  UINT8 FwProgress;
597 
598 /** Offset 0x015A - SOL Switch
599  Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx
600  $EN_DIS
601 **/
602  UINT8 AmtSolEnabled;
603 
604 /** Offset 0x015B - OS Timer
605  16 bits Value, Set OS watchdog timer.
606  $EN_DIS
607 **/
608  UINT16 WatchDogTimerOs;
609 
610 /** Offset 0x015D - BIOS Timer
611  16 bits Value, Set BIOS watchdog timer.
612  $EN_DIS
613 **/
614  UINT16 WatchDogTimerBios;
615 
616 /** Offset 0x015F - Remote Assistance Trigger Availablilty
617  Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx
618  $EN_DIS
619 **/
620  UINT8 RemoteAssistance;
621 
622 /** Offset 0x0160 - KVM Switch
623  Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx
624  $EN_DIS
625 **/
626  UINT8 AmtKvmEnabled;
627 
628 /** Offset 0x0161 - MEBX execution
629  Enable/Disable. 0: Disable, 1: enable, Force MEBX execution
630  $EN_DIS
631 **/
632  UINT8 ForcMebxSyncUp;
633 
634 /** Offset 0x0162
635 **/
636  UINT8 UnusedUpdSpace5[1];
637 
638 /** Offset 0x0163 - PCH PCIe root port connection type
639  0: built-in device, 1:slot
640 **/
641  UINT8 PcieRpSlotImplemented[24];
642 
643 /** Offset 0x017B - Usage type for ClkSrc
644  0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
645  (free running), 0xFF: not used
646 **/
647  UINT8 PcieClkSrcUsage[16];
648 
649 /** Offset 0x018B - ClkReq-to-ClkSrc mapping
650  Number of ClkReq signal assigned to ClkSrc
651 **/
652  UINT8 PcieClkSrcClkReq[16];
653 
654 /** Offset 0x019B - PCIE RP Access Control Services Extended Capability
655  Enable/Disable PCIE RP Access Control Services Extended Capability
656 **/
657  UINT8 PcieRpAcsEnabled[24];
658 
659 /** Offset 0x01B3 - PCIE RP Clock Power Management
660  Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
661  can still be controlled by L1 PM substates mechanism
662 **/
663  UINT8 PcieRpEnableCpm[24];
664 
665 /** Offset 0x01CB - PCIE RP Detect Timeout Ms
666  The number of milliseconds within 0~65535 in reference code will wait for link to
667  exit Detect state for enabled ports before assuming there is no device and potentially
668  disabling the port.
669 **/
670  UINT16 PcieRpDetectTimeoutMs[24];
671 
672 /** Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating
673  Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
674  PCH-H. 0: disable, 1: enable
675  $EN_DIS
676 **/
677  UINT8 PmcModPhySusPgEnable;
678 
679 /** Offset 0x01FC - SlpS0WithGbeSupport
680  Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable
681  $EN_DIS
682 **/
683  UINT8 SlpS0WithGbeSupport;
684 
685 /** Offset 0x01FD
686 **/
687  UINT8 UnusedUpdSpace6[3];
688 
689 /** Offset 0x0200 - Enable/Disable SA CRID
690  Enable: SA CRID, Disable (Default): SA CRID
691  $EN_DIS
692 **/
693  UINT8 CridEnable;
694 
695 /** Offset 0x0201 - DMI ASPM
696  0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1
697  0:Disable, 1:L0s, 2:L1, 3:L0sL1
698 **/
699  UINT8 DmiAspm;
700 
701 /** Offset 0x0202 - PCIe DeEmphasis control per root port
702  0: -6dB, 1(Default): -3.5dB
703  0:-6dB, 1:-3.5dB
704 **/
705  UINT8 PegDeEmphasis[4];
706 
707 /** Offset 0x0206 - PCIe Slot Power Limit value per root port
708  Slot power limit value per root port
709 **/
710  UINT8 PegSlotPowerLimitValue[4];
711 
712 /** Offset 0x020A - PCIe Slot Power Limit scale per root port
713  Slot power limit scale per root port
714  0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
715 **/
716  UINT8 PegSlotPowerLimitScale[4];
717 
718 /** Offset 0x020E - PCIe Physical Slot Number per root port
719  Physical Slot Number per root port
720 **/
721  UINT16 PegPhysicalSlotNumber[4];
722 
723 /** Offset 0x0216 - Enable/Disable PavpEnable
724  Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
725  $EN_DIS
726 **/
727  UINT8 PavpEnable;
728 
729 /** Offset 0x0217 - CdClock Frequency selection
730  0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz
731  0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz
732 **/
733  UINT8 CdClock;
734 
735 /** Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit
736  Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
737  $EN_DIS
738 **/
739  UINT8 PeiGraphicsPeimInit;
740 
741 /** Offset 0x0219
742 **/
743  UINT8 UnusedUpdSpace7;
744 
745 /** Offset 0x021A - Enable or disable GNA device
746  0=Disable, 1(Default)=Enable
747  $EN_DIS
748 **/
749  UINT8 GnaEnable;
750 
751 /** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table
752  0=Disable/Clear, 1=Enable/Set
753  $EN_DIS
754 **/
755  UINT8 X2ApicOptOut;
756 
757 /** Offset 0x021C - Base addresses for VT-d function MMIO access
758  Base addresses for VT-d MMIO access per VT-d engine
759 **/
760  UINT32 VtdBaseAddress[3];
761 
762 /** Offset 0x0228 - Enable or disable eDP device
763  0=Disable, 1(Default)=Enable
764  $EN_DIS
765 **/
766  UINT8 DdiPortEdp;
767 
768 /** Offset 0x0229 - Enable or disable HPD of DDI port B
769  0=Disable, 1(Default)=Enable
770  $EN_DIS
771 **/
772  UINT8 DdiPortBHpd;
773 
774 /** Offset 0x022A - Enable or disable HPD of DDI port C
775  0=Disable, 1(Default)=Enable
776  $EN_DIS
777 **/
778  UINT8 DdiPortCHpd;
779 
780 /** Offset 0x022B - Enable or disable HPD of DDI port D
781  0=Disable, 1(Default)=Enable
782  $EN_DIS
783 **/
784  UINT8 DdiPortDHpd;
785 
786 /** Offset 0x022C - Enable or disable HPD of DDI port F
787  0=Disable, 1(Default)=Enable
788  $EN_DIS
789 **/
790  UINT8 DdiPortFHpd;
791 
792 /** Offset 0x022D - Enable or disable DDC of DDI port B
793  0=Disable, 1(Default)=Enable
794  $EN_DIS
795 **/
796  UINT8 DdiPortBDdc;
797 
798 /** Offset 0x022E - Enable or disable DDC of DDI port C
799  0=Disable, 1(Default)=Enable
800  $EN_DIS
801 **/
802  UINT8 DdiPortCDdc;
803 
804 /** Offset 0x022F - Enable or disable DDC of DDI port D
805  0=Disable, 1(Default)=Enable
806  $EN_DIS
807 **/
808  UINT8 DdiPortDDdc;
809 
810 /** Offset 0x0230 - Enable or disable DDC of DDI port F
811  0(Default)=Disable, 1=Enable
812  $EN_DIS
813 **/
814  UINT8 DdiPortFDdc;
815 
816 /** Offset 0x0231 - Enable/Disable SkipS3CdClockInit
817  Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
818  CD clock in S3 resume due to GOP absent
819  $EN_DIS
820 **/
821  UINT8 SkipS3CdClockInit;
822 
823 /** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms
824  Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate
825  T12 Delay to max 500ms
826  0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
827 **/
828  UINT16 DeltaT12PowerCycleDelay;
829 
830 /** Offset 0x0234 - Blt Buffer Address
831  Address of Blt buffer
832 **/
833  UINT32 BltBufferAddress;
834 
835 /** Offset 0x0238 - Blt Buffer Size
836  Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
837  EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
838 **/
839  UINT32 BltBufferSize;
840 
841 /** Offset 0x023C - SaPostMemProductionRsvd
842  Reserved for SA Post-Mem Production
843  $EN_DIS
844 **/
845  UINT8 SaPostMemProductionRsvd[35];
846 
847 /** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable
848  PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for
849  Alpine ridge
850 **/
851  UINT8 PcieRootPortGen2PllL1CgDisable[24];
852 
853 /** Offset 0x0277 - Advanced Encryption Standard (AES) feature
854  Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
855  $EN_DIS
856 **/
857  UINT8 AesEnable;
858 
859 /** Offset 0x0278 - Power State 3 enable/disable
860  PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
861  For all VR Indexes
862 **/
863  UINT8 Psi3Enable[5];
864 
865 /** Offset 0x027D - Power State 4 enable/disable
866  PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
867  all VR Indexes
868 **/
869  UINT8 Psi4Enable[5];
870 
871 /** Offset 0x0282 - Imon slope correction
872  PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
873  Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
874 **/
875  UINT8 ImonSlope[5];
876 
877 /** Offset 0x0287 - Imon offset correction
878  PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
879  Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
880 **/
881  UINT8 ImonOffset[5];
882 
883 /** Offset 0x028C - Enable/Disable BIOS configuration of VR
884  Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
885 **/
886  UINT8 VrConfigEnable[5];
887 
888 /** Offset 0x0291 - Thermal Design Current enable/disable
889  PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
890  Enable.For all VR Indexes
891 **/
892  UINT8 TdcEnable[5];
893 
894 /** Offset 0x0296 - HECI3 state
895  PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
896  Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms
897  , 8 - 8ms , 10 - 10ms.For all VR Indexe
898 **/
899  UINT8 TdcTimeWindow[5];
900 
901 /** Offset 0x029B - Thermal Design Current Lock
902  PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
903  all VR Indexes
904 **/
905  UINT8 TdcLock[5];
906 
907 /** Offset 0x02A0 - Platform Psys slope correction
908  PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
909  1/100 increment values. Range is 0-200. 125 = 1.25
910 **/
911  UINT8 PsysSlope;
912 
913 /** Offset 0x02A1 - Platform Psys offset correction
914  PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,
915  Range 0-255. Value of 100 = 100/4 = 25 offset
916 **/
917  UINT8 PsysOffset;
918 
919 /** Offset 0x02A2 - Acoustic Noise Mitigation feature
920  Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program
921  slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.<b>0:
922  Disabled</b>; 1: Enabled
923  $EN_DIS
924 **/
925  UINT8 AcousticNoiseMitigation;
926 
927 /** Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain
928  Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
929  feature enabled. <b>0: False</b>; 1: True
930  $EN_DIS
931 **/
932  UINT8 FastPkgCRampDisableIa;
933 
934 /** Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain
935  Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic
936  Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
937  0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
938 **/
939  UINT8 SlowSlewRateForIa;
940 
941 /** Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain
942  Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic
943  Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
944  0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
945 **/
946  UINT8 SlowSlewRateForGt;
947 
948 /** Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain
949  Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic
950  Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
951  0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
952 **/
953  UINT8 SlowSlewRateForSa;
954 
955 /** Offset 0x02A7 - Thermal Design Current current limit
956  PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
957  Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
958 **/
959  UINT16 TdcPowerLimit[5];
960 
961 /** Offset 0x02B1 - AcLoadline
962  PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
963  0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
964 **/
965  UINT16 AcLoadline[5];
966 
967 /** Offset 0x02BB
968 **/
969  UINT8 UnusedUpdSpace8[10];
970 
971 /** Offset 0x02C5 - DcLoadline
972  PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
973  0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
974 **/
975  UINT16 DcLoadline[5];
976 
977 /** Offset 0x02CF - Power State 1 Threshold current
978  PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
979 **/
980  UINT16 Psi1Threshold[5];
981 
982 /** Offset 0x02D9 - Power State 2 Threshold current
983  PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
984 **/
985  UINT16 Psi2Threshold[5];
986 
987 /** Offset 0x02E3 - Power State 3 Threshold current
988  PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
989 **/
990  UINT16 Psi3Threshold[5];
991 
992 /** Offset 0x02ED - Icc Max limit
993  PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
994 **/
995  UINT16 IccMax[5];
996 
997 /** Offset 0x02F7 - VR Voltage Limit
998  PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
999 **/
1000  UINT16 VrVoltageLimit[5];
1001 
1002 /** Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain
1003  Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
1004  feature enabled. <b>0: False</b>; 1: True
1005  $EN_DIS
1006 **/
1007  UINT8 FastPkgCRampDisableGt;
1008 
1009 /** Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
1010  Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
1011  feature enabled. <b>0: False</b>; 1: True
1012  $EN_DIS
1013 **/
1014  UINT8 FastPkgCRampDisableSa;
1015 
1016 /** Offset 0x0303 - Enable VR specific mailbox command
1017  VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
1018  VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
1019  command sent for PS4 exit issue. 11b - Reserved.
1020  $EN_DIS
1021 **/
1022  UINT8 SendVrMbxCmd;
1023 
1024 /** Offset 0x0304 - Reserved
1025  Reserved
1026 **/
1027  UINT8 Reserved2;
1028 
1029 /** Offset 0x0305 - Enable or Disable TXT
1030  Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.
1031  $EN_DIS
1032 **/
1033  UINT8 TxtEnable;
1034 
1035 /** Offset 0x0306
1036 **/
1037  UINT8 UnusedUpdSpace9[6];
1038 
1039 /** Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization
1040  @deprecated SkipMpInit has been moved to FspmUpd
1041  $EN_DIS
1042 **/
1043  UINT8 SkipMpInit;
1044 
1045 /** Offset 0x030D - McIVR RFI Frequency Prefix
1046  PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. <b>0: Plus (+)</b>; 1:
1047  Minus (-).
1048 **/
1049  UINT8 McivrRfiFrequencyPrefix;
1050 
1051 /** Offset 0x030E - McIVR RFI Frequency Adjustment
1052  PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in
1053  increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>.
1054 **/
1055  UINT8 McivrRfiFrequencyAdjust;
1056 
1057 /** Offset 0x030F - FIVR RFI Frequency
1058  PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:
1059  Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
1060  0-1535 (Up to 153.5MHz) for 19MHz clock.
1061 **/
1062  UINT16 FivrRfiFrequency;
1063 
1064 /** Offset 0x0311 - McIVR RFI Spread Spectrum
1065  PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/-
1066  1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.
1067 **/
1068  UINT8 McivrSpreadSpectrum;
1069 
1070 /** Offset 0x0312 - FIVR RFI Spread Spectrum
1071  PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;
1072  Range: 0.0% to 10.0% (0-100).
1073 **/
1074  UINT8 FivrSpreadSpectrum;
1075 
1076 /** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain
1077  Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
1078  feature enabled. <b>0: False</b>; 1: True
1079  $EN_DIS
1080 **/
1081  UINT8 FastPkgCRampDisableFivr;
1082 
1083 /** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain
1084  Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic
1085  Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
1086  0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
1087 **/
1088  UINT8 SlowSlewRateForFivr;
1089 
1090 /** Offset 0x0315 - CpuBistData
1091  Pointer CPU BIST Data
1092 **/
1093  UINT32 CpuBistData;
1094 
1095 /** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.
1096  Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox
1097  command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
1098 **/
1099  UINT8 IslVrCmd;
1100 
1101 /** Offset 0x031A - Imon slope1 correction
1102  PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
1103  Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
1104 **/
1105  UINT16 ImonSlope1[5];
1106 
1107 /** Offset 0x0324 - CPU VR Power Delivery Design
1108  Used to communicate the power delivery design capability of the board. This value
1109  is an enum of the available power delivery segments that are defined in the Platform
1110  Design Guide.
1111 **/
1112  UINT32 VrPowerDeliveryDesign;
1113 
1114 /** Offset 0x0328 - Pre Wake Randomization time
1115  PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization
1116  time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.
1117  Range 0-255 <b>0</b>.
1118 **/
1119  UINT8 PreWake;
1120 
1121 /** Offset 0x0329 - Ramp Up Randomization time
1122  PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization
1123  time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
1124  0-255 <b>0</b>.
1125 **/
1126  UINT8 RampUp;
1127 
1128 /** Offset 0x032A - Ramp Down Randomization time
1129  PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization
1130  time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
1131  0-255 <b>0</b>.
1132 **/
1133  UINT8 RampDown;
1134 
1135 /** Offset 0x032B - CpuMpPpi
1136  Pointer for CpuMpPpi
1137 **/
1138  UINT32 CpuMpPpi;
1139 
1140 /** Offset 0x032F - CpuMpHob
1141  Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage.
1142 **/
1143  UINT32 CpuMpHob;
1144 
1145 /** Offset 0x0333 - Enable or Disable processor debug features
1146  Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
1147  $EN_DIS
1148 **/
1149  UINT8 DebugInterfaceEnable;
1150 
1151 /** Offset 0x0334 - ReservedCpuPostMemProduction
1152  Reserved for CPU Post-Mem Production
1153  $EN_DIS
1154 **/
1155  UINT8 ReservedCpuPostMemProduction[18];
1156 
1157 /** Offset 0x0346 - Enable DMI ASPM
1158  Deprecated.
1159  $EN_DIS
1160 **/
1161  UINT8 PchDmiAspm;
1162 
1163 /** Offset 0x0347 - Enable Power Optimizer
1164  Enable DMI Power Optimizer on PCH side.
1165  $EN_DIS
1166 **/
1167  UINT8 PchPwrOptEnable;
1168 
1169 /** Offset 0x0348 - PCH Flash Protection Ranges Write Enble
1170  Write or erase is blocked by hardware.
1171 **/
1172  UINT8 PchWriteProtectionEnable[5];
1173 
1174 /** Offset 0x034D - PCH Flash Protection Ranges Read Enble
1175  Read is blocked by hardware.
1176 **/
1177  UINT8 PchReadProtectionEnable[5];
1178 
1179 /** Offset 0x0352 - PCH Protect Range Limit
1180  Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
1181  limit comparison.
1182 **/
1183  UINT16 PchProtectedRangeLimit[5];
1184 
1185 /** Offset 0x035C - PCH Protect Range Base
1186  Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
1187 **/
1188  UINT16 PchProtectedRangeBase[5];
1189 
1190 /** Offset 0x0366 - Enable Pme
1191  Enable Azalia wake-on-ring.
1192  $EN_DIS
1193 **/
1194  UINT8 PchHdaPme;
1195 
1196 /** Offset 0x0367
1197 **/
1198  UINT8 UnusedUpdSpace10;
1199 
1200 /** Offset 0x0368 - VC Type
1201  Virtual Channel Type Select: 0: VC0, 1: VC1.
1202  0: VC0, 1: VC1
1203 **/
1204  UINT8 PchHdaVcType;
1205 
1206 /** Offset 0x0369 - HD Audio Link Frequency
1207  HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
1208  0: 6MHz, 1: 12MHz, 2: 24MHz
1209 **/
1210  UINT8 PchHdaLinkFrequency;
1211 
1212 /** Offset 0x036A - iDisp-Link Frequency
1213  iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
1214  4: 96MHz, 3: 48MHz
1215 **/
1216  UINT8 PchHdaIDispLinkFrequency;
1217 
1218 /** Offset 0x036B - iDisp-Link T-mode
1219  iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
1220  0: 2T, 1: 1T
1221 **/
1222  UINT8 PchHdaIDispLinkTmode;
1223 
1224 /** Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system
1225  0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
1226  driver or SST driver supported).
1227  $EN_DIS
1228 **/
1229  UINT8 PchHdaDspUaaCompliance;
1230 
1231 /** Offset 0x036D - iDisplay Audio Codec disconnection
1232  0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
1233  $EN_DIS
1234 **/
1235  UINT8 PchHdaIDispCodecDisconnect;
1236 
1237 /** Offset 0x036E - USB LFPS Filter selection
1238  For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns,
1239  3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns.
1240 **/
1241  UINT8 PchUsbHsioFilterSel[10];
1242 
1243 /** Offset 0x0378
1244 **/
1245  UINT8 UnusedUpdSpace11[5];
1246 
1247 /** Offset 0x037D - Enable PCH Io Apic Entry 24-119
1248  0: Disable; 1: Enable.
1249  $EN_DIS
1250 **/
1251  UINT8 PchIoApicEntry24_119;
1252 
1253 /** Offset 0x037E - PCH Io Apic ID
1254  This member determines IOAPIC ID. Default is 0x02.
1255 **/
1256  UINT8 PchIoApicId;
1257 
1258 /** Offset 0x037F
1259 **/
1260  UINT8 UnusedUpdSpace12;
1261 
1262 /** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned
1263  0: Disable; 1: Enable.
1264  $EN_DIS
1265 **/
1266  UINT8 PchIshSpiGpioAssign;
1267 
1268 /** Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned
1269  0: Disable; 1: Enable.
1270  $EN_DIS
1271 **/
1272  UINT8 PchIshUart0GpioAssign;
1273 
1274 /** Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned
1275  0: Disable; 1: Enable.
1276  $EN_DIS
1277 **/
1278  UINT8 PchIshUart1GpioAssign;
1279 
1280 /** Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned
1281  0: Disable; 1: Enable.
1282  $EN_DIS
1283 **/
1284  UINT8 PchIshI2c0GpioAssign;
1285 
1286 /** Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned
1287  0: Disable; 1: Enable.
1288  $EN_DIS
1289 **/
1290  UINT8 PchIshI2c1GpioAssign;
1291 
1292 /** Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned
1293  0: Disable; 1: Enable.
1294  $EN_DIS
1295 **/
1296  UINT8 PchIshI2c2GpioAssign;
1297 
1298 /** Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned
1299  0: Disable; 1: Enable.
1300  $EN_DIS
1301 **/
1302  UINT8 PchIshGp0GpioAssign;
1303 
1304 /** Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned
1305  0: Disable; 1: Enable.
1306  $EN_DIS
1307 **/
1308  UINT8 PchIshGp1GpioAssign;
1309 
1310 /** Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned
1311  0: Disable; 1: Enable.
1312  $EN_DIS
1313 **/
1314  UINT8 PchIshGp2GpioAssign;
1315 
1316 /** Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned
1317  0: Disable; 1: Enable.
1318  $EN_DIS
1319 **/
1320  UINT8 PchIshGp3GpioAssign;
1321 
1322 /** Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned
1323  0: Disable; 1: Enable.
1324  $EN_DIS
1325 **/
1326  UINT8 PchIshGp4GpioAssign;
1327 
1328 /** Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned
1329  0: Disable; 1: Enable.
1330  $EN_DIS
1331 **/
1332  UINT8 PchIshGp5GpioAssign;
1333 
1334 /** Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned
1335  0: Disable; 1: Enable.
1336  $EN_DIS
1337 **/
1338  UINT8 PchIshGp6GpioAssign;
1339 
1340 /** Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned
1341  0: Disable; 1: Enable.
1342  $EN_DIS
1343 **/
1344  UINT8 PchIshGp7GpioAssign;
1345 
1346 /** Offset 0x038E - PCH ISH PDT Unlock Msg
1347  0: False; 1: True.
1348  $EN_DIS
1349 **/
1350  UINT8 PchIshPdtUnlock;
1351 
1352 /** Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN
1353  0: Disable; 1: Enable.
1354  $EN_DIS
1355 **/
1356  UINT8 PchLanLtrEnable;
1357 
1358 /** Offset 0x0390
1359 **/
1360  UINT8 UnusedUpdSpace13[3];
1361 
1362 /** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK
1363  Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
1364  protection.
1365  $EN_DIS
1366 **/
1367  UINT8 PchLockDownBiosLock;
1368 
1369 /** Offset 0x0394 - PCH Compatibility Revision ID
1370  This member describes whether or not the CRID feature of PCH should be enabled.
1371  $EN_DIS
1372 **/
1373  UINT8 PchCrid;
1374 
1375 /** Offset 0x0395 - RTC CMOS MEMORY LOCK
1376  Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
1377  and and lower 128-byte bank of RTC RAM.
1378  $EN_DIS
1379 **/
1380  UINT8 PchLockDownRtcMemoryLock;
1381 
1382 /** Offset 0x0396 - Enable PCIE RP HotPlug
1383  Indicate whether the root port is hot plug available.
1384 **/
1385  UINT8 PcieRpHotPlug[24];
1386 
1387 /** Offset 0x03AE - Enable PCIE RP Pm Sci
1388  Indicate whether the root port power manager SCI is enabled.
1389 **/
1390  UINT8 PcieRpPmSci[24];
1391 
1392 /** Offset 0x03C6 - Enable PCIE RP Ext Sync
1393  Indicate whether the extended synch is enabled.
1394 **/
1395  UINT8 PcieRpExtSync[24];
1396 
1397 /** Offset 0x03DE - Enable PCIE RP Transmitter Half Swing
1398  Indicate whether the Transmitter Half Swing is enabled.
1399 **/
1400  UINT8 PcieRpTransmitterHalfSwing[24];
1401 
1402 /** Offset 0x03F6 - Enable PCIE RP Clk Req Detect
1403  Probe CLKREQ# signal before enabling CLKREQ# based power management.
1404 **/
1405  UINT8 PcieRpClkReqDetect[24];
1406 
1407 /** Offset 0x040E - PCIE RP Advanced Error Report
1408  Indicate whether the Advanced Error Reporting is enabled.
1409 **/
1410  UINT8 PcieRpAdvancedErrorReporting[24];
1411 
1412 /** Offset 0x0426 - PCIE RP Unsupported Request Report
1413  Indicate whether the Unsupported Request Report is enabled.
1414 **/
1415  UINT8 PcieRpUnsupportedRequestReport[24];
1416 
1417 /** Offset 0x043E - PCIE RP Fatal Error Report
1418  Indicate whether the Fatal Error Report is enabled.
1419 **/
1420  UINT8 PcieRpFatalErrorReport[24];
1421 
1422 /** Offset 0x0456 - PCIE RP No Fatal Error Report
1423  Indicate whether the No Fatal Error Report is enabled.
1424 **/
1425  UINT8 PcieRpNoFatalErrorReport[24];
1426 
1427 /** Offset 0x046E - PCIE RP Correctable Error Report
1428  Indicate whether the Correctable Error Report is enabled.
1429 **/
1430  UINT8 PcieRpCorrectableErrorReport[24];
1431 
1432 /** Offset 0x0486 - PCIE RP System Error On Fatal Error
1433  Indicate whether the System Error on Fatal Error is enabled.
1434 **/
1435  UINT8 PcieRpSystemErrorOnFatalError[24];
1436 
1437 /** Offset 0x049E - PCIE RP System Error On Non Fatal Error
1438  Indicate whether the System Error on Non Fatal Error is enabled.
1439 **/
1440  UINT8 PcieRpSystemErrorOnNonFatalError[24];
1441 
1442 /** Offset 0x04B6 - PCIE RP System Error On Correctable Error
1443  Indicate whether the System Error on Correctable Error is enabled.
1444 **/
1445  UINT8 PcieRpSystemErrorOnCorrectableError[24];
1446 
1447 /** Offset 0x04CE - PCIE RP Max Payload
1448  Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
1449 **/
1450  UINT8 PcieRpMaxPayload[24];
1451 
1452 /** Offset 0x04E6 - PCH USB3 RX HSIO Tuning parameters
1453  Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for
1454  controlling the input offset
1455 **/
1456  UINT8 PchUsbHsioRxTuningParameters[10];
1457 
1458 /** Offset 0x04F0 - PCH USB3 HSIO Rx Tuning Enable
1459  Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable,
1460  1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable
1461 **/
1462  UINT8 PchUsbHsioRxTuningEnable[10];
1463 
1464 /** Offset 0x04FA
1465 **/
1466  UINT8 UnusedUpdSpace14[4];
1467 
1468 /** Offset 0x04FE - PCIE RP Pcie Speed
1469  Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
1470  PCH_PCIE_SPEED).
1471 **/
1472  UINT8 PcieRpPcieSpeed[24];
1473 
1474 /** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method
1475  PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
1476  1: hardware equalization; 4: Fixed Coeficients.
1477 **/
1478  UINT8 PcieRpGen3EqPh3Method[24];
1479 
1480 /** Offset 0x052E - PCIE RP Physical Slot Number
1481  Indicates the slot number for the root port. Default is the value as root port index.
1482 **/
1483  UINT8 PcieRpPhysicalSlotNumber[24];
1484 
1485 /** Offset 0x0546 - PCIE RP Completion Timeout
1486  The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
1487 **/
1488  UINT8 PcieRpCompletionTimeout[24];
1489 
1490 /** Offset 0x055E
1491 **/
1492  UINT8 UnusedUpdSpace15[106];
1493 
1494 /** Offset 0x05C8 - PCIE RP Aspm
1495  The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
1496  PchPcieAspmAutoConfig.
1497 **/
1498  UINT8 PcieRpAspm[24];
1499 
1500 /** Offset 0x05E0 - PCIE RP L1 Substates
1501  The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
1502  Default is PchPcieL1SubstatesL1_1_2.
1503 **/
1504  UINT8 PcieRpL1Substates[24];
1505 
1506 /** Offset 0x05F8 - PCIE RP Ltr Enable
1507  Latency Tolerance Reporting Mechanism.
1508 **/
1509  UINT8 PcieRpLtrEnable[24];
1510 
1511 /** Offset 0x0610 - PCIE RP Ltr Config Lock
1512  0: Disable; 1: Enable.
1513 **/
1514  UINT8 PcieRpLtrConfigLock[24];
1515 
1516 /** Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm
1517  PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.
1518 **/
1519  UINT8 PcieEqPh3LaneParamCm[24];
1520 
1521 /** Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp
1522  PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.
1523 **/
1524  UINT8 PcieEqPh3LaneParamCp[24];
1525 
1526 /** Offset 0x0658 - PCIE Sw Eq CoeffList Cm
1527  PCH_PCIE_EQ_PARAM. Coefficient C-1.
1528 **/
1529  UINT8 PcieSwEqCoeffListCm[5];
1530 
1531 /** Offset 0x065D - PCIE Sw Eq CoeffList Cp
1532  PCH_PCIE_EQ_PARAM. Coefficient C+1.
1533 **/
1534  UINT8 PcieSwEqCoeffListCp[5];
1535 
1536 /** Offset 0x0662 - PCIE Disable RootPort Clock Gating
1537  Describes whether the PCI Express Clock Gating for each root port is enabled by
1538  platform modules. 0: Disable; 1: Enable.
1539  $EN_DIS
1540 **/
1541  UINT8 PcieDisableRootPortClockGating;
1542 
1543 /** Offset 0x0663 - PCIE Enable Peer Memory Write
1544  This member describes whether Peer Memory Writes are enabled on the platform.
1545  $EN_DIS
1546 **/
1547  UINT8 PcieEnablePeerMemoryWrite;
1548 
1549 /** Offset 0x0664
1550 **/
1551  UINT8 UnusedUpdSpace16;
1552 
1553 /** Offset 0x0665 - PCIE Compliance Test Mode
1554  Compliance Test Mode shall be enabled when using Compliance Load Board.
1555  $EN_DIS
1556 **/
1557  UINT8 PcieComplianceTestMode;
1558 
1559 /** Offset 0x0666 - PCIE Rp Function Swap
1560  Allows BIOS to use root port function number swapping when root port of function
1561  0 is disabled.
1562  $EN_DIS
1563 **/
1564  UINT8 PcieRpFunctionSwap;
1565 
1566 /** Offset 0x0667 - Teton Glacier Support
1567  Enables support for the Teton Glacier card.
1568  $EN_DIS
1569 **/
1570  UINT8 TetonGlacierSupport;
1571 
1572 /** Offset 0x0668 - Teton Glacier Cycle Router
1573  Specify to which cycle router Teton Glacier is connected, it is valid only when
1574  Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system
1575 **/
1576  UINT8 TetonGlacierCR;
1577 
1578 /** Offset 0x0669 - PCH Pm PME_B0_S5_DIS
1579  When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
1580  $EN_DIS
1581 **/
1582  UINT8 PchPmPmeB0S5Dis;
1583 
1584 /** Offset 0x066A - SPI ChipSelect signal polarity
1585  Selects SPI ChipSelect signal polarity.
1586 **/
1587  UINT8 SerialIoSpiCsPolarity[3];
1588 
1589 /** Offset 0x066D - PCIE IMR
1590  Enables Isolated Memory Region for PCIe.
1591  $EN_DIS
1592 **/
1593  UINT8 PcieRpImrEnabled;
1594 
1595 /** Offset 0x066E - PCIE IMR port number
1596  Selects PCIE root port number for IMR feature.
1597 **/
1598  UINT8 PcieRpImrSelection;
1599 
1600 /** Offset 0x066F
1601 **/
1602  UINT8 UnusedUpdSpace17;
1603 
1604 /** Offset 0x0670 - PCH Pm Wol Enable Override
1605  Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
1606  $EN_DIS
1607 **/
1608  UINT8 PchPmWolEnableOverride;
1609 
1610 /** Offset 0x0671 - PCH Pm Pcie Wake From DeepSx
1611  Determine if enable PCIe to wake from deep Sx.
1612  $EN_DIS
1613 **/
1614  UINT8 PchPmPcieWakeFromDeepSx;
1615 
1616 /** Offset 0x0672 - PCH Pm WoW lan Enable
1617  Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
1618  $EN_DIS
1619 **/
1620  UINT8 PchPmWoWlanEnable;
1621 
1622 /** Offset 0x0673 - PCH Pm WoW lan DeepSx Enable
1623  Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
1624  PWRM_CFG3 register.
1625  $EN_DIS
1626 **/
1627  UINT8 PchPmWoWlanDeepSxEnable;
1628 
1629 /** Offset 0x0674 - PCH Pm Lan Wake From DeepSx
1630  Determine if enable LAN to wake from deep Sx.
1631  $EN_DIS
1632 **/
1633  UINT8 PchPmLanWakeFromDeepSx;
1634 
1635 /** Offset 0x0675 - PCH Pm Deep Sx Pol
1636  Deep Sx Policy.
1637  $EN_DIS
1638 **/
1639  UINT8 PchPmDeepSxPol;
1640 
1641 /** Offset 0x0676 - PCH Pm Slp S3 Min Assert
1642  SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
1643 **/
1644  UINT8 PchPmSlpS3MinAssert;
1645 
1646 /** Offset 0x0677 - PCH Pm Slp S4 Min Assert
1647  SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
1648 **/
1649  UINT8 PchPmSlpS4MinAssert;
1650 
1651 /** Offset 0x0678 - PCH Pm Slp Sus Min Assert
1652  SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
1653 **/
1654  UINT8 PchPmSlpSusMinAssert;
1655 
1656 /** Offset 0x0679 - PCH Pm Slp A Min Assert
1657  SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
1658 **/
1659  UINT8 PchPmSlpAMinAssert;
1660 
1661 /** Offset 0x067A - SLP_S0# Override
1662  Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled'
1663  will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion
1664  when debug is enabled. \n
1665  Note: This BIOS option should keep 'Auto', other options are intended for advanced
1666  configuration only.
1667  0:Disabled, 1:Enabled, 2:Auto
1668 **/
1669  UINT8 SlpS0Override;
1670 
1671 /** Offset 0x067B - S0ix Override Settings
1672  Select 'Auto', it will be auto-configured according to probe type. 'No Change' will
1673  keep PMC default settings. Or select the desired debug probe type for S0ix Override
1674  settings.\n
1675  Reminder: DCI OOB (aka BSSB) uses CCA probe.\n
1676  Note: This BIOS option should keep 'Auto', other options are intended for advanced
1677  configuration only.
1678  0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto
1679 **/
1680  UINT8 SlpS0DisQForDebug;
1681 
1682 /** Offset 0x067C - USB Overcurrent Override for DbC
1683  This option overrides USB Over Current enablement state that USB OC will be disabled
1684  after enabling this option. Enable when DbC is used to avoid signaling conflicts.
1685  $EN_DIS
1686 **/
1687  UINT8 PchEnableDbcObs;
1688 
1689 /** Offset 0x067D
1690 **/
1691  UINT8 UnusedUpdSpace18[3];
1692 
1693 /** Offset 0x0680 - PCH Pm Lpc Clock Run
1694  This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
1695  Default value is Disabled
1696  $EN_DIS
1697 **/
1698  UINT8 PchPmLpcClockRun;
1699 
1700 /** Offset 0x0681 - PCH Pm Slp Strch Sus Up
1701  Enable SLP_X Stretching After SUS Well Power Up.
1702  $EN_DIS
1703 **/
1704  UINT8 PchPmSlpStrchSusUp;
1705 
1706 /** Offset 0x0682 - PCH Pm Slp Lan Low Dc
1707  Enable/Disable SLP_LAN# Low on DC Power.
1708  $EN_DIS
1709 **/
1710  UINT8 PchPmSlpLanLowDc;
1711 
1712 /** Offset 0x0683 - PCH Pm Pwr Btn Override Period
1713  PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
1714 **/
1715  UINT8 PchPmPwrBtnOverridePeriod;
1716 
1717 /** Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown
1718  When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
1719  $EN_DIS
1720 **/
1721  UINT8 PchPmDisableDsxAcPresentPulldown;
1722 
1723 /** Offset 0x0685
1724 **/
1725  UINT8 UnusedUpdSpace19;
1726 
1727 /** Offset 0x0686 - PCH Pm Disable Native Power Button
1728  Power button native mode disable.
1729  $EN_DIS
1730 **/
1731  UINT8 PchPmDisableNativePowerButton;
1732 
1733 /** Offset 0x0687 - PCH Pm Slp S0 Enable
1734  Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
1735  $EN_DIS
1736 **/
1737  UINT8 PchPmSlpS0Enable;
1738 
1739 /** Offset 0x0688 - PCH Pm ME_WAKE_STS
1740  Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
1741  $EN_DIS
1742 **/
1743  UINT8 PchPmMeWakeSts;
1744 
1745 /** Offset 0x0689 - PCH Pm WOL_OVR_WK_STS
1746  Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
1747  $EN_DIS
1748 **/
1749  UINT8 PchPmWolOvrWkSts;
1750 
1751 /** Offset 0x068A - PCH Pm Reset Power Cycle Duration
1752  Could be customized in the unit of second. Please refer to EDS for all support settings.
1753  0 is default, 1 is 1 second, 2 is 2 seconds, ...
1754 **/
1755  UINT8 PchPmPwrCycDur;
1756 
1757 /** Offset 0x068B - PCH Pm Pcie Pll Ssc
1758  Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
1759  BIOS override.
1760 **/
1761  UINT8 PchPmPciePllSsc;
1762 
1763 /** Offset 0x068C
1764 **/
1765  UINT8 UnusedUpdSpace20;
1766 
1767 /** Offset 0x068D - PCH Sata Pwr Opt Enable
1768  SATA Power Optimizer on PCH side.
1769  $EN_DIS
1770 **/
1771  UINT8 SataPwrOptEnable;
1772 
1773 /** Offset 0x068E - PCH Sata eSATA Speed Limit
1774  When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
1775  $EN_DIS
1776 **/
1777  UINT8 EsataSpeedLimit;
1778 
1779 /** Offset 0x068F - PCH Sata Speed Limit
1780  Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
1781 **/
1782  UINT8 SataSpeedLimit;
1783 
1784 /** Offset 0x0690 - Enable SATA Port HotPlug
1785  Enable SATA Port HotPlug.
1786 **/
1787  UINT8 SataPortsHotPlug[8];
1788 
1789 /** Offset 0x0698 - Enable SATA Port Interlock Sw
1790  Enable SATA Port Interlock Sw.
1791 **/
1792  UINT8 SataPortsInterlockSw[8];
1793 
1794 /** Offset 0x06A0 - Enable SATA Port External
1795  Enable SATA Port External.
1796 **/
1797  UINT8 SataPortsExternal[8];
1798 
1799 /** Offset 0x06A8 - Enable SATA Port SpinUp
1800  Enable the COMRESET initialization Sequence to the device.
1801 **/
1802  UINT8 SataPortsSpinUp[8];
1803 
1804 /** Offset 0x06B0 - Enable SATA Port Solid State Drive
1805  0: HDD; 1: SSD.
1806 **/
1807  UINT8 SataPortsSolidStateDrive[8];
1808 
1809 /** Offset 0x06B8 - Enable SATA Port Enable Dito Config
1810  Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
1811 **/
1812  UINT8 SataPortsEnableDitoConfig[8];
1813 
1814 /** Offset 0x06C0 - Enable SATA Port DmVal
1815  DITO multiplier. Default is 15.
1816 **/
1817  UINT8 SataPortsDmVal[8];
1818 
1819 /** Offset 0x06C8 - Enable SATA Port DmVal
1820  DEVSLP Idle Timeout (DITO), Default is 625.
1821 **/
1822  UINT16 SataPortsDitoVal[8];
1823 
1824 /** Offset 0x06D8 - Enable SATA Port ZpOdd
1825  Support zero power ODD.
1826 **/
1827  UINT8 SataPortsZpOdd[8];
1828 
1829 /** Offset 0x06E0 - PCH Sata Rst Raid Device Id
1830  Enable RAID Alternate ID.
1831  0:Client, 1:Alternate, 2:Server
1832 **/
1833  UINT8 SataRstRaidDeviceId;
1834 
1835 /** Offset 0x06E1 - PCH Sata Rst Raid0
1836  RAID0.
1837  $EN_DIS
1838 **/
1839  UINT8 SataRstRaid0;
1840 
1841 /** Offset 0x06E2 - PCH Sata Rst Raid1
1842  RAID1.
1843  $EN_DIS
1844 **/
1845  UINT8 SataRstRaid1;
1846 
1847 /** Offset 0x06E3 - PCH Sata Rst Raid10
1848  RAID10.
1849  $EN_DIS
1850 **/
1851  UINT8 SataRstRaid10;
1852 
1853 /** Offset 0x06E4 - PCH Sata Rst Raid5
1854  RAID5.
1855  $EN_DIS
1856 **/
1857  UINT8 SataRstRaid5;
1858 
1859 /** Offset 0x06E5 - PCH Sata Rst Irrt
1860  Intel Rapid Recovery Technology.
1861  $EN_DIS
1862 **/
1863  UINT8 SataRstIrrt;
1864 
1865 /** Offset 0x06E6 - PCH Sata Rst Orom Ui Banner
1866  OROM UI and BANNER.
1867  $EN_DIS
1868 **/
1869  UINT8 SataRstOromUiBanner;
1870 
1871 /** Offset 0x06E7 - PCH Sata Rst Orom Ui Delay
1872  00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
1873 **/
1874  UINT8 SataRstOromUiDelay;
1875 
1876 /** Offset 0x06E8 - PCH Sata Rst Hdd Unlock
1877  Indicates that the HDD password unlock in the OS is enabled.
1878  $EN_DIS
1879 **/
1880  UINT8 SataRstHddUnlock;
1881 
1882 /** Offset 0x06E9 - PCH Sata Rst Led Locate
1883  Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
1884  enabled on the OS.
1885  $EN_DIS
1886 **/
1887  UINT8 SataRstLedLocate;
1888 
1889 /** Offset 0x06EA - PCH Sata Rst Irrt Only
1890  Allow only IRRT drives to span internal and external ports.
1891  $EN_DIS
1892 **/
1893  UINT8 SataRstIrrtOnly;
1894 
1895 /** Offset 0x06EB - PCH Sata Rst Smart Storage
1896  RST Smart Storage caching Bit.
1897  $EN_DIS
1898 **/
1899  UINT8 SataRstSmartStorage;
1900 
1901 /** Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable
1902  Enable Intel RST for PCIe Storage remapping.
1903 **/
1904  UINT8 SataRstPcieEnable[3];
1905 
1906 /** Offset 0x06EF - PCH Sata Rst Pcie Storage Port
1907  Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
1908 **/
1909  UINT8 SataRstPcieStoragePort[3];
1910 
1911 /** Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay
1912  PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
1913 **/
1914  UINT8 SataRstPcieDeviceResetDelay[3];
1915 
1916 /** Offset 0x06F5 - Enable eMMC HS400 Training
1917  Deprecated.
1918  $EN_DIS
1919 **/
1920  UINT8 PchScsEmmcHs400TuningRequired;
1921 
1922 /** Offset 0x06F6 - Set HS400 Tuning Data Valid
1923  Set if HS400 Tuning Data Valid.
1924  $EN_DIS
1925 **/
1926  UINT8 PchScsEmmcHs400DllDataValid;
1927 
1928 /** Offset 0x06F7 - Rx Strobe Delay Control
1929  Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
1930 **/
1931  UINT8 PchScsEmmcHs400RxStrobeDll1;
1932 
1933 /** Offset 0x06F8 - Tx Data Delay Control
1934  Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
1935 **/
1936  UINT8 PchScsEmmcHs400TxDataDll;
1937 
1938 /** Offset 0x06F9 - I/O Driver Strength
1939  Deprecated.
1940  0:33 Ohm, 1:40 Ohm, 2:50 Ohm
1941 **/
1942  UINT8 PchScsEmmcHs400DriverStrength;
1943 
1944 /** Offset 0x06FA - PCH SerialIo I2C Pads Termination
1945  0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
1946  0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
1947  pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
1948  for I2C1, and so on.
1949 **/
1950  UINT8 PchSerialIoI2cPadsTermination[6];
1951 
1952 /** Offset 0x0700
1953 **/
1954  UINT8 UnusedUpdSpace21;
1955 
1956 /** Offset 0x0701 - PcdSerialIoUart0PinMuxing
1957  Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.
1958  0:default pins, 1:pins muxed with CNV_BRI/RGI
1959 **/
1960  UINT8 SerialIoUart0PinMuxing;
1961 
1962 /** Offset 0x0702
1963 **/
1964  UINT8 UnusedUpdSpace22[1];
1965 
1966 /** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines
1967  Enables UART hardware flow control, CTS and RTS linesh.
1968 **/
1969  UINT8 SerialIoUartHwFlowCtrl[3];
1970 
1971 /** Offset 0x0706 - UART Number For Debug Purpose
1972  UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected
1973  as CNVi BT Core interface, it cannot be used for debug purpose.
1974  0:UART0, 1:UART1, 2:UART2
1975 **/
1976  UINT8 SerialIoDebugUartNumber;
1977 
1978 /** Offset 0x0707 - Enable Debug UART Controller
1979  Enable debug UART controller after post.
1980  $EN_DIS
1981 **/
1982  UINT8 SerialIoEnableDebugUartAfterPost;
1983 
1984 /** Offset 0x0708 - Enable Serial IRQ
1985  Determines if enable Serial IRQ.
1986  $EN_DIS
1987 **/
1988  UINT8 PchSirqEnable;
1989 
1990 /** Offset 0x0709 - Serial IRQ Mode Select
1991  Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.
1992  $EN_DIS
1993 **/
1994  UINT8 PchSirqMode;
1995 
1996 /** Offset 0x070A - Start Frame Pulse Width
1997  Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
1998  0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk
1999 **/
2000  UINT8 PchStartFramePulse;
2001 
2002 /** Offset 0x070B - Reserved
2003  Reserved
2004  $EN_DIS
2005 **/
2006  UINT8 ReservedForFuture1;
2007 
2008 /** Offset 0x070C - Thermal Device SMI Enable
2009  This locks down SMI Enable on Alert Thermal Sensor Trip.
2010  $EN_DIS
2011 **/
2012  UINT8 PchTsmicLock;
2013 
2014 /** Offset 0x070D - Thermal Throttling Custimized T0Level Value
2015  Custimized T0Level value.
2016 **/
2017  UINT16 PchT0Level;
2018 
2019 /** Offset 0x070F - Thermal Throttling Custimized T1Level Value
2020  Custimized T1Level value.
2021 **/
2022  UINT16 PchT1Level;
2023 
2024 /** Offset 0x0711 - Thermal Throttling Custimized T2Level Value
2025  Custimized T2Level value.
2026 **/
2027  UINT16 PchT2Level;
2028 
2029 /** Offset 0x0713 - Enable The Thermal Throttle
2030  Enable the thermal throttle function.
2031  $EN_DIS
2032 **/
2033  UINT8 PchTTEnable;
2034 
2035 /** Offset 0x0714 - PMSync State 13
2036  When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
2037  at least T2 state.
2038  $EN_DIS
2039 **/
2040  UINT8 PchTTState13Enable;
2041 
2042 /** Offset 0x0715 - Thermal Throttle Lock
2043  Thermal Throttle Lock.
2044  $EN_DIS
2045 **/
2046  UINT8 PchTTLock;
2047 
2048 /** Offset 0x0716 - Thermal Throttling Suggested Setting
2049  Thermal Throttling Suggested Setting.
2050  $EN_DIS
2051 **/
2052  UINT8 TTSuggestedSetting;
2053 
2054 /** Offset 0x0717 - Enable PCH Cross Throttling
2055  Enable/Disable PCH Cross Throttling
2056  $EN_DIS
2057 **/
2058  UINT8 TTCrossThrottling;
2059 
2060 /** Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable
2061  DMI Thermal Sensor Autonomous Width Enable.
2062  $EN_DIS
2063 **/
2064  UINT8 PchDmiTsawEn;
2065 
2066 /** Offset 0x0719 - DMI Thermal Sensor Suggested Setting
2067  DMT thermal sensor suggested representative values.
2068  $EN_DIS
2069 **/
2070  UINT8 DmiSuggestedSetting;
2071 
2072 /** Offset 0x071A - Thermal Sensor 0 Target Width
2073  DMT thermal sensor suggested representative values.
2074  0:x1, 1:x2, 2:x4, 3:x8, 4:x16
2075 **/
2076  UINT8 DmiTS0TW;
2077 
2078 /** Offset 0x071B - Thermal Sensor 1 Target Width
2079  Thermal Sensor 1 Target Width.
2080  0:x1, 1:x2, 2:x4, 3:x8, 4:x16
2081 **/
2082  UINT8 DmiTS1TW;
2083 
2084 /** Offset 0x071C - Thermal Sensor 2 Target Width
2085  Thermal Sensor 2 Target Width.
2086  0:x1, 1:x2, 2:x4, 3:x8, 4:x16
2087 **/
2088  UINT8 DmiTS2TW;
2089 
2090 /** Offset 0x071D - Thermal Sensor 3 Target Width
2091  Thermal Sensor 3 Target Width.
2092  0:x1, 1:x2, 2:x4, 3:x8, 4:x16
2093 **/
2094  UINT8 DmiTS3TW;
2095 
2096 /** Offset 0x071E - Port 0 T1 Multipler
2097  Port 0 T1 Multipler.
2098 **/
2099  UINT8 SataP0T1M;
2100 
2101 /** Offset 0x071F - Port 0 T2 Multipler
2102  Port 0 T2 Multipler.
2103 **/
2104  UINT8 SataP0T2M;
2105 
2106 /** Offset 0x0720 - Port 0 T3 Multipler
2107  Port 0 T3 Multipler.
2108 **/
2109  UINT8 SataP0T3M;
2110 
2111 /** Offset 0x0721 - Port 0 Tdispatch
2112  Port 0 Tdispatch.
2113 **/
2114  UINT8 SataP0TDisp;
2115 
2116 /** Offset 0x0722 - Port 1 T1 Multipler
2117  Port 1 T1 Multipler.
2118 **/
2119  UINT8 SataP1T1M;
2120 
2121 /** Offset 0x0723 - Port 1 T2 Multipler
2122  Port 1 T2 Multipler.
2123 **/
2124  UINT8 SataP1T2M;
2125 
2126 /** Offset 0x0724 - Port 1 T3 Multipler
2127  Port 1 T3 Multipler.
2128 **/
2129  UINT8 SataP1T3M;
2130 
2131 /** Offset 0x0725 - Port 1 Tdispatch
2132  Port 1 Tdispatch.
2133 **/
2134  UINT8 SataP1TDisp;
2135 
2136 /** Offset 0x0726 - Port 0 Tinactive
2137  Port 0 Tinactive.
2138 **/
2139  UINT8 SataP0Tinact;
2140 
2141 /** Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch
2142  Port 0 Alternate Fast Init Tdispatch.
2143  $EN_DIS
2144 **/
2145  UINT8 SataP0TDispFinit;
2146 
2147 /** Offset 0x0728 - Port 1 Tinactive
2148  Port 1 Tinactive.
2149 **/
2150  UINT8 SataP1Tinact;
2151 
2152 /** Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch
2153  Port 1 Alternate Fast Init Tdispatch.
2154  $EN_DIS
2155 **/
2156  UINT8 SataP1TDispFinit;
2157 
2158 /** Offset 0x072A - Sata Thermal Throttling Suggested Setting
2159  Sata Thermal Throttling Suggested Setting.
2160  $EN_DIS
2161 **/
2162  UINT8 SataThermalSuggestedSetting;
2163 
2164 /** Offset 0x072B - Enable Memory Thermal Throttling
2165  Enable Memory Thermal Throttling.
2166  $EN_DIS
2167 **/
2168  UINT8 PchMemoryThrottlingEnable;
2169 
2170 /** Offset 0x072C - Memory Thermal Throttling
2171  Enable Memory Thermal Throttling.
2172 **/
2173  UINT8 PchMemoryPmsyncEnable[2];
2174 
2175 /** Offset 0x072E - Enable Memory Thermal Throttling
2176  Enable Memory Thermal Throttling.
2177 **/
2178  UINT8 PchMemoryC0TransmitEnable[2];
2179 
2180 /** Offset 0x0730 - Enable Memory Thermal Throttling
2181  Enable Memory Thermal Throttling.
2182 **/
2183  UINT8 PchMemoryPinSelection[2];
2184 
2185 /** Offset 0x0732 - Thermal Device Temperature
2186  Decides the temperature.
2187 **/
2188  UINT16 PchTemperatureHotLevel;
2189 
2190 /** Offset 0x0734 - Enable xHCI Compliance Mode
2191  Compliance Mode can be enabled for testing through this option but this is disabled
2192  by default.
2193  $EN_DIS
2194 **/
2195  UINT8 PchEnableComplianceMode;
2196 
2197 /** Offset 0x0735 - USB2 Port Over Current Pin
2198  Describe the specific over current pin number of USB 2.0 Port N.
2199 **/
2200  UINT8 Usb2OverCurrentPin[16];
2201 
2202 /** Offset 0x0745 - USB3 Port Over Current Pin
2203  Describe the specific over current pin number of USB 3.0 Port N.
2204 **/
2205  UINT8 Usb3OverCurrentPin[10];
2206 
2207 /** Offset 0x074F - Enable 8254 Static Clock Gating
2208  Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
2209  might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
2210  boot legacy OS using 8254 timer. Also enable this while S0ix is enabled.
2211  $EN_DIS
2212 **/
2213  UINT8 Enable8254ClockGating;
2214 
2215 /** Offset 0x0750 - PCH Sata Rst Optane Memory
2216  Optane Memory
2217  $EN_DIS
2218 **/
2219  UINT8 SataRstOptaneMemory;
2220 
2221 /** Offset 0x0751 - PCH Sata Rst CPU Attached Storage
2222  CPU Attached Storage
2223  $EN_DIS
2224 **/
2225  UINT8 SataRstCpuAttachedStorage;
2226 
2227 /** Offset 0x0752 - Enable 8254 Static Clock Gating On S3
2228  This is only applicable when Enable8254ClockGating is disabled. FSP will do the
2229  8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
2230  avoids the SMI requirement for the programming.
2231  $EN_DIS
2232 **/
2233  UINT8 Enable8254ClockGatingOnS3;
2234 
2235 /** Offset 0x0753
2236 **/
2237  UINT8 UnusedUpdSpace23;
2238 
2239 /** Offset 0x0754 - Pch PCIE device override table pointer
2240  The PCIe device table is being used to override PCIe device ASPM settings. This
2241  is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
2242  refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
2243  must be 0.
2244 **/
2245  UINT32 PchPcieDeviceOverrideTablePtr;
2246 
2247 /** Offset 0x0758 - Enable TCO timer.
2248  When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
2249  huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
2250  emulation must be enabled, and WDAT table must not be exposed to the OS.
2251  $EN_DIS
2252 **/
2253  UINT8 EnableTcoTimer;
2254 
2255 /** Offset 0x0759 - BgpdtHash[4]
2256  BgpdtHash values
2257 **/
2258  UINT64 BgpdtHash[4];
2259 
2260 /** Offset 0x0779 - BiosGuardAttr
2261  BiosGuardAttr default values
2262 **/
2263  UINT32 BiosGuardAttr;
2264 
2265 /** Offset 0x077D - BiosGuardModulePtr
2266  BiosGuardModulePtr default values
2267 **/
2268  UINT64 BiosGuardModulePtr;
2269 
2270 /** Offset 0x0785 - SendEcCmd
2271  SendEcCmd function pointer. \n
2272  @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
2273  EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
2274 **/
2275  UINT64 SendEcCmd;
2276 
2277 /** Offset 0x078D - EcCmdProvisionEav
2278  Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
2279 **/
2280  UINT8 EcCmdProvisionEav;
2281 
2282 /** Offset 0x078E - EcCmdLock
2283  EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
2284 **/
2285  UINT8 EcCmdLock;
2286 
2287 /** Offset 0x078F - SgxEpoch0
2288  SgxEpoch0 default values
2289 **/
2290  UINT64 SgxEpoch0;
2291 
2292 /** Offset 0x0797 - SgxEpoch1
2293  SgxEpoch1 default values
2294 **/
2295  UINT64 SgxEpoch1;
2296 
2297 /** Offset 0x079F - SgxSinitNvsData
2298  SgxSinitNvsData default values
2299 **/
2300  UINT8 SgxSinitNvsData;
2301 
2302 /** Offset 0x07A0 - Si Config CSM Flag.
2303  Platform specific common policies that used by several silicon components. CSM status flag.
2304  $EN_DIS
2305 **/
2306  UINT8 SiCsmFlag;
2307 
2308 /** Offset 0x07A1
2309 **/
2310  UINT32 SiSsidTablePtr;
2311 
2312 /** Offset 0x07A5
2313 **/
2314  UINT16 SiNumberOfSsidTableEntry;
2315 
2316 /** Offset 0x07A7 - SATA RST Interrupt Mode
2317  Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
2318  0:Msix, 1:Msi, 2:Legacy
2319 **/
2320  UINT8 SataRstInterrupt;
2321 
2322 /** Offset 0x07A8 - ME Unconfig on RTC clear
2323  0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
2324  2: Cmos is clear, status unkonwn. 3: Reserved
2325  0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
2326  is clear, 3: Reserved
2327 **/
2328  UINT8 MeUnconfigOnRtcClear;
2329 
2330 /** Offset 0x07A9 - Enable PS_ON.
2331  PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
2332  target that will be required by the California Energy Commission (CEC). When FALSE,
2333  PS_ON is to be disabled.
2334  $EN_DIS
2335 **/
2336  UINT8 PsOnEnable;
2337 
2338 /** Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable
2339  Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
2340  and VccSTG rails instead of SLP_S0# pin.
2341  $EN_DIS
2342 **/
2343  UINT8 PmcCpuC10GatePinEnable;
2344 
2345 /** Offset 0x07AB - Pch Dmi Aspm Ctrl
2346  ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
2347  0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
2348 **/
2349  UINT8 PchDmiAspmCtrl;
2350 
2351 /** Offset 0x07AC
2352 **/
2353  UINT8 ReservedFspsUpd[1];
2354 } FSP_S_CONFIG;
2355 
2356 /** Fsp S Test Configuration
2357 **/
2358 typedef struct {
2359 
2360 /** Offset 0x07AD
2361 **/
2362  UINT32 Signature;
2363 
2364 /** Offset 0x07B1 - Enable/Disable Device 7
2365  Enable: Device 7 enabled, Disable (Default): Device 7 disabled
2366  $EN_DIS
2367 **/
2368  UINT8 ChapDeviceEnable;
2369 
2370 /** Offset 0x07B2 - Skip PAM register lock
2371  Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
2372  PAM registers will be locked by RC
2373  $EN_DIS
2374 **/
2375  UINT8 SkipPamLock;
2376 
2377 /** Offset 0x07B3 - EDRAM Test Mode
2378  Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
2379  PAM registers will be locked by RC
2380  0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
2381 **/
2382  UINT8 EdramTestMode;
2383 
2384 /** Offset 0x07B4 - DMI Extended Sync Control
2385  Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended
2386  Sync Control
2387  $EN_DIS
2388 **/
2389  UINT8 DmiExtSync;
2390 
2391 /** Offset 0x07B5 - DMI IOT Control
2392  Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control
2393  $EN_DIS
2394 **/
2395  UINT8 DmiIot;
2396 
2397 /** Offset 0x07B6 - PEG Max Payload size per root port
2398  0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
2399  0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
2400 **/
2401  UINT8 PegMaxPayload[4];
2402 
2403 /** Offset 0x07BA - Enable/Disable IGFX RenderStandby
2404  Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
2405  $EN_DIS
2406 **/
2407  UINT8 RenderStandby;
2408 
2409 /** Offset 0x07BB - Enable/Disable IGFX PmSupport
2410  Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
2411  $EN_DIS
2412 **/
2413  UINT8 PmSupport;
2414 
2415 /** Offset 0x07BC - Enable/Disable CdynmaxClamp
2416  Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
2417  $EN_DIS
2418 **/
2419  UINT8 CdynmaxClampEnable;
2420 
2421 /** Offset 0x07BD - Disable VT-d
2422  0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
2423  $EN_DIS
2424 **/
2425  UINT8 VtdDisable;
2426 
2427 /** Offset 0x07BE - GT Frequency Limit
2428  0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
2429  7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
2430  650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
2431  0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
2432  0x18: 1200 Mhz
2433  0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
2434  7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
2435  650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
2436  0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
2437  0x18: 1200 Mhz
2438 **/
2439  UINT8 GtFreqMax;
2440 
2441 /** Offset 0x07BF - Disable Turbo GT
2442  0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
2443  $EN_DIS
2444 **/
2445  UINT8 DisableTurboGt;
2446 
2447 /** Offset 0x07C0 - SaPostMemTestRsvd
2448  Reserved for SA Post-Mem Test
2449  $EN_DIS
2450 **/
2451  UINT8 SaPostMemTestRsvd[11];
2452 
2453 /** Offset 0x07CB - 1-Core Ratio Limit
2454  1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core
2455  Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit,
2456  4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit,
2457  8-Core Ratio Limit. Range is 0 to 255
2458 **/
2459  UINT8 OneCoreRatioLimit;
2460 
2461 /** Offset 0x07CC - 2-Core Ratio Limit
2462  2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core
2463  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2464 **/
2465  UINT8 TwoCoreRatioLimit;
2466 
2467 /** Offset 0x07CD - 3-Core Ratio Limit
2468  3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core
2469  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2470 **/
2471  UINT8 ThreeCoreRatioLimit;
2472 
2473 /** Offset 0x07CE - 4-Core Ratio Limit
2474  4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core
2475  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
2476 **/
2477  UINT8 FourCoreRatioLimit;
2478 
2479 /** Offset 0x07CF - Enable or Disable HWP
2480  Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
2481  2-3:Reserved
2482  $EN_DIS
2483 **/
2484  UINT8 Hwp;
2485 
2486 /** Offset 0x07D0 - Hardware Duty Cycle Control
2487  Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
2488  $EN_DIS
2489 **/
2490  UINT8 HdcControl;
2491 
2492 /** Offset 0x07D1 - Package Long duration turbo mode time
2493  Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds.
2494  Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40
2495  , 48 , 56 , 64 , 80 , 96 , 112 , 128
2496 **/
2497  UINT8 PowerLimit1Time;
2498 
2499 /** Offset 0x07D2 - Short Duration Turbo Mode
2500  Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
2501  $EN_DIS
2502 **/
2503  UINT8 PowerLimit2;
2504 
2505 /** Offset 0x07D3 - Turbo settings Lock
2506  Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
2507  $EN_DIS
2508 **/
2509  UINT8 TurboPowerLimitLock;
2510 
2511 /** Offset 0x07D4 - Package PL3 time window
2512  Package PL3 time window range for this policy from 0 to 64ms
2513 **/
2514  UINT8 PowerLimit3Time;
2515 
2516 /** Offset 0x07D5 - Package PL3 Duty Cycle
2517  Package PL3 Duty Cycle; Valid Range is 0 to 100
2518 **/
2519  UINT8 PowerLimit3DutyCycle;
2520 
2521 /** Offset 0x07D6 - Package PL3 Lock
2522  Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable
2523  $EN_DIS
2524 **/
2525  UINT8 PowerLimit3Lock;
2526 
2527 /** Offset 0x07D7 - Package PL4 Lock
2528  Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable
2529  $EN_DIS
2530 **/
2531  UINT8 PowerLimit4Lock;
2532 
2533 /** Offset 0x07D8 - TCC Activation Offset
2534  TCC Activation Offset. Offset from factory set TCC activation temperature at which
2535  the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
2536  Temperature, in volts.For Y SKU, the recommended default for this policy is <b>15</b>,
2537  For all other SKUs the recommended default are <b>0</b>
2538 **/
2539  UINT8 TccActivationOffset;
2540 
2541 /** Offset 0x07D9 - Tcc Offset Clamp Enable/Disable
2542  Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
2543  below P1.For Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
2544  For all other SKUs the recommended default are <b>0: Disabled</b>.
2545  $EN_DIS
2546 **/
2547  UINT8 TccOffsetClamp;
2548 
2549 /** Offset 0x07DA - Tcc Offset Lock
2550  Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
2551  target; <b>0: Disabled</b>; 1: Enabled.
2552  $EN_DIS
2553 **/
2554  UINT8 TccOffsetLock;
2555 
2556 /** Offset 0x07DB - Custom Ratio State Entries
2557  The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
2558  ratio table.Sets the number of custom P-states. At least 2 states must be present
2559 **/
2560  UINT8 NumberOfEntries;
2561 
2562 /** Offset 0x07DC - Custom Short term Power Limit time window
2563  Short term Power Limit time window value for custom CTDP level 1. Valid Range 0
2564  to 128, 0 = AUTO
2565 **/
2566  UINT8 Custom1PowerLimit1Time;
2567 
2568 /** Offset 0x07DD - Custom Turbo Activation Ratio
2569  Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
2570 **/
2571  UINT8 Custom1TurboActivationRatio;
2572 
2573 /** Offset 0x07DE - Custom Config Tdp Control
2574  Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
2575 **/
2576  UINT8 Custom1ConfigTdpControl;
2577 
2578 /** Offset 0x07DF - Custom Short term Power Limit time window
2579  Short term Power Limit time window value for custom CTDP level 2. Valid Range 0
2580  to 128, 0 = AUTO
2581 **/
2582  UINT8 Custom2PowerLimit1Time;
2583 
2584 /** Offset 0x07E0 - Custom Turbo Activation Ratio
2585  Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
2586 **/
2587  UINT8 Custom2TurboActivationRatio;
2588 
2589 /** Offset 0x07E1 - Custom Config Tdp Control
2590  Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
2591 **/
2592  UINT8 Custom2ConfigTdpControl;
2593 
2594 /** Offset 0x07E2 - Custom Short term Power Limit time window
2595  Short term Power Limit time window value for custom CTDP level 3. Valid Range 0
2596  to 128, 0 = AUTO
2597 **/
2598  UINT8 Custom3PowerLimit1Time;
2599 
2600 /** Offset 0x07E3 - Custom Turbo Activation Ratio
2601  Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
2602 **/
2603  UINT8 Custom3TurboActivationRatio;
2604 
2605 /** Offset 0x07E4 - Custom Config Tdp Control
2606  Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
2607 **/
2608  UINT8 Custom3ConfigTdpControl;
2609 
2610 /** Offset 0x07E5 - ConfigTdp mode settings Lock
2611  Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
2612  $EN_DIS
2613 **/
2614  UINT8 ConfigTdpLock;
2615 
2616 /** Offset 0x07E6 - Load Configurable TDP SSDT
2617  Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
2618  $EN_DIS
2619 **/
2620  UINT8 ConfigTdpBios;
2621 
2622 /** Offset 0x07E7 - PL1 Enable value
2623  PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
2624  $EN_DIS
2625 **/
2626  UINT8 PsysPowerLimit1;
2627 
2628 /** Offset 0x07E8 - PL1 timewindow
2629  PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds)
2630  1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
2631 **/
2632  UINT8 PsysPowerLimit1Time;
2633 
2634 /** Offset 0x07E9 - PL2 Enable Value
2635  PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
2636  1: Enable.
2637  $EN_DIS
2638 **/
2639  UINT8 PsysPowerLimit2;
2640 
2641 /** Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher
2642  Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
2643  $EN_DIS
2644 **/
2645  UINT8 MlcStreamerPrefetcher;
2646 
2647 /** Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher
2648  Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
2649  $EN_DIS
2650 **/
2651  UINT8 MlcSpatialPrefetcher;
2652 
2653 /** Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions
2654  Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
2655  $EN_DIS
2656 **/
2657  UINT8 MonitorMwaitEnable;
2658 
2659 /** Offset 0x07ED - Enable or Disable initialization of machine check registers
2660  Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
2661  $EN_DIS
2662 **/
2663  UINT8 MachineCheckEnable;
2664 
2665 /** Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features
2666  @deprecated Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
2667  $EN_DIS
2668 **/
2669  UINT8 DebugInterfaceEnable;
2670 
2671 /** Offset 0x07EF - Lock or Unlock debug interface features
2672  Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
2673  $EN_DIS
2674 **/
2675  UINT8 DebugInterfaceLockEnable;
2676 
2677 /** Offset 0x07F0 - AP Idle Manner of waiting for SIPI
2678  AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
2679  1: HALT loop, 2: MWAIT loop, 3: RUN loop
2680 **/
2681  UINT8 ApIdleManner;
2682 
2683 /** Offset 0x07F1 - Control on Processor Trace output scheme
2684  Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
2685  0: Single Range Output, 1: ToPA Output
2686 **/
2687  UINT8 ProcessorTraceOutputScheme;
2688 
2689 /** Offset 0x07F2 - Enable or Disable Processor Trace feature
2690  Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
2691  $EN_DIS
2692 **/
2693  UINT8 ProcessorTraceEnable;
2694 
2695 /** Offset 0x07F3 - Base of memory region allocated for Processor Trace
2696  Base address of memory region allocated for Processor Trace. Processor Trace requires
2697  2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
2698 **/
2699  UINT64 ProcessorTraceMemBase;
2700 
2701 /** Offset 0x07FB - Memory region allocation for Processor Trace
2702  Length in bytes of memory region allocated for Processor Trace. Processor Trace
2703  requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
2704 **/
2705  UINT32 ProcessorTraceMemLength;
2706 
2707 /** Offset 0x07FF - Enable or Disable Voltage Optimization feature
2708  Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>
2709  $EN_DIS
2710 **/
2711  UINT8 VoltageOptimization;
2712 
2713 /** Offset 0x0800 - Enable or Disable Intel SpeedStep Technology
2714  Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
2715  $EN_DIS
2716 **/
2717  UINT8 Eist;
2718 
2719 /** Offset 0x0801 - Enable or Disable Energy Efficient P-state
2720  Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
2721  <b>1: Enable</b>
2722  $EN_DIS
2723 **/
2724  UINT8 EnergyEfficientPState;
2725 
2726 /** Offset 0x0802 - Enable or Disable Energy Efficient Turbo
2727  Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
2728  <b>1: Enable</b>
2729  $EN_DIS
2730 **/
2731  UINT8 EnergyEfficientTurbo;
2732 
2733 /** Offset 0x0803 - Enable or Disable T states
2734  Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
2735  $EN_DIS
2736 **/
2737  UINT8 TStates;
2738 
2739 /** Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT#
2740  Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
2741  $EN_DIS
2742 **/
2743  UINT8 BiProcHot;
2744 
2745 /** Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally
2746  Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
2747  $EN_DIS
2748 **/
2749  UINT8 DisableProcHotOut;
2750 
2751 /** Offset 0x0806 - Enable or Disable PROCHOT# Response
2752  Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
2753  $EN_DIS
2754 **/
2755  UINT8 ProcHotResponse;
2756 
2757 /** Offset 0x0807 - Enable or Disable VR Thermal Alert
2758  Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
2759  $EN_DIS
2760 **/
2761  UINT8 DisableVrThermalAlert;
2762 
2763 /** Offset 0x0808 - Enable or Disable Thermal Reporting
2764  Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
2765  $EN_DIS
2766 **/
2767  UINT8 AutoThermalReporting;
2768 
2769 /** Offset 0x0809 - Enable or Disable Thermal Monitor
2770  Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
2771  $EN_DIS
2772 **/
2773  UINT8 ThermalMonitor;
2774 
2775 /** Offset 0x080A - Enable or Disable CPU power states (C-states)
2776  Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
2777  $EN_DIS
2778 **/
2779  UINT8 Cx;
2780 
2781 /** Offset 0x080B - Configure C-State Configuration Lock
2782  Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
2783  $EN_DIS
2784 **/
2785  UINT8 PmgCstCfgCtrlLock;
2786 
2787 /** Offset 0x080C - Enable or Disable Enhanced C-states
2788  Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
2789  $EN_DIS
2790 **/
2791  UINT8 C1e;
2792 
2793 /** Offset 0x080D - Enable or Disable Package Cstate Demotion
2794  Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable
2795  $EN_DIS
2796 **/
2797  UINT8 PkgCStateDemotion;
2798 
2799 /** Offset 0x080E - Enable or Disable Package Cstate UnDemotion
2800  Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable
2801  $EN_DIS
2802 **/
2803  UINT8 PkgCStateUnDemotion;
2804 
2805 /** Offset 0x080F - Enable or Disable CState-Pre wake
2806  Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
2807  $EN_DIS
2808 **/
2809  UINT8 CStatePreWake;
2810 
2811 /** Offset 0x0810 - Enable or Disable TimedMwait Support.
2812  Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
2813  $EN_DIS
2814 **/
2815  UINT8 TimedMwait;
2816 
2817 /** Offset 0x0811 - Enable or Disable IO to MWAIT redirection
2818  Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
2819  $EN_DIS
2820 **/
2821  UINT8 CstCfgCtrIoMwaitRedirection;
2822 
2823 /** Offset 0x0812 - Set the Max Pkg Cstate
2824  Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
2825  C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
2826  6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
2827 **/
2828  UINT8 PkgCStateLimit;
2829 
2830 /** Offset 0x0813 - TimeUnit for C-State Latency Control0
2831  TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2832  , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2833 **/
2834  UINT8 CstateLatencyControl0TimeUnit;
2835 
2836 /** Offset 0x0814 - TimeUnit for C-State Latency Control1
2837  TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2838  , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2839 **/
2840  UINT8 CstateLatencyControl1TimeUnit;
2841 
2842 /** Offset 0x0815 - TimeUnit for C-State Latency Control2
2843  TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2844  , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2845 **/
2846  UINT8 CstateLatencyControl2TimeUnit;
2847 
2848 /** Offset 0x0816 - TimeUnit for C-State Latency Control3
2849  TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2850  , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2851 **/
2852  UINT8 CstateLatencyControl3TimeUnit;
2853 
2854 /** Offset 0x0817 - TimeUnit for C-State Latency Control4
2855  Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2856 **/
2857  UINT8 CstateLatencyControl4TimeUnit;
2858 
2859 /** Offset 0x0818 - TimeUnit for C-State Latency Control5
2860  TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
2861  , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
2862 **/
2863  UINT8 CstateLatencyControl5TimeUnit;
2864 
2865 /** Offset 0x0819 - Interrupt Redirection Mode Select
2866  Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
2867  PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
2868 **/
2869  UINT8 PpmIrmSetting;
2870 
2871 /** Offset 0x081A - Lock prochot configuration
2872  Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
2873  $EN_DIS
2874 **/
2875  UINT8 ProcHotLock;
2876 
2877 /** Offset 0x081B - Configuration for boot TDP selection
2878  Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
2879  Up;0xFF : Deactivate
2880 **/
2881  UINT8 ConfigTdpLevel;
2882 
2883 /** Offset 0x081C - Race To Halt
2884  Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
2885  in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
2886  through MSR 1FC bit 20)Disable; <b>1: Enable</b>
2887  $EN_DIS
2888 **/
2889  UINT8 RaceToHalt;
2890 
2891 /** Offset 0x081D - Max P-State Ratio
2892  Max P-State Ratio, Valid Range 0 to 0x7F
2893 **/
2894  UINT8 MaxRatio;
2895 
2896 /** Offset 0x081E - P-state ratios for custom P-state table
2897  P-state ratios for custom P-state table. NumberOfEntries has valid range between
2898  0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
2899  are configurable. Valid Range of each entry is 0 to 0x7F
2900 **/
2901  UINT8 StateRatio[40];
2902 
2903 /** Offset 0x0846 - P-state ratios for max 16 version of custom P-state table
2904  P-state ratios for max 16 version of custom P-state table. This table is used for
2905  OS versions limited to a max of 16 P-States. If the first entry of this table is
2906  0, or if Number of Entries is 16 or less, then this table will be ignored, and
2907  up to the top 16 values of the StateRatio table will be used instead. Valid Range
2908  of each entry is 0 to 0x7F
2909 **/
2910  UINT8 StateRatioMax16[16];
2911 
2912 /** Offset 0x0856 - Platform Power Pmax
2913  PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
2914  Range 0-1024 Watts. Value of 800 = 100W
2915 **/
2916  UINT16 PsysPmax;
2917 
2918 /** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0
2919  Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF
2920 **/
2921  UINT16 CstateLatencyControl0Irtl;
2922 
2923 /** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1
2924  Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
2925 **/
2926  UINT16 CstateLatencyControl1Irtl;
2927 
2928 /** Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2
2929  Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF
2930 **/
2931  UINT16 CstateLatencyControl2Irtl;
2932 
2933 /** Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3
2934  Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF
2935 **/
2936  UINT16 CstateLatencyControl3Irtl;
2937 
2938 /** Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4
2939  Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF
2940 **/
2941  UINT16 CstateLatencyControl4Irtl;
2942 
2943 /** Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5
2944  Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF
2945 **/
2946  UINT16 CstateLatencyControl5Irtl;
2947 
2948 /** Offset 0x0864 - Package Long duration turbo mode power limit
2949  Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
2950  Valid Range 0 to 4095875 in Step size of 125
2951 **/
2952  UINT32 PowerLimit1;
2953 
2954 /** Offset 0x0868 - Package Short duration turbo mode power limit
2955  Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2956  Range 0 to 4095875 in Step size of 125
2957 **/
2958  UINT32 PowerLimit2Power;
2959 
2960 /** Offset 0x086C - Package PL3 power limit
2961  Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2962  Range 0 to 4095875 in Step size of 125
2963 **/
2964  UINT32 PowerLimit3;
2965 
2966 /** Offset 0x0870 - Package PL4 power limit
2967  Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2968  Range 0 to 1023875 in Step size of 125
2969 **/
2970  UINT32 PowerLimit4;
2971 
2972 /** Offset 0x0874 - Tcc Offset Time Window for RATL
2973  Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2974  Range 0 to 1023875 in Step size of 125
2975 **/
2976  UINT32 TccOffsetTimeWindowForRatl;
2977 
2978 /** Offset 0x0878 - Short term Power Limit value for custom cTDP level 1
2979  Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2980  Range 0 to 4095875 in Step size of 125
2981 **/
2982  UINT32 Custom1PowerLimit1;
2983 
2984 /** Offset 0x087C - Long term Power Limit value for custom cTDP level 1
2985  Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2986  Range 0 to 4095875 in Step size of 125
2987 **/
2988  UINT32 Custom1PowerLimit2;
2989 
2990 /** Offset 0x0880 - Short term Power Limit value for custom cTDP level 2
2991  Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2992  Range 0 to 4095875 in Step size of 125
2993 **/
2994  UINT32 Custom2PowerLimit1;
2995 
2996 /** Offset 0x0884 - Long term Power Limit value for custom cTDP level 2
2997  Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
2998  Range 0 to 4095875 in Step size of 125
2999 **/
3000  UINT32 Custom2PowerLimit2;
3001 
3002 /** Offset 0x0888 - Short term Power Limit value for custom cTDP level 3
3003  Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
3004  Range 0 to 4095875 in Step size of 125
3005 **/
3006  UINT32 Custom3PowerLimit1;
3007 
3008 /** Offset 0x088C - Long term Power Limit value for custom cTDP level 3
3009  Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
3010  Range 0 to 4095875 in Step size of 125
3011 **/
3012  UINT32 Custom3PowerLimit2;
3013 
3014 /** Offset 0x0890 - Platform PL1 power
3015  Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
3016  0 to 4095875 in Step size of 125
3017 **/
3018  UINT32 PsysPowerLimit1Power;
3019 
3020 /** Offset 0x0894 - Platform PL2 power
3021  Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
3022  0 to 4095875 in Step size of 125
3023 **/
3024  UINT32 PsysPowerLimit2Power;
3025 
3026 /** Offset 0x0898 - Set Three Strike Counter Disable
3027  False (default): Three Strike counter will be incremented and True: Prevents Three
3028  Strike counter from incrementing; <b>0: False</b>; 1: True.
3029  0: False, 1: True
3030 **/
3031  UINT8 ThreeStrikeCounterDisable;
3032 
3033 /** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
3034  Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
3035  $EN_DIS
3036 **/
3037  UINT8 HwpInterruptControl;
3038 
3039 /** Offset 0x089A - 5-Core Ratio Limit
3040  5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core
3041  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
3042  0x0:0xFF
3043 **/
3044  UINT8 FiveCoreRatioLimit;
3045 
3046 /** Offset 0x089B - 6-Core Ratio Limit
3047  6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core
3048  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
3049  0x0:0xFF
3050 **/
3051  UINT8 SixCoreRatioLimit;
3052 
3053 /** Offset 0x089C - 7-Core Ratio Limit
3054  7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core
3055  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
3056  0x0:0xFF
3057 **/
3058  UINT8 SevenCoreRatioLimit;
3059 
3060 /** Offset 0x089D - 8-Core Ratio Limit
3061  8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core
3062  Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
3063  0x0:0xFF
3064 **/
3065  UINT8 EightCoreRatioLimit;
3066 
3067 /** Offset 0x089E - Intel Turbo Boost Max Technology 3.0
3068  Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
3069  $EN_DIS
3070 **/
3071  UINT8 EnableItbm;
3072 
3073 /** Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver
3074  Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled
3075  $EN_DIS
3076 **/
3077  UINT8 EnableItbmDriver;
3078 
3079 /** Offset 0x08A0 - Enable or Disable C1 Cstate Demotion
3080  Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>
3081  $EN_DIS
3082 **/
3083  UINT8 C1StateAutoDemotion;
3084 
3085 /** Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion
3086  Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>
3087  $EN_DIS
3088 **/
3089  UINT8 C1StateUnDemotion;
3090 
3091 /** Offset 0x08A2 - CpuWakeUpTimer
3092  Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased
3093  to 180 seconds. 0: Disable; <b>1: Enable</b>
3094  $EN_DIS
3095 **/
3096  UINT8 CpuWakeUpTimer;
3097 
3098 /** Offset 0x08A3 - Minimum Ring ratio limit override
3099  Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
3100  ratio limit
3101 **/
3102  UINT8 MinRingRatioLimit;
3103 
3104 /** Offset 0x08A4 - Minimum Ring ratio limit override
3105  Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
3106  ratio limit
3107 **/
3108  UINT8 MaxRingRatioLimit;
3109 
3110 /** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion
3111  Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>
3112  $EN_DIS
3113 **/
3114  UINT8 C3StateAutoDemotion;
3115 
3116 /** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion
3117  Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>
3118  $EN_DIS
3119 **/
3120  UINT8 C3StateUnDemotion;
3121 
3122 /** Offset 0x08A7 - ReservedCpuPostMemTest
3123  Reserved for CPU Post-Mem Test
3124  $EN_DIS
3125 **/
3126  UINT8 ReservedCpuPostMemTest[19];
3127 
3128 /** Offset 0x08BA - SgxSinitDataFromTpm
3129  SgxSinitDataFromTpm default values
3130 **/
3131  UINT8 SgxSinitDataFromTpm;
3132 
3133 /** Offset 0x08BB - End of Post message
3134  Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
3135  EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI
3136  0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
3137 **/
3138  UINT8 EndOfPostMessage;
3139 
3140 /** Offset 0x08BC - D0I3 Setting for HECI Disable
3141  Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
3142  HECI devices
3143  $EN_DIS
3144 **/
3145  UINT8 DisableD0I3SettingForHeci;
3146 
3147 /** Offset 0x08BD - HD Audio Reset Wait Timer
3148  The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
3149 **/
3150  UINT16 PchHdaResetWaitTimer;
3151 
3152 /** Offset 0x08BF - Enable LOCKDOWN SMI
3153  Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
3154  $EN_DIS
3155 **/
3156  UINT8 PchLockDownGlobalSmi;
3157 
3158 /** Offset 0x08C0 - Enable LOCKDOWN BIOS Interface
3159  Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
3160  $EN_DIS
3161 **/
3162  UINT8 PchLockDownBiosInterface;
3163 
3164 /** Offset 0x08C1 - Unlock all GPIO pads
3165  Force all GPIO pads to be unlocked for debug purpose.
3166  $EN_DIS
3167 **/
3168  UINT8 PchUnlockGpioPads;
3169 
3170 /** Offset 0x08C2 - PCH Unlock SBI access
3171  Deprecated
3172  $EN_DIS
3173 **/
3174  UINT8 PchSbiUnlock;
3175 
3176 /** Offset 0x08C3 - PCH Unlock SideBand access
3177  The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
3178  3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
3179  $EN_DIS
3180 **/
3181  UINT8 PchSbAccessUnlock;
3182 
3183 /** Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency
3184  Latency Tolerance Reporting, Max Snoop Latency.
3185 **/
3186  UINT16 PcieRpLtrMaxSnoopLatency[24];
3187 
3188 /** Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency
3189  Latency Tolerance Reporting, Max Non-Snoop Latency.
3190 **/
3191  UINT16 PcieRpLtrMaxNoSnoopLatency[24];
3192 
3193 /** Offset 0x0924 - PCIE RP Snoop Latency Override Mode
3194  Latency Tolerance Reporting, Snoop Latency Override Mode.
3195 **/
3196  UINT8 PcieRpSnoopLatencyOverrideMode[24];
3197 
3198 /** Offset 0x093C - PCIE RP Snoop Latency Override Multiplier
3199  Latency Tolerance Reporting, Snoop Latency Override Multiplier.
3200 **/
3201  UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
3202 
3203 /** Offset 0x0954 - PCIE RP Snoop Latency Override Value
3204  Latency Tolerance Reporting, Snoop Latency Override Value.
3205 **/
3206  UINT16 PcieRpSnoopLatencyOverrideValue[24];
3207 
3208 /** Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode
3209  Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
3210 **/
3211  UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
3212 
3213 /** Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier
3214  Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
3215 **/
3216  UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
3217 
3218 /** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value
3219  Latency Tolerance Reporting, Non-Snoop Latency Override Value.
3220 **/
3221  UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
3222 
3223 /** Offset 0x09E4 - PCIE RP Slot Power Limit Scale
3224  Specifies scale used for slot power limit value. Leave as 0 to set to default.
3225 **/
3226  UINT8 PcieRpSlotPowerLimitScale[24];
3227 
3228 /** Offset 0x09FC - PCIE RP Slot Power Limit Value
3229  Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
3230 **/
3231  UINT16 PcieRpSlotPowerLimitValue[24];
3232 
3233 /** Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset
3234  Used during Gen3 Link Equalization. Used for all lanes. Default is 5.
3235 **/
3236  UINT8 PcieRpUptp[24];
3237 
3238 /** Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset
3239  Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
3240 **/
3241  UINT8 PcieRpDptp[24];
3242 
3243 /** Offset 0x0A5C - PCIE RP Enable Port8xh Decode
3244  This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
3245  1: Enable.
3246  $EN_DIS
3247 **/
3248  UINT8 PcieEnablePort8xhDecode;
3249 
3250 /** Offset 0x0A5D - PCIE Port8xh Decode Port Index
3251  The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
3252 **/
3253  UINT8 PchPciePort8xhDecodePortIndex;
3254 
3255 /** Offset 0x0A5E - PCH Energy Reporting
3256  Disable/Enable PCH to CPU energy report feature.
3257  $EN_DIS
3258 **/
3259  UINT8 PchPmDisableEnergyReport;
3260 
3261 /** Offset 0x0A5F - PCH Sata Test Mode
3262  Allow entrance to the PCH SATA test modes.
3263  $EN_DIS
3264 **/
3265  UINT8 SataTestMode;
3266 
3267 /** Offset 0x0A60 - PCH USB OverCurrent mapping lock enable
3268  If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
3269  that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
3270  $EN_DIS
3271 **/
3272  UINT8 PchXhciOcLock;
3273 
3274 /** Offset 0x0A61
3275 **/
3276  UINT8 UnusedUpdSpace24[17];
3277 
3278 /** Offset 0x0A72 - Skip POSTBOOT SAI
3279  Deprecated
3280  $EN_DIS
3281 **/
3282  UINT8 SkipPostBootSai;
3283 
3284 /** Offset 0x0A73 - Mctp Broadcast Cycle
3285  Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
3286  $EN_DIS
3287 **/
3288  UINT8 MctpBroadcastCycle;
3289 
3290 /** Offset 0x0A74
3291 **/
3292  UINT8 ReservedFspsTestUpd[12];
3293 } FSP_S_TEST_CONFIG;
3294 
3295 /** Fsp S UPD Configuration
3296 **/
3297 typedef struct {
3298 
3299 /** Offset 0x0000
3300 **/
3301  FSP_UPD_HEADER FspUpdHeader;
3302 
3303 /** Offset 0x0020
3304 **/
3305  FSP_S_CONFIG FspsConfig;
3306 
3307 /** Offset 0x07AD
3308 **/
3309  FSP_S_TEST_CONFIG FspsTestConfig;
3310 
3311 /** Offset 0x0A80
3312 **/
3313  UINT16 UpdTerminator;
3314 } FSPS_UPD;
3315 
3316 #pragma pack()
3317 
3318 #endif
FSP_S_TEST_CONFIG::PsysPowerLimit2Power
UINT32 PsysPowerLimit2Power
Offset 0x0894 - Platform PL2 power Platform PL2 power.
Definition: FspsUpd.h:3024
FSP_S_TEST_CONFIG::ThreeCoreRatioLimit
UINT8 ThreeCoreRatioLimit
Offset 0x07CD - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:2471
FSP_S_CONFIG::PchHdaAudioLinkDmic1
UINT8 PchHdaAudioLinkDmic1
Offset 0x00FF - Enable HD Audio DMIC1 Link Enable/disable HD Audio DMIC1 link.
Definition: FspsUpd.h:347
FSP_S_CONFIG::TcoIrqEnable
UINT8 TcoIrqEnable
Offset 0x008B - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS.
Definition: FspsUpd.h:248
FSP_S_CONFIG::PchHdaIDispLinkFrequency
UINT8 PchHdaIDispLinkFrequency
Offset 0x036A - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz...
Definition: FspsUpd.h:1216
FSP_S_TEST_CONFIG::CstateLatencyControl1Irtl
UINT16 CstateLatencyControl1Irtl
Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit...
Definition: FspsUpd.h:2926
FSP_S_CONFIG::PchPmVrAlert
UINT8 PchPmVrAlert
Offset 0x0151 - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0'...
Definition: FspsUpd.h:547
FSP_S_CONFIG::PchTTLock
UINT8 PchTTLock
Offset 0x0715 - Thermal Throttle Lock Thermal Throttle Lock.
Definition: FspsUpd.h:2046
FSP_S_TEST_CONFIG::Custom3PowerLimit2
UINT32 Custom3PowerLimit2
Offset 0x088C - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for c...
Definition: FspsUpd.h:3012
FSP_S_CONFIG::WatchDogTimerBios
UINT16 WatchDogTimerBios
Offset 0x015D - BIOS Timer 16 bits Value, Set BIOS watchdog timer.
Definition: FspsUpd.h:614
FSP_S_CONFIG::SlowSlewRateForIa
UINT8 SlowSlewRateForIa
Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configur...
Definition: FspsUpd.h:939
FSP_S_CONFIG::UnusedUpdSpace19
UINT8 UnusedUpdSpace19
Offset 0x0685.
Definition: FspsUpd.h:1725
FSP_S_CONFIG::CridEnable
UINT8 CridEnable
Offset 0x0200 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS...
Definition: FspsUpd.h:693
FSP_S_CONFIG::BltBufferAddress
UINT32 BltBufferAddress
Offset 0x0234 - Blt Buffer Address Address of Blt buffer.
Definition: FspsUpd.h:833
FSP_S_CONFIG::PchCnviMfUart1Type
UINT8 PchCnviMfUart1Type
Offset 0x014B - CNVi MfUart1 Type This option configures Uart type which connects to MfUart1 0:ISH Ua...
Definition: FspsUpd.h:511
FSP_S_CONFIG::MeUnconfigOnRtcClear
UINT8 MeUnconfigOnRtcClear
Offset 0x07A8 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear.
Definition: FspsUpd.h:2328
FSP_S_TEST_CONFIG::ProcessorTraceEnable
UINT8 ProcessorTraceEnable
Offset 0x07F2 - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; ...
Definition: FspsUpd.h:2693
FSP_S_CONFIG::PchT2Level
UINT16 PchT2Level
Offset 0x0711 - Thermal Throttling Custimized T2Level Value Custimized T2Level value.
Definition: FspsUpd.h:2027
FSP_S_CONFIG::PchPmWoWlanDeepSxEnable
UINT8 PchPmWoWlanDeepSxEnable
Offset 0x0673 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the D...
Definition: FspsUpd.h:1627
FSP_S_CONFIG::PchUsb2PhySusPgEnable
UINT8 PchUsb2PhySusPgEnable
Offset 0x0148 - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating...
Definition: FspsUpd.h:494
FSP_S_CONFIG::SataSalpSupport
UINT8 SataSalpSupport
Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management...
Definition: FspsUpd.h:167
FSP_S_CONFIG::PchLockDownRtcMemoryLock
UINT8 PchLockDownRtcMemoryLock
Offset 0x0395 - RTC CMOS MEMORY LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-...
Definition: FspsUpd.h:1380
FSP_S_CONFIG::PchPmWolEnableOverride
UINT8 PchPmWolEnableOverride
Offset 0x0670 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General ...
Definition: FspsUpd.h:1608
FSP_S_CONFIG::UsbPdoProgramming
UINT8 UsbPdoProgramming
Offset 0x0114 - USB PDO Programming Enable/disable PDO programming for USB in PEI phase...
Definition: FspsUpd.h:420
FSP_S_CONFIG::SataP0TDispFinit
UINT8 SataP0TDispFinit
Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch.
Definition: FspsUpd.h:2145
FSP_S_TEST_CONFIG::PsysPowerLimit2
UINT8 PsysPowerLimit2
Offset 0x07E9 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power...
Definition: FspsUpd.h:2639
FSP_S_CONFIG::TTCrossThrottling
UINT8 TTCrossThrottling
Offset 0x0717 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS.
Definition: FspsUpd.h:2058
FSP_S_CONFIG::SataRstCpuAttachedStorage
UINT8 SataRstCpuAttachedStorage
Offset 0x0751 - PCH Sata Rst CPU Attached Storage CPU Attached Storage $EN_DIS.
Definition: FspsUpd.h:2225
FSP_S_TEST_CONFIG::NumberOfEntries
UINT8 NumberOfEntries
Offset 0x07DB - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states.
Definition: FspsUpd.h:2560
FSP_S_TEST_CONFIG::EnergyEfficientTurbo
UINT8 EnergyEfficientTurbo
Offset 0x0802 - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo...
Definition: FspsUpd.h:2731
FSP_S_TEST_CONFIG::EdramTestMode
UINT8 EdramTestMode
Offset 0x07B3 - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should l...
Definition: FspsUpd.h:2382
FSP_S_TEST_CONFIG::CstateLatencyControl2Irtl
UINT16 CstateLatencyControl2Irtl
Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit...
Definition: FspsUpd.h:2931
FSP_S_TEST_CONFIG::PchLockDownBiosInterface
UINT8 PchLockDownBiosInterface
Offset 0x08C0 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes ...
Definition: FspsUpd.h:3162
FSP_S_CONFIG::PchPmSlpStrchSusUp
UINT8 PchPmSlpStrchSusUp
Offset 0x0681 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up...
Definition: FspsUpd.h:1704
FSP_S_CONFIG::FivrRfiFrequency
UINT16 FivrRfiFrequency
Offset 0x030F - FIVR RFI Frequency PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
Definition: FspsUpd.h:1062
FSP_S_CONFIG::RemoteAssistance
UINT8 RemoteAssistance
Offset 0x015F - Remote Assistance Trigger Availablilty Enable/Disable.
Definition: FspsUpd.h:620
FSP_S_TEST_CONFIG::C1e
UINT8 C1e
Offset 0x080C - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states.
Definition: FspsUpd.h:2791
FSP_S_TEST_CONFIG::PpmIrmSetting
UINT8 PpmIrmSetting
Offset 0x0819 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
Definition: FspsUpd.h:2869
FSP_S_CONFIG::PchDmiAspmCtrl
UINT8 PchDmiAspmCtrl
Offset 0x07AB - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link...
Definition: FspsUpd.h:2349
FSP_S_CONFIG::PchEspiLgmrEnable
UINT8 PchEspiLgmrEnable
Offset 0x014C - Espi Lgmr Memory Range decode This option enables or disables espi lgmr $EN_DIS...
Definition: FspsUpd.h:517
FSP_S_TEST_CONFIG::MinRingRatioLimit
UINT8 MinRingRatioLimit
Offset 0x08A3 - Minimum Ring ratio limit override Minimum Ring ratio limit override.
Definition: FspsUpd.h:3102
FSP_S_CONFIG::PchIshGp7GpioAssign
UINT8 PchIshGp7GpioAssign
Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1344
AZALIA_HEADER
Azalia Header structure.
Definition: FspsUpd.h:44
FSP_S_CONFIG::DdiPortCDdc
UINT8 DdiPortCDdc
Offset 0x022E - Enable or disable DDC of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:802
FSP_S_CONFIG::SdCardPowerEnableActiveHigh
UINT8 SdCardPowerEnableActiveHigh
Offset 0x0147 - SdCard power enable polarity Choose SD_PWREN# polarity 0: Active low, 1: Active high.
Definition: FspsUpd.h:487
FSP_S_CONFIG::IslVrCmd
UINT8 IslVrCmd
Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.
Definition: FspsUpd.h:1099
FSP_S_CONFIG::BiosGuardModulePtr
UINT64 BiosGuardModulePtr
Offset 0x077D - BiosGuardModulePtr BiosGuardModulePtr default values.
Definition: FspsUpd.h:2268
FSP_S_TEST_CONFIG::PowerLimit4
UINT32 PowerLimit4
Offset 0x0870 - Package PL4 power limit Package PL4 power limit.
Definition: FspsUpd.h:2970
FSP_S_CONFIG::SerialIoEnableDebugUartAfterPost
UINT8 SerialIoEnableDebugUartAfterPost
Offset 0x0707 - Enable Debug UART Controller Enable debug UART controller after post.
Definition: FspsUpd.h:1982
FSP_S_TEST_CONFIG::ProcessorTraceMemLength
UINT32 ProcessorTraceMemLength
Offset 0x07FB - Memory region allocation for Processor Trace Length in bytes of memory region allocat...
Definition: FspsUpd.h:2705
FSP_S_CONFIG::FastPkgCRampDisableSa
UINT8 FastPkgCRampDisableSa
Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew R...
Definition: FspsUpd.h:1014
FSP_S_TEST_CONFIG::SixCoreRatioLimit
UINT8 SixCoreRatioLimit
Offset 0x089B - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:3051
AZALIA_HEADER::RevisionId
UINT8 RevisionId
Revision ID of the codec. 0xFF matches any revision.
Definition: FspsUpd.h:47
FSP_S_TEST_CONFIG::PsysPowerLimit1Time
UINT8 PsysPowerLimit1Time
Offset 0x07E8 - PL1 timewindow PL1 timewindow in seconds.
Definition: FspsUpd.h:2632
FSP_S_CONFIG::PchLanEnable
UINT8 PchLanEnable
Offset 0x00FC - Enable LAN Enable/disable LAN controller.
Definition: FspsUpd.h:329
FSP_S_TEST_CONFIG::Custom1PowerLimit2
UINT32 Custom1PowerLimit2
Offset 0x087C - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for c...
Definition: FspsUpd.h:2988
FSP_S_CONFIG::PmcCpuC10GatePinEnable
UINT8 PmcCpuC10GatePinEnable
Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to ...
Definition: FspsUpd.h:2343
FSP_S_CONFIG::PchIshGp0GpioAssign
UINT8 PchIshGp0GpioAssign
Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1302
FSP_S_TEST_CONFIG::CstateLatencyControl3TimeUnit
UINT8 CstateLatencyControl3TimeUnit
Offset 0x0816 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid val...
Definition: FspsUpd.h:2852
FSP_S_TEST_CONFIG::BiProcHot
UINT8 BiProcHot
Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; ...
Definition: FspsUpd.h:2743
AUDIO_AZALIA_VERB_TABLE::Header
AZALIA_HEADER Header
AZALIA PCH header.
Definition: FspsUpd.h:57
FSP_S_CONFIG::PchMemoryThrottlingEnable
UINT8 PchMemoryThrottlingEnable
Offset 0x072B - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
Definition: FspsUpd.h:2168
FSP_S_CONFIG::PchLockDownBiosLock
UINT8 PchLockDownBiosLock
Offset 0x0393 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDC...
Definition: FspsUpd.h:1367
FSP_S_CONFIG::PchCrid
UINT8 PchCrid
Offset 0x0394 - PCH Compatibility Revision ID This member describes whether or not the CRID feature o...
Definition: FspsUpd.h:1373
FSP_S_CONFIG::SataLedEnable
UINT8 SataLedEnable
Offset 0x0150 - SATA LED SATA LED indicating SATA controller activity.
Definition: FspsUpd.h:540
FSP_S_CONFIG::PchHdaVerbTablePtr
UINT32 PchHdaVerbTablePtr
Offset 0x008D - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table.
Definition: FspsUpd.h:258
FSP_S_TEST_CONFIG::OneCoreRatioLimit
UINT8 OneCoreRatioLimit
Offset 0x07CB - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:2459
FSP_S_CONFIG::SlpS0Override
UINT8 SlpS0Override
Offset 0x067A - SLP_S0# Override Select 'Auto', it will be auto-configured according to probe type...
Definition: FspsUpd.h:1669
FSP_S_TEST_CONFIG::PkgCStateUnDemotion
UINT8 PkgCStateUnDemotion
Offset 0x080E - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemoti...
Definition: FspsUpd.h:2803
FSP_S_TEST_CONFIG::PchHdaResetWaitTimer
UINT16 PchHdaResetWaitTimer
Offset 0x08BD - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of ...
Definition: FspsUpd.h:3150
FSP_S_TEST_CONFIG::EnergyEfficientPState
UINT8 EnergyEfficientPState
Offset 0x0801 - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state...
Definition: FspsUpd.h:2724
FSP_S_CONFIG::ReservedForFuture1
UINT8 ReservedForFuture1
Offset 0x070B - Reserved Reserved $EN_DIS.
Definition: FspsUpd.h:2006
FSP_S_CONFIG::PcieRpDpcMask
UINT32 PcieRpDpcMask
Offset 0x010C - DPC for PCIE RP Mask Enable/disable Downstream Port Containment for PCIE Root Ports...
Definition: FspsUpd.h:407
FSP_S_CONFIG::SataRstInterrupt
UINT8 SataRstInterrupt
Offset 0x07A7 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SAT...
Definition: FspsUpd.h:2320
FSP_S_CONFIG::PchPmPwrCycDur
UINT8 PchPmPwrCycDur
Offset 0x068A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second...
Definition: FspsUpd.h:1755
FSP_S_CONFIG::SendEcCmd
UINT64 SendEcCmd
Offset 0x0785 - SendEcCmd SendEcCmd function pointer.
Definition: FspsUpd.h:2275
FSP_S_CONFIG::ForcMebxSyncUp
UINT8 ForcMebxSyncUp
Offset 0x0161 - MEBX execution Enable/Disable.
Definition: FspsUpd.h:632
FSP_S_CONFIG::PmcPowerButtonDebounce
UINT32 PmcPowerButtonDebounce
Offset 0x0115 - Power button debounce configuration Debounce time for PWRBTN in microseconds.
Definition: FspsUpd.h:426
FSP_S_TEST_CONFIG::CdynmaxClampEnable
UINT8 CdynmaxClampEnable
Offset 0x07BC - Enable/Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable Cd...
Definition: FspsUpd.h:2419
FSP_S_TEST_CONFIG::Custom1ConfigTdpControl
UINT8 Custom1ConfigTdpControl
Offset 0x07DE - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1...
Definition: FspsUpd.h:2576
FSP_S_CONFIG::PchScsEmmcHs400RxStrobeDll1
UINT8 PchScsEmmcHs400RxStrobeDll1
Offset 0x06F7 - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode)...
Definition: FspsUpd.h:1931
FSP_S_TEST_CONFIG::CstateLatencyControl4Irtl
UINT16 CstateLatencyControl4Irtl
Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit...
Definition: FspsUpd.h:2941
FSP_S_CONFIG::PchPmSlpS3MinAssert
UINT8 PchPmSlpS3MinAssert
Offset 0x0676 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy.
Definition: FspsUpd.h:1644
FSP_S_TEST_CONFIG::C1StateAutoDemotion
UINT8 C1StateAutoDemotion
Offset 0x08A0 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion.
Definition: FspsUpd.h:3083
FSP_S_TEST_CONFIG::GtFreqMax
UINT8 GtFreqMax
Offset 0x07BE - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz...
Definition: FspsUpd.h:2439
FSP_S_CONFIG::PchPmSlpS4MinAssert
UINT8 PchPmSlpS4MinAssert
Offset 0x0677 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy.
Definition: FspsUpd.h:1649
FSP_S_CONFIG::PmcModPhySusPgEnable
UINT8 PmcModPhySusPgEnable
Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic...
Definition: FspsUpd.h:677
FSP_S_TEST_CONFIG::SkipPostBootSai
UINT8 SkipPostBootSai
Offset 0x0A72 - Skip POSTBOOT SAI Deprecated $EN_DIS.
Definition: FspsUpd.h:3282
FSP_S_TEST_CONFIG::EnableItbm
UINT8 EnableItbm
Offset 0x089E - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3...
Definition: FspsUpd.h:3071
FSP_S_CONFIG::PchPmSlpS0Vm075VSupport
UINT8 PchPmSlpS0Vm075VSupport
Offset 0x0154 - SLP_S0 VM 0.75V Support SLP_S0 Voltage Margining 0.75V Support Policy.
Definition: FspsUpd.h:565
FSP_S_CONFIG::PchHdaSndwBufferRcomp
UINT8 PchHdaSndwBufferRcomp
Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting 0: non-ACT - 50 Ohm driver impedance...
Definition: FspsUpd.h:395
FSP_S_CONFIG::CpuBistData
UINT32 CpuBistData
Offset 0x0315 - CpuBistData Pointer CPU BIST Data.
Definition: FspsUpd.h:1093
FSP_S_TEST_CONFIG::CstateLatencyControl3Irtl
UINT16 CstateLatencyControl3Irtl
Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit...
Definition: FspsUpd.h:2936
FSP_S_CONFIG::GraphicsConfigPtr
UINT32 GraphicsConfigPtr
Offset 0x0028 - Graphics Configuration Ptr Points to VBT.
Definition: FspsUpd.h:101
FSP_S_TEST_CONFIG::PkgCStateLimit
UINT8 PkgCStateLimit
Offset 0x0812 - Set the Max Pkg Cstate Set the Max Pkg Cstate.
Definition: FspsUpd.h:2828
FSP_S_CONFIG::PchTTEnable
UINT8 PchTTEnable
Offset 0x0713 - Enable The Thermal Throttle Enable the thermal throttle function. ...
Definition: FspsUpd.h:2033
FSP_S_CONFIG::PchScsEmmcHs400TuningRequired
UINT8 PchScsEmmcHs400TuningRequired
Offset 0x06F5 - Enable eMMC HS400 Training Deprecated.
Definition: FspsUpd.h:1920
FSP_S_CONFIG::UnusedUpdSpace16
UINT8 UnusedUpdSpace16
Offset 0x0664.
Definition: FspsUpd.h:1551
FSP_S_CONFIG::ManageabilityMode
UINT8 ManageabilityMode
Offset 0x0158 - Manageability Mode set by Mebx Enable/Disable.
Definition: FspsUpd.h:589
FSP_S_CONFIG::SendVrMbxCmd
UINT8 SendVrMbxCmd
Offset 0x0303 - Enable VR specific mailbox command VR specific mailbox commands.
Definition: FspsUpd.h:1022
FSP_S_CONFIG::CdClock
UINT8 CdClock
Offset 0x0217 - CdClock Frequency selection 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz 0: ...
Definition: FspsUpd.h:733
FSP_S_CONFIG::XdciEnable
UINT8 XdciEnable
Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller.
Definition: FspsUpd.h:197
FSP_S_TEST_CONFIG::Custom2PowerLimit1Time
UINT8 Custom2PowerLimit1Time
Offset 0x07DF - Custom Short term Power Limit time window Short term Power Limit time window value fo...
Definition: FspsUpd.h:2582
FSP_S_TEST_CONFIG::DisableD0I3SettingForHeci
UINT8 DisableD0I3SettingForHeci
Offset 0x08BC - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disabl...
Definition: FspsUpd.h:3145
FSP_S_CONFIG::SataP1T3M
UINT8 SataP1T3M
Offset 0x0724 - Port 1 T3 Multipler Port 1 T3 Multipler.
Definition: FspsUpd.h:2129
FSP_S_TEST_CONFIG::C1StateUnDemotion
UINT8 C1StateUnDemotion
Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion...
Definition: FspsUpd.h:3089
FSP_S_TEST_CONFIG::DmiIot
UINT8 DmiIot
Offset 0x07B5 - DMI IOT Control Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Con...
Definition: FspsUpd.h:2395
FSP_S_CONFIG::PsOnEnable
UINT8 PsOnEnable
Offset 0x07A9 - Enable PS_ON.
Definition: FspsUpd.h:2336
FSP_S_TEST_CONFIG::Signature
UINT32 Signature
Offset 0x07AD.
Definition: FspsUpd.h:2362
FSP_S_TEST_CONFIG::TimedMwait
UINT8 TimedMwait
Offset 0x0810 - Enable or Disable TimedMwait Support.
Definition: FspsUpd.h:2815
FSP_S_CONFIG::RampDown
UINT8 RampDown
Offset 0x032A - Ramp Down Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range...
Definition: FspsUpd.h:1133
FSP_S_CONFIG::UnusedUpdSpace7
UINT8 UnusedUpdSpace7
Offset 0x0219.
Definition: FspsUpd.h:743
FSP_S_TEST_CONFIG::ConfigTdpBios
UINT8 ConfigTdpBios
Offset 0x07E6 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disabl...
Definition: FspsUpd.h:2620
FSP_S_CONFIG::PchDmiTsawEn
UINT8 PchDmiTsawEn
Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable...
Definition: FspsUpd.h:2064
FSP_S_TEST_CONFIG::Custom1PowerLimit1
UINT32 Custom1PowerLimit1
Offset 0x0878 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for...
Definition: FspsUpd.h:2982
FSP_S_CONFIG::AsfEnabled
UINT8 AsfEnabled
Offset 0x0157 - ASF Switch Enable/Disable.
Definition: FspsUpd.h:583
FSP_S_TEST_CONFIG::DmiExtSync
UINT8 DmiExtSync
Offset 0x07B4 - DMI Extended Sync Control Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control $EN_DIS.
Definition: FspsUpd.h:2389
FSP_S_CONFIG::PchPmPciePllSsc
UINT8 PchPmPciePllSsc
Offset 0x068B - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage.
Definition: FspsUpd.h:1761
FSP_S_TEST_CONFIG::PchLockDownGlobalSmi
UINT8 PchLockDownGlobalSmi
Offset 0x08BF - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bi...
Definition: FspsUpd.h:3156
FSP_S_TEST_CONFIG::FourCoreRatioLimit
UINT8 FourCoreRatioLimit
Offset 0x07CE - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:2477
FSP_S_CONFIG::PeiGraphicsPeimInit
UINT8 PeiGraphicsPeimInit
Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS.
Definition: FspsUpd.h:739
FSP_S_CONFIG::MicrocodeRegionBase
UINT32 MicrocodeRegionBase
Offset 0x0038 - MicrocodeRegionBase Memory Base of Microcode Updates.
Definition: FspsUpd.h:150
FSP_S_TEST_CONFIG::PchPmDisableEnergyReport
UINT8 PchPmDisableEnergyReport
Offset 0x0A5E - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature.
Definition: FspsUpd.h:3259
FSP_S_CONFIG::TcoIrqSelect
UINT8 TcoIrqSelect
Offset 0x008A - Select TcoIrqSelect TCO IRQ Select.
Definition: FspsUpd.h:242
FSP_S_TEST_CONFIG::Custom1PowerLimit1Time
UINT8 Custom1PowerLimit1Time
Offset 0x07DC - Custom Short term Power Limit time window Short term Power Limit time window value fo...
Definition: FspsUpd.h:2566
FSP_S_CONFIG::SlpS0DisQForDebug
UINT8 SlpS0DisQForDebug
Offset 0x067B - S0ix Override Settings Select 'Auto', it will be auto-configured according to probe t...
Definition: FspsUpd.h:1680
FSP_S_TEST_CONFIG::VoltageOptimization
UINT8 VoltageOptimization
Offset 0x07FF - Enable or Disable Voltage Optimization feature Enable or Disable Voltage Optimization...
Definition: FspsUpd.h:2711
FSP_S_CONFIG::PchPmWoWlanEnable
UINT8 PchPmWoWlanEnable
Offset 0x0672 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP...
Definition: FspsUpd.h:1620
FSP_S_CONFIG::PcieRpDpcExtensionsMask
UINT32 PcieRpDpcExtensionsMask
Offset 0x0110 - DPC Extensions PCIE RP Mask Enable/disable DPC Extensions for PCIE Root Ports...
Definition: FspsUpd.h:413
FSP_S_TEST_CONFIG::PchXhciOcLock
UINT8 PchXhciOcLock
Offset 0x0A60 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS wi...
Definition: FspsUpd.h:3272
FSP_S_CONFIG::PchPmDisableDsxAcPresentPulldown
UINT8 PchPmDisableDsxAcPresentPulldown
Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_P...
Definition: FspsUpd.h:1721
FSP_S_CONFIG::McivrRfiFrequencyPrefix
UINT8 McivrRfiFrequencyPrefix
Offset 0x030D - McIVR RFI Frequency Prefix PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix...
Definition: FspsUpd.h:1049
FSP_S_CONFIG::PchPmWolOvrWkSts
UINT8 PchPmWolOvrWkSts
Offset 0x0689 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRS...
Definition: FspsUpd.h:1749
FSP_S_TEST_CONFIG::DebugInterfaceLockEnable
UINT8 DebugInterfaceLockEnable
Offset 0x07EF - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: D...
Definition: FspsUpd.h:2675
FSP_S_CONFIG::PchHdaAudioLinkSndw2
UINT8 PchHdaAudioLinkSndw2
Offset 0x0104 - Enable HD Audio SoundWire#2 Link Enable/disable HD Audio SNDW2 link.
Definition: FspsUpd.h:377
FSP_S_CONFIG::SataPwrOptEnable
UINT8 SataPwrOptEnable
Offset 0x068D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side.
Definition: FspsUpd.h:1771
FSP_S_CONFIG::SlowSlewRateForFivr
UINT8 SlowSlewRateForFivr
Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain Slew Rate config...
Definition: FspsUpd.h:1088
FSP_S_CONFIG::PchHdaAudioLinkSndw1
UINT8 PchHdaAudioLinkSndw1
Offset 0x0103 - Enable HD Audio SoundWire#1 Link Enable/disable HD Audio SNDW1 link.
Definition: FspsUpd.h:371
FSP_S_CONFIG::PchSirqMode
UINT8 PchSirqMode
Offset 0x0709 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode...
Definition: FspsUpd.h:1994
FSP_S_CONFIG::PcieRpImrEnabled
UINT8 PcieRpImrEnabled
Offset 0x066D - PCIE IMR Enables Isolated Memory Region for PCIe.
Definition: FspsUpd.h:1593
FSP_S_CONFIG::SkipMpInit
UINT8 SkipMpInit
Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization.
Definition: FspsUpd.h:1043
FSP_S_CONFIG::PchIshUart0GpioAssign
UINT8 PchIshUart0GpioAssign
Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1272
FSP_S_TEST_CONFIG::Custom1TurboActivationRatio
UINT8 Custom1TurboActivationRatio
Offset 0x07DD - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1...
Definition: FspsUpd.h:2571
FSP_S_CONFIG::UnusedUpdSpace23
UINT8 UnusedUpdSpace23
Offset 0x0753.
Definition: FspsUpd.h:2237
FSP_S_CONFIG::UnusedUpdSpace20
UINT8 UnusedUpdSpace20
Offset 0x068C.
Definition: FspsUpd.h:1765
AZALIA_HEADER::SdiNum
UINT8 SdiNum
SDI number, 0xFF matches any SDI.
Definition: FspsUpd.h:48
FSP_S_TEST_CONFIG::PowerLimit2
UINT8 PowerLimit2
Offset 0x07D2 - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode.
Definition: FspsUpd.h:2503
FSP_S_CONFIG::SiNumberOfSsidTableEntry
UINT16 SiNumberOfSsidTableEntry
Offset 0x07A5.
Definition: FspsUpd.h:2314
FSP_S_CONFIG::SataRstHddUnlock
UINT8 SataRstHddUnlock
Offset 0x06E8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled...
Definition: FspsUpd.h:1880
FSP_S_CONFIG::SataMode
UINT8 SataMode
Offset 0x0093 - SATA Mode Select SATA controller working mode.
Definition: FspsUpd.h:275
FSP_S_CONFIG::PchHdaAudioLinkSsp0
UINT8 PchHdaAudioLinkSsp0
Offset 0x0100 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP0/I2S link.
Definition: FspsUpd.h:353
FSP_S_CONFIG::SataRstRaid5
UINT8 SataRstRaid5
Offset 0x06E4 - PCH Sata Rst Raid5 RAID5.
Definition: FspsUpd.h:1857
FSP_S_TEST_CONFIG::RaceToHalt
UINT8 RaceToHalt
Offset 0x081C - Race To Halt Enable/Disable Race To Halt feature.
Definition: FspsUpd.h:2889
FSP_S_CONFIG::SkipS3CdClockInit
UINT8 SkipS3CdClockInit
Offset 0x0231 - Enable/Disable SkipS3CdClockInit Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent $EN_DIS.
Definition: FspsUpd.h:821
FSP_S_CONFIG::PchHdaAudioLinkSndw3
UINT8 PchHdaAudioLinkSndw3
Offset 0x0105 - Enable HD Audio SoundWire#3 Link Enable/disable HD Audio SNDW3 link.
Definition: FspsUpd.h:383
FSP_S_TEST_CONFIG::TStates
UINT8 TStates
Offset 0x0803 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable...
Definition: FspsUpd.h:2737
FSP_S_TEST_CONFIG::ProcessorTraceOutputScheme
UINT8 ProcessorTraceOutputScheme
Offset 0x07F1 - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0:...
Definition: FspsUpd.h:2687
FspUpd.h
Copyright (c) 2018, Intel Corporation.
FSP_S_TEST_CONFIG::CstateLatencyControl2TimeUnit
UINT8 CstateLatencyControl2TimeUnit
Offset 0x0815 - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid val...
Definition: FspsUpd.h:2846
FSP_S_CONFIG::BltBufferSize
UINT32 BltBufferSize
Offset 0x0238 - Blt Buffer Size Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (t...
Definition: FspsUpd.h:839
FSP_S_CONFIG::PchHotEnable
UINT8 PchHotEnable
Offset 0x014F - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel...
Definition: FspsUpd.h:534
AZALIA_HEADER::DataDwords
UINT16 DataDwords
Number of data DWORDs pointed by the codec data buffer.
Definition: FspsUpd.h:49
FSP_S_CONFIG::UnusedUpdSpace17
UINT8 UnusedUpdSpace17
Offset 0x066F.
Definition: FspsUpd.h:1602
FSP_S_CONFIG::CpuMpHob
UINT32 CpuMpHob
Offset 0x032F - CpuMpHob Pointer for CpuMpHob.
Definition: FspsUpd.h:1143
FSP_S_TEST_CONFIG::CstateLatencyControl5Irtl
UINT16 CstateLatencyControl5Irtl
Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit...
Definition: FspsUpd.h:2946
FSP_S_TEST_CONFIG::SevenCoreRatioLimit
UINT8 SevenCoreRatioLimit
Offset 0x089C - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:3058
FSP_S_TEST_CONFIG::TwoCoreRatioLimit
UINT8 TwoCoreRatioLimit
Offset 0x07CC - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:2465
FSP_S_TEST_CONFIG::PowerLimit3DutyCycle
UINT8 PowerLimit3DutyCycle
Offset 0x07D5 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100...
Definition: FspsUpd.h:2519
FSP_S_CONFIG::PchPmLanWakeFromDeepSx
UINT8 PchPmLanWakeFromDeepSx
Offset 0x0674 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx...
Definition: FspsUpd.h:1633
FSP_S_TEST_CONFIG::ConfigTdpLock
UINT8 ConfigTdpLock
Offset 0x07E5 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0...
Definition: FspsUpd.h:2614
FSP_S_CONFIG::SataThermalSuggestedSetting
UINT8 SataThermalSuggestedSetting
Offset 0x072A - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting...
Definition: FspsUpd.h:2162
FSP_S_CONFIG::SgxSinitNvsData
UINT8 SgxSinitNvsData
Offset 0x079F - SgxSinitNvsData SgxSinitNvsData default values.
Definition: FspsUpd.h:2300
FSP_S_CONFIG::WatchDog
UINT8 WatchDog
Offset 0x0156 - WatchDog Timer Switch Enable/Disable.
Definition: FspsUpd.h:577
FSP_S_TEST_CONFIG::ApIdleManner
UINT8 ApIdleManner
Offset 0x07F0 - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; ...
Definition: FspsUpd.h:2681
FSP_S_CONFIG::DmiTS0TW
UINT8 DmiTS0TW
Offset 0x071A - Thermal Sensor 0 Target Width DMT thermal sensor suggested representative values...
Definition: FspsUpd.h:2076
FSP_S_TEST_CONFIG::MaxRatio
UINT8 MaxRatio
Offset 0x081D - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F.
Definition: FspsUpd.h:2894
FSP_S_TEST_CONFIG::MachineCheckEnable
UINT8 MachineCheckEnable
Offset 0x07ED - Enable or Disable initialization of machine check registers Enable or Disable initial...
Definition: FspsUpd.h:2663
FSP_S_CONFIG::EcCmdLock
UINT8 EcCmdLock
Offset 0x078E - EcCmdLock EcCmdLock default values.
Definition: FspsUpd.h:2285
FSP_S_TEST_CONFIG::Custom2PowerLimit2
UINT32 Custom2PowerLimit2
Offset 0x0884 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for c...
Definition: FspsUpd.h:3000
FSPS_UPD
Fsp S UPD Configuration.
Definition: FspsUpd.h:3297
FSP_S_CONFIG::SataEnable
UINT8 SataEnable
Offset 0x0092 - Enable SATA Enable/disable SATA controller.
Definition: FspsUpd.h:269
FSP_S_CONFIG::PchHdaIDispLinkTmode
UINT8 PchHdaIDispLinkTmode
Offset 0x036B - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T...
Definition: FspsUpd.h:1222
FSP_S_TEST_CONFIG::PowerLimit4Lock
UINT8 PowerLimit4Lock
Offset 0x07D7 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS...
Definition: FspsUpd.h:2531
FSP_S_CONFIG::UnusedUpdSpace4
UINT8 UnusedUpdSpace4
Offset 0x014E.
Definition: FspsUpd.h:528
FSP_S_CONFIG::UnusedUpdSpace10
UINT8 UnusedUpdSpace10
Offset 0x0367.
Definition: FspsUpd.h:1198
FSP_S_CONFIG::PchPmLpcClockRun
UINT8 PchPmLpcClockRun
Offset 0x0680 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of...
Definition: FspsUpd.h:1698
FSP_S_CONFIG::ChipsetInitBinLen
UINT32 ChipsetInitBinLen
Offset 0x0124 - Length of ChipsetInit Binary ChipsetInit Binary Length.
Definition: FspsUpd.h:462
FSP_S_CONFIG::SataRstRaidDeviceId
UINT8 SataRstRaidDeviceId
Offset 0x06E0 - PCH Sata Rst Raid Device Id Enable RAID Alternate ID.
Definition: FspsUpd.h:1833
FSP_S_CONFIG::AesEnable
UINT8 AesEnable
Offset 0x0277 - Advanced Encryption Standard (AES) feature Enable or Disable Advanced Encryption Stan...
Definition: FspsUpd.h:857
FSP_S_TEST_CONFIG::EightCoreRatioLimit
UINT8 EightCoreRatioLimit
Offset 0x089D - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:3065
FSP_S_CONFIG::SerialIoUart0PinMuxing
UINT8 SerialIoUart0PinMuxing
Offset 0x0701 - PcdSerialIoUart0PinMuxing Select SerialIo Uart0 pin muxing.
Definition: FspsUpd.h:1960
FSP_S_CONFIG::SataP1T1M
UINT8 SataP1T1M
Offset 0x0722 - Port 1 T1 Multipler Port 1 T1 Multipler.
Definition: FspsUpd.h:2119
FSP_S_CONFIG::SataP0T3M
UINT8 SataP0T3M
Offset 0x0720 - Port 0 T3 Multipler Port 0 T3 Multipler.
Definition: FspsUpd.h:2109
FSP_S_TEST_CONFIG::TccOffsetLock
UINT8 TccOffsetLock
Offset 0x07DA - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock ...
Definition: FspsUpd.h:2554
FSP_S_CONFIG::PchScsEmmcHs400DriverStrength
UINT8 PchScsEmmcHs400DriverStrength
Offset 0x06F9 - I/O Driver Strength Deprecated.
Definition: FspsUpd.h:1942
FSP_S_CONFIG::LogoSize
UINT32 LogoSize
Offset 0x0024 - Logo Size Size of PEI Display Logo Image.
Definition: FspsUpd.h:96
FSP_S_CONFIG::NumOfDevIntConfig
UINT8 NumOfDevIntConfig
Offset 0x007F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry...
Definition: FspsUpd.h:220
FSP_S_TEST_CONFIG::Hwp
UINT8 Hwp
Offset 0x07CF - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support.
Definition: FspsUpd.h:2484
FSP_S_CONFIG::AmtSolEnabled
UINT8 AmtSolEnabled
Offset 0x015A - SOL Switch Enable/Disable.
Definition: FspsUpd.h:602
FSP_S_CONFIG::SataRstRaid1
UINT8 SataRstRaid1
Offset 0x06E2 - PCH Sata Rst Raid1 RAID1.
Definition: FspsUpd.h:1845
FSP_S_TEST_CONFIG::ProcHotLock
UINT8 ProcHotLock
Offset 0x081A - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: ...
Definition: FspsUpd.h:2875
FSP_S_CONFIG::DdiPortFHpd
UINT8 DdiPortFHpd
Offset 0x022C - Enable or disable HPD of DDI port F 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:790
FSP_S_CONFIG::PchIshPdtUnlock
UINT8 PchIshPdtUnlock
Offset 0x038E - PCH ISH PDT Unlock Msg 0: False; 1: True.
Definition: FspsUpd.h:1350
FSP_S_CONFIG::SataRstOromUiBanner
UINT8 SataRstOromUiBanner
Offset 0x06E6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER.
Definition: FspsUpd.h:1869
FSP_S_TEST_CONFIG::AutoThermalReporting
UINT8 AutoThermalReporting
Offset 0x0808 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI ...
Definition: FspsUpd.h:2767
FSP_S_CONFIG::ShowSpiController
UINT8 ShowSpiController
Offset 0x0034 - Show SPI controller Enable/disable to show SPI controller.
Definition: FspsUpd.h:141
FSP_S_CONFIG::FwProgress
UINT8 FwProgress
Offset 0x0159 - PET Progress Enable/Disable.
Definition: FspsUpd.h:596
FSP_S_CONFIG::EnableTcoTimer
UINT8 EnableTcoTimer
Offset 0x0758 - Enable TCO timer.
Definition: FspsUpd.h:2253
FSP_S_CONFIG::DebugInterfaceEnable
UINT8 DebugInterfaceEnable
Offset 0x0333 - Enable or Disable processor debug features Enable or Disable processor debug features...
Definition: FspsUpd.h:1149
FSP_S_CONFIG::DevIntConfigPtr
UINT32 DevIntConfigPtr
Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
Definition: FspsUpd.h:214
FSP_S_CONFIG::SciIrqSelect
UINT8 SciIrqSelect
Offset 0x0089 - Select SciIrqSelect SCI IRQ Select.
Definition: FspsUpd.h:237
FSP_S_CONFIG::DdiPortFDdc
UINT8 DdiPortFDdc
Offset 0x0230 - Enable or disable DDC of DDI port F 0(Default)=Disable, 1=Enable $EN_DIS.
Definition: FspsUpd.h:814
FSP_S_CONFIG::Heci3Enabled
UINT8 Heci3Enabled
Offset 0x014D - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not i...
Definition: FspsUpd.h:524
FSP_S_TEST_CONFIG::TccOffsetClamp
UINT8 TccOffsetClamp
Offset 0x07D9 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limi...
Definition: FspsUpd.h:2547
FSP_S_TEST_CONFIG::Custom3TurboActivationRatio
UINT8 Custom3TurboActivationRatio
Offset 0x07E3 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3...
Definition: FspsUpd.h:2603
FSP_S_TEST_CONFIG::MonitorMwaitEnable
UINT8 MonitorMwaitEnable
Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instru...
Definition: FspsUpd.h:2657
FSP_S_CONFIG::PchT0Level
UINT16 PchT0Level
Offset 0x070D - Thermal Throttling Custimized T0Level Value Custimized T0Level value.
Definition: FspsUpd.h:2017
FSPS_UPD::FspsConfig
FSP_S_CONFIG FspsConfig
Offset 0x0020.
Definition: FspsUpd.h:3305
FSP_S_CONFIG::PchIshGp2GpioAssign
UINT8 PchIshGp2GpioAssign
Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1314
FSP_S_CONFIG::PchDmiAspm
UINT8 PchDmiAspm
Offset 0x0346 - Enable DMI ASPM Deprecated.
Definition: FspsUpd.h:1161
FSP_S_TEST_CONFIG::CstateLatencyControl5TimeUnit
UINT8 CstateLatencyControl5TimeUnit
Offset 0x0818 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid val...
Definition: FspsUpd.h:2863
FSP_S_CONFIG::PsysOffset
UINT8 PsysOffset
Offset 0x02A1 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction...
Definition: FspsUpd.h:917
FSP_S_CONFIG::DdiPortBHpd
UINT8 DdiPortBHpd
Offset 0x0229 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:772
FSP_S_TEST_CONFIG::PowerLimit3Lock
UINT8 PowerLimit3Lock
Offset 0x07D6 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS...
Definition: FspsUpd.h:2525
FSP_S_CONFIG::DdiPortDDdc
UINT8 DdiPortDDdc
Offset 0x022F - Enable or disable DDC of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:808
FSP_S_CONFIG::SataRstOromUiDelay
UINT8 SataRstOromUiDelay
Offset 0x06E7 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PC...
Definition: FspsUpd.h:1874
SiPchNoInt
No Interrupt Pin.
Definition: FspsUpd.h:65
FSP_S_TEST_CONFIG::FiveCoreRatioLimit
UINT8 FiveCoreRatioLimit
Offset 0x089A - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 25...
Definition: FspsUpd.h:3044
FSP_S_CONFIG::TTSuggestedSetting
UINT8 TTSuggestedSetting
Offset 0x0716 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting...
Definition: FspsUpd.h:2052
FSP_S_CONFIG::PsysSlope
UINT8 PsysSlope
Offset 0x02A0 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction...
Definition: FspsUpd.h:911
FSP_S_CONFIG::DdiPortCHpd
UINT8 DdiPortCHpd
Offset 0x022A - Enable or disable HPD of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:778
FSP_S_CONFIG::PchPmDeepSxPol
UINT8 PchPmDeepSxPol
Offset 0x0675 - PCH Pm Deep Sx Pol Deep Sx Policy.
Definition: FspsUpd.h:1639
FSP_S_CONFIG::PchIoApicEntry24_119
UINT8 PchIoApicEntry24_119
Offset 0x037D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable.
Definition: FspsUpd.h:1251
FSP_S_CONFIG::AmtKvmEnabled
UINT8 AmtKvmEnabled
Offset 0x0160 - KVM Switch Enable/Disable.
Definition: FspsUpd.h:626
FSP_S_TEST_CONFIG::CStatePreWake
UINT8 CStatePreWake
Offset 0x080F - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake.
Definition: FspsUpd.h:2809
FSP_S_CONFIG::SataRstRaid0
UINT8 SataRstRaid0
Offset 0x06E1 - PCH Sata Rst Raid0 RAID0.
Definition: FspsUpd.h:1839
FSP_S_CONFIG::SgxEpoch1
UINT64 SgxEpoch1
Offset 0x0797 - SgxEpoch1 SgxEpoch1 default values.
Definition: FspsUpd.h:2295
FSP_S_CONFIG::FastPkgCRampDisableFivr
UINT8 FastPkgCRampDisableFivr
Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain Disable Fast Slew...
Definition: FspsUpd.h:1081
FSP_S_CONFIG::PchPmSlpLanLowDc
UINT8 PchPmSlpLanLowDc
Offset 0x0682 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power.
Definition: FspsUpd.h:1710
FSP_S_CONFIG::SataRstRaid10
UINT8 SataRstRaid10
Offset 0x06E3 - PCH Sata Rst Raid10 RAID10.
Definition: FspsUpd.h:1851
FSP_S_TEST_CONFIG::CstCfgCtrIoMwaitRedirection
UINT8 CstCfgCtrIoMwaitRedirection
Offset 0x0811 - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; ...
Definition: FspsUpd.h:2821
FSP_S_CONFIG::PchHdaLinkFrequency
UINT8 PchHdaLinkFrequency
Offset 0x0369 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz...
Definition: FspsUpd.h:1210
FSP_S_TEST_CONFIG::PsysPowerLimit1
UINT8 PsysPowerLimit1
Offset 0x07E7 - PL1 Enable value PL1 Enable value to limit average platform power.
Definition: FspsUpd.h:2626
FSP_S_TEST_CONFIG::ThermalMonitor
UINT8 ThermalMonitor
Offset 0x0809 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: E...
Definition: FspsUpd.h:2773
FSP_S_CONFIG::UnusedUpdSpace3
UINT8 UnusedUpdSpace3
Offset 0x014A.
Definition: FspsUpd.h:505
FSP_S_CONFIG::DmiSuggestedSetting
UINT8 DmiSuggestedSetting
Offset 0x0719 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative valu...
Definition: FspsUpd.h:2070
FSP_S_CONFIG::PchIshGp6GpioAssign
UINT8 PchIshGp6GpioAssign
Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1338
FSP_S_CONFIG::PchHdaDspEnable
UINT8 PchHdaDspEnable
Offset 0x002D - Enable HD Audio DSP Enable/disable HD Audio DSP feature.
Definition: FspsUpd.h:113
FSP_S_CONFIG::DmiTS1TW
UINT8 DmiTS1TW
Offset 0x071B - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width.
Definition: FspsUpd.h:2082
FSP_S_CONFIG::AcousticNoiseMitigation
UINT8 AcousticNoiseMitigation
Offset 0x02A2 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature...
Definition: FspsUpd.h:925
FSP_S_CONFIG::PchScsEmmcHs400TxDataDll
UINT8 PchScsEmmcHs400TxDataDll
Offset 0x06F8 - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode)...
Definition: FspsUpd.h:1936
FSP_S_TEST_CONFIG::ConfigTdpLevel
UINT8 ConfigTdpLevel
Offset 0x081B - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nom...
Definition: FspsUpd.h:2881
FSP_S_CONFIG::EcCmdProvisionEav
UINT8 EcCmdProvisionEav
Offset 0x078D - EcCmdProvisionEav Ephemeral Authorization Value default values.
Definition: FspsUpd.h:2280
FSP_S_CONFIG::BiosGuardAttr
UINT32 BiosGuardAttr
Offset 0x0779 - BiosGuardAttr BiosGuardAttr default values.
Definition: FspsUpd.h:2263
FSPS_UPD::FspUpdHeader
FSP_UPD_HEADER FspUpdHeader
Offset 0x0000.
Definition: FspsUpd.h:3301
FSP_S_CONFIG::Device4Enable
UINT8 Device4Enable
Offset 0x002C - Enable Device 4 Enable/disable Device 4 $EN_DIS.
Definition: FspsUpd.h:107
FSP_S_CONFIG::PchHdaAudioLinkHda
UINT8 PchHdaAudioLinkHda
Offset 0x00FD - Enable HD Audio Link Enable/disable HD Audio Link.
Definition: FspsUpd.h:335
FSP_S_CONFIG::PchTTState13Enable
UINT8 PchTTState13Enable
Offset 0x0714 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 1...
Definition: FspsUpd.h:2040
SI_PCH_DEVICE_INTERRUPT_CONFIG::Irq
UINT8 Irq
IRQ to be set for device.
Definition: FspsUpd.h:78
FSPS_UPD::UpdTerminator
UINT16 UpdTerminator
Offset 0x0A80.
Definition: FspsUpd.h:3313
FSP_S_CONFIG::SlowSlewRateForGt
UINT8 SlowSlewRateForGt
Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configur...
Definition: FspsUpd.h:946
FSP_S_TEST_CONFIG::PchUnlockGpioPads
UINT8 PchUnlockGpioPads
Offset 0x08C1 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose...
Definition: FspsUpd.h:3168
FSP_S_TEST_CONFIG::Custom2TurboActivationRatio
UINT8 Custom2TurboActivationRatio
Offset 0x07E0 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2...
Definition: FspsUpd.h:2587
FSP_S_CONFIG::TurboMode
UINT8 TurboMode
Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode.
Definition: FspsUpd.h:161
FSP_S_CONFIG::PchScsEmmcHs400DllDataValid
UINT8 PchScsEmmcHs400DllDataValid
Offset 0x06F6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid.
Definition: FspsUpd.h:1926
FSP_S_CONFIG::PchHdaPme
UINT8 PchHdaPme
Offset 0x0366 - Enable Pme Enable Azalia wake-on-ring.
Definition: FspsUpd.h:1194
FSP_S_TEST_CONFIG::CstateLatencyControl1TimeUnit
UINT8 CstateLatencyControl1TimeUnit
Offset 0x0814 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid val...
Definition: FspsUpd.h:2840
FSP_S_CONFIG::PchHdaVcType
UINT8 PchHdaVcType
Offset 0x0368 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1.
Definition: FspsUpd.h:1204
FSP_S_CONFIG::PchTsmicLock
UINT8 PchTsmicLock
Offset 0x070C - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip...
Definition: FspsUpd.h:2012
FSP_S_TEST_CONFIG::PowerLimit3Time
UINT8 PowerLimit3Time
Offset 0x07D4 - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms...
Definition: FspsUpd.h:2514
FSP_S_CONFIG::PchIshGp5GpioAssign
UINT8 PchIshGp5GpioAssign
Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1332
FSP_S_CONFIG::PchHdaIDispCodecDisconnect
UINT8 PchHdaIDispCodecDisconnect
Offset 0x036D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
Definition: FspsUpd.h:1235
FSP_S_CONFIG::Reserved2
UINT8 Reserved2
Offset 0x0304 - Reserved Reserved.
Definition: FspsUpd.h:1027
FSP_S_CONFIG::WatchDogTimerOs
UINT16 WatchDogTimerOs
Offset 0x015B - OS Timer 16 bits Value, Set OS watchdog timer.
Definition: FspsUpd.h:608
FSP_S_CONFIG::TetonGlacierSupport
UINT8 TetonGlacierSupport
Offset 0x0667 - Teton Glacier Support Enables support for the Teton Glacier card. ...
Definition: FspsUpd.h:1570
FSP_S_TEST_CONFIG::PmgCstCfgCtrlLock
UINT8 PmgCstCfgCtrlLock
Offset 0x080B - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable...
Definition: FspsUpd.h:2785
FSP_S_CONFIG::PchIshGp1GpioAssign
UINT8 PchIshGp1GpioAssign
Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1308
FSP_S_CONFIG::PchHdaDspUaaCompliance
UINT8 PchHdaDspUaaCompliance
Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (...
Definition: FspsUpd.h:1229
FSP_S_TEST_CONFIG::HwpInterruptControl
UINT8 HwpInterruptControl
Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Ena...
Definition: FspsUpd.h:3037
FSP_S_CONFIG::DmiTS3TW
UINT8 DmiTS3TW
Offset 0x071D - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width.
Definition: FspsUpd.h:2094
FSP_S_TEST_CONFIG::PowerLimit1Time
UINT8 PowerLimit1Time
Offset 0x07D1 - Package Long duration turbo mode time Package Long duration turbo mode time window in...
Definition: FspsUpd.h:2497
FSP_S_TEST_CONFIG::MlcSpatialPrefetcher
UINT8 MlcSpatialPrefetcher
Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0:...
Definition: FspsUpd.h:2651
FSP_S_CONFIG::TxtEnable
UINT8 TxtEnable
Offset 0x0305 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable.
Definition: FspsUpd.h:1033
FSP_S_TEST_CONFIG::Custom2ConfigTdpControl
UINT8 Custom2ConfigTdpControl
Offset 0x07E1 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1...
Definition: FspsUpd.h:2592
FSP_S_CONFIG::ScsSdCardEnabled
UINT8 ScsSdCardEnabled
Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller.
Definition: FspsUpd.h:135
FSP_S_CONFIG::SiCsmFlag
UINT8 SiCsmFlag
Offset 0x07A0 - Si Config CSM Flag.
Definition: FspsUpd.h:2306
FSP_S_CONFIG::EsataSpeedLimit
UINT8 EsataSpeedLimit
Offset 0x068E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
Definition: FspsUpd.h:1777
FSP_S_CONFIG::DeltaT12PowerCycleDelay
UINT16 DeltaT12PowerCycleDelay
Offset 0x0232 - Delta T12 Power Cycle Delay required in ms Select the value for delay required...
Definition: FspsUpd.h:828
FSP_S_TEST_CONFIG
Fsp S Test Configuration.
Definition: FspsUpd.h:2358
FSP_S_CONFIG::PchPwrOptEnable
UINT8 PchPwrOptEnable
Offset 0x0347 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side.
Definition: FspsUpd.h:1167
FSP_S_CONFIG::PchPcieDeviceOverrideTablePtr
UINT32 PchPcieDeviceOverrideTablePtr
Offset 0x0754 - Pch PCIE device override table pointer The PCIe device table is being used to overrid...
Definition: FspsUpd.h:2245
FSP_S_CONFIG::McivrRfiFrequencyAdjust
UINT8 McivrRfiFrequencyAdjust
Offset 0x030E - McIVR RFI Frequency Adjustment PCODE MMIO Mailbox: Adjust the RFI frequency relative ...
Definition: FspsUpd.h:1055
FSP_S_TEST_CONFIG::HdcControl
UINT8 HdcControl
Offset 0x07D0 - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration.
Definition: FspsUpd.h:2490
FSP_S_TEST_CONFIG::Custom3PowerLimit1Time
UINT8 Custom3PowerLimit1Time
Offset 0x07E2 - Custom Short term Power Limit time window Short term Power Limit time window value fo...
Definition: FspsUpd.h:2598
FSP_S_CONFIG::PchPmPcieWakeFromDeepSx
UINT8 PchPmPcieWakeFromDeepSx
Offset 0x0671 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx...
Definition: FspsUpd.h:1614
FSP_S_TEST_CONFIG::PsysPowerLimit1Power
UINT32 PsysPowerLimit1Power
Offset 0x0890 - Platform PL1 power Platform PL1 power.
Definition: FspsUpd.h:3018
FSP_S_CONFIG::CpuMpPpi
UINT32 CpuMpPpi
Offset 0x032B - CpuMpPpi Pointer for CpuMpPpi.
Definition: FspsUpd.h:1138
FSP_S_CONFIG::PchEnableComplianceMode
UINT8 PchEnableComplianceMode
Offset 0x0734 - Enable xHCI Compliance Mode Compliance Mode can be enabled for testing through this o...
Definition: FspsUpd.h:2195
FSP_S_CONFIG::SataSpeedLimit
UINT8 SataSpeedLimit
Offset 0x068F - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: ...
Definition: FspsUpd.h:1782
AUDIO_AZALIA_VERB_TABLE
Audio Azalia Verb Table structure.
Definition: FspsUpd.h:56
FSP_S_CONFIG::MicrocodeRegionSize
UINT32 MicrocodeRegionSize
Offset 0x003C - MicrocodeRegionSize Size of Microcode Updates.
Definition: FspsUpd.h:155
FSP_S_CONFIG::SataP1T2M
UINT8 SataP1T2M
Offset 0x0723 - Port 1 T2 Multipler Port 1 T2 Multipler.
Definition: FspsUpd.h:2124
FSP_S_CONFIG::ChipsetInitBinPtr
UINT32 ChipsetInitBinPtr
Offset 0x0120 - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer.
Definition: FspsUpd.h:457
FSP_S_CONFIG::SataRstLegacyOrom
UINT8 SataRstLegacyOrom
Offset 0x011A - PCH SATA use RST Legacy OROM Use PCH SATA RST Legacy OROM when CSM is Enabled $EN_DIS...
Definition: FspsUpd.h:438
FSP_S_CONFIG::PchIshGp3GpioAssign
UINT8 PchIshGp3GpioAssign
Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1320
FSP_S_CONFIG::SataRstSmartStorage
UINT8 SataRstSmartStorage
Offset 0x06EB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit.
Definition: FspsUpd.h:1899
FSP_S_TEST_CONFIG::TurboPowerLimitLock
UINT8 TurboPowerLimitLock
Offset 0x07D3 - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable ...
Definition: FspsUpd.h:2509
FSP_S_CONFIG::PchIshI2c2GpioAssign
UINT8 PchIshI2c2GpioAssign
Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1296
FSP_S_CONFIG::DdiPortBDdc
UINT8 DdiPortBDdc
Offset 0x022D - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:796
AUDIO_AZALIA_VERB_TABLE::Data
UINT32 * Data
Pointer to the data buffer. Its length is specified in the header.
Definition: FspsUpd.h:58
AZALIA_HEADER::VendorId
UINT16 VendorId
Codec Vendor ID.
Definition: FspsUpd.h:45
FSP_S_CONFIG::PchIoApicId
UINT8 PchIoApicId
Offset 0x037E - PCH Io Apic ID This member determines IOAPIC ID.
Definition: FspsUpd.h:1256
FSP_S_CONFIG::PchPmSlpS0Vm070VSupport
UINT8 PchPmSlpS0Vm070VSupport
Offset 0x0153 - SLP_S0 VM 0.70V Support SLP_S0 Voltage Margining 0.70V Support Policy.
Definition: FspsUpd.h:559
FSP_S_CONFIG::SgxEpoch0
UINT64 SgxEpoch0
Offset 0x078F - SgxEpoch0 SgxEpoch0 default values.
Definition: FspsUpd.h:2290
FSP_S_TEST_CONFIG::Cx
UINT8 Cx
Offset 0x080A - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-s...
Definition: FspsUpd.h:2779
FSP_S_CONFIG::SataP1TDispFinit
UINT8 SataP1TDispFinit
Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch.
Definition: FspsUpd.h:2156
FSP_S_CONFIG::PavpEnable
UINT8 PavpEnable
Offset 0x0216 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEn...
Definition: FspsUpd.h:727
FSP_S_CONFIG::SlpS0WithGbeSupport
UINT8 SlpS0WithGbeSupport
Offset 0x01FC - SlpS0WithGbeSupport Enable/Disable SLP_S0 with GBE Support.
Definition: FspsUpd.h:683
FSP_S_CONFIG::RampUp
UINT8 RampUp
Offset 0x0329 - Ramp Up Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range...
Definition: FspsUpd.h:1126
FSP_S_CONFIG::FastPkgCRampDisableGt
UINT8 FastPkgCRampDisableGt
Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew R...
Definition: FspsUpd.h:1007
FSP_S_CONFIG::PchLanLtrEnable
UINT8 PchLanLtrEnable
Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable.
Definition: FspsUpd.h:1356
FSP_S_CONFIG::SiSsidTablePtr
UINT32 SiSsidTablePtr
Offset 0x07A1.
Definition: FspsUpd.h:2310
FSP_S_TEST_CONFIG::PmSupport
UINT8 PmSupport
Offset 0x07BB - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS.
Definition: FspsUpd.h:2413
FSP_S_CONFIG::PchUsbOverCurrentEnable
UINT8 PchUsbOverCurrentEnable
Offset 0x0149 - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI control...
Definition: FspsUpd.h:501
FSP_S_CONFIG::PchHdaAudioLinkDmic0
UINT8 PchHdaAudioLinkDmic0
Offset 0x00FE - Enable HD Audio DMIC0 Link Enable/disable HD Audio DMIC0 link.
Definition: FspsUpd.h:341
FSP_S_CONFIG::PchSirqEnable
UINT8 PchSirqEnable
Offset 0x0708 - Enable Serial IRQ Determines if enable Serial IRQ.
Definition: FspsUpd.h:1988
FSP_S_CONFIG::TraceHubMemBase
UINT32 TraceHubMemBase
Offset 0x011B - Trace Hub Memory Base If Trace Hub is enabled and trace to memory is desired...
Definition: FspsUpd.h:445
FSP_S_CONFIG::DdiPortDHpd
UINT8 DdiPortDHpd
Offset 0x022B - Enable or disable HPD of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:784
FSP_S_CONFIG::UnusedUpdSpace12
UINT8 UnusedUpdSpace12
Offset 0x037F.
Definition: FspsUpd.h:1260
FSP_S_CONFIG::PchIshI2c0GpioAssign
UINT8 PchIshI2c0GpioAssign
Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1284
FSP_S_CONFIG::McivrSpreadSpectrum
UINT8 McivrSpreadSpectrum
Offset 0x0311 - McIVR RFI Spread Spectrum PCODE MMIO Mailbox: McIVR RFI Spread Spectrum.
Definition: FspsUpd.h:1068
FSP_S_TEST_CONFIG::PchPciePort8xhDecodePortIndex
UINT8 PchPciePort8xhDecodePortIndex
Offset 0x0A5D - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh De...
Definition: FspsUpd.h:3253
FSP_S_CONFIG::PchCnviMode
UINT8 PchCnviMode
Offset 0x0146 - CNVi Configuration This option allows for automatic detection of Connectivity Solutio...
Definition: FspsUpd.h:481
FSP_S_TEST_CONFIG::SataTestMode
UINT8 SataTestMode
Offset 0x0A5F - PCH Sata Test Mode Allow entrance to the PCH SATA test modes.
Definition: FspsUpd.h:3265
FSP_S_TEST_CONFIG::CstateLatencyControl4TimeUnit
UINT8 CstateLatencyControl4TimeUnit
Offset 0x0817 - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns ...
Definition: FspsUpd.h:2857
FSP_S_CONFIG::LogoPtr
UINT32 LogoPtr
Offset 0x0020 - Logo Pointer Points to PEI Display Logo Image.
Definition: FspsUpd.h:91
FSP_S_CONFIG::DmiAspm
UINT8 DmiAspm
Offset 0x0201 - DMI ASPM 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 0:Disable, 1:L0s, 2:L1, 3:L0sL1.
Definition: FspsUpd.h:699
FSP_S_TEST_CONFIG::DisableTurboGt
UINT8 DisableTurboGt
Offset 0x07BF - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT ...
Definition: FspsUpd.h:2445
FSP_S_TEST_CONFIG::SgxSinitDataFromTpm
UINT8 SgxSinitDataFromTpm
Offset 0x08BA - SgxSinitDataFromTpm SgxSinitDataFromTpm default values.
Definition: FspsUpd.h:3131
FSP_S_TEST_CONFIG::ProcessorTraceMemBase
UINT64 ProcessorTraceMemBase
Offset 0x07F3 - Base of memory region allocated for Processor Trace Base address of memory region all...
Definition: FspsUpd.h:2699
FSP_S_CONFIG::PchHdaVerbTableEntryNum
UINT8 PchHdaVerbTableEntryNum
Offset 0x008C - PCH HDA Verb Table Entry Number Number of Entries in Verb Table.
Definition: FspsUpd.h:253
FSP_S_CONFIG::SataP0T2M
UINT8 SataP0T2M
Offset 0x071F - Port 0 T2 Multipler Port 0 T2 Multipler.
Definition: FspsUpd.h:2104
FSP_S_TEST_CONFIG::PchSbAccessUnlock
UINT8 PchSbAccessUnlock
Offset 0x08C3 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e...
Definition: FspsUpd.h:3181
FSP_S_TEST_CONFIG::MaxRingRatioLimit
UINT8 MaxRingRatioLimit
Offset 0x08A4 - Minimum Ring ratio limit override Maximum Ring ratio limit override.
Definition: FspsUpd.h:3108
FSP_S_TEST_CONFIG::Eist
UINT8 Eist
Offset 0x0800 - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Techno...
Definition: FspsUpd.h:2717
FSP_S_CONFIG::SataP0Tinact
UINT8 SataP0Tinact
Offset 0x0726 - Port 0 Tinactive Port 0 Tinactive.
Definition: FspsUpd.h:2139
FSP_S_CONFIG::PchPmDisableNativePowerButton
UINT8 PchPmDisableNativePowerButton
Offset 0x0686 - PCH Pm Disable Native Power Button Power button native mode disable.
Definition: FspsUpd.h:1731
FSP_S_CONFIG::SataRstIrrtOnly
UINT8 SataRstIrrtOnly
Offset 0x06EA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports...
Definition: FspsUpd.h:1893
FSP_S_TEST_CONFIG::TccOffsetTimeWindowForRatl
UINT32 TccOffsetTimeWindowForRatl
Offset 0x0874 - Tcc Offset Time Window for RATL Package PL4 power limit.
Definition: FspsUpd.h:2976
FSP_S_TEST_CONFIG::PsysPmax
UINT16 PsysPmax
Offset 0x0856 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax.
Definition: FspsUpd.h:2916
FSP_S_CONFIG::PchHdaAudioLinkSsp1
UINT8 PchHdaAudioLinkSsp1
Offset 0x0101 - Enable HD Audio SSP1 Link Enable/disable HD Audio SSP1/I2S link.
Definition: FspsUpd.h:359
FSP_S_TEST_CONFIG::ProcHotResponse
UINT8 ProcHotResponse
Offset 0x0806 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; ...
Definition: FspsUpd.h:2755
FSP_S_CONFIG::PchPmPmeB0S5Dis
UINT8 PchPmPmeB0S5Dis
Offset 0x0669 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed ...
Definition: FspsUpd.h:1582
SI_PCH_DEVICE_INTERRUPT_CONFIG::Function
UINT8 Function
Device function.
Definition: FspsUpd.h:76
FSP_S_CONFIG::PcieRpImrSelection
UINT8 PcieRpImrSelection
Offset 0x066E - PCIE IMR port number Selects PCIE root port number for IMR feature.
Definition: FspsUpd.h:1598
FSP_S_CONFIG::SataRstLedLocate
UINT8 SataRstLedLocate
Offset 0x06E9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to...
Definition: FspsUpd.h:1887
FSP_S_CONFIG::DdiPortEdp
UINT8 DdiPortEdp
Offset 0x0228 - Enable or disable eDP device 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:766
AZALIA_HEADER::Reserved
UINT32 Reserved
Reserved for future use. Must be set to 0.
Definition: FspsUpd.h:50
FSP_S_CONFIG::PchEnableDbcObs
UINT8 PchEnableDbcObs
Offset 0x067C - USB Overcurrent Override for DbC This option overrides USB Over Current enablement st...
Definition: FspsUpd.h:1687
FSP_S_TEST_CONFIG::PowerLimit2Power
UINT32 PowerLimit2Power
Offset 0x0868 - Package Short duration turbo mode power limit Package Short duration turbo mode power...
Definition: FspsUpd.h:2958
FSP_S_CONFIG::PchIshUart1GpioAssign
UINT8 PchIshUart1GpioAssign
Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1278
FSP_S_TEST_CONFIG::C3StateUnDemotion
UINT8 C3StateUnDemotion
Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion Enable or Disable C3 Cstate UnDemotion...
Definition: FspsUpd.h:3120
FSP_S_CONFIG::SataP0T1M
UINT8 SataP0T1M
Offset 0x071E - Port 0 T1 Multipler Port 0 T1 Multipler.
Definition: FspsUpd.h:2099
FSP_S_CONFIG::PchIshGp4GpioAssign
UINT8 PchIshGp4GpioAssign
Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1326
FSP_S_CONFIG::PchIshSpiGpioAssign
UINT8 PchIshSpiGpioAssign
Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1266
FSP_S_CONFIG::PreWake
UINT8 PreWake
Offset 0x0328 - Pre Wake Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range...
Definition: FspsUpd.h:1119
AZALIA_HEADER::DeviceId
UINT16 DeviceId
Codec Device ID.
Definition: FspsUpd.h:46
FSP_S_TEST_CONFIG::EnableItbmDriver
UINT8 EnableItbmDriver
Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver Intel Turbo Boost Max Technology 3...
Definition: FspsUpd.h:3077
FSP_S_TEST_CONFIG::PowerLimit3
UINT32 PowerLimit3
Offset 0x086C - Package PL3 power limit Package PL3 power limit.
Definition: FspsUpd.h:2964
FSP_S_CONFIG::TetonGlacierCR
UINT8 TetonGlacierCR
Offset 0x0668 - Teton Glacier Cycle Router Specify to which cycle router Teton Glacier is connected...
Definition: FspsUpd.h:1576
FSP_S_TEST_CONFIG::DisableVrThermalAlert
UINT8 DisableVrThermalAlert
Offset 0x0807 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1:...
Definition: FspsUpd.h:2761
FSP_S_TEST_CONFIG::CpuWakeUpTimer
UINT8 CpuWakeUpTimer
Offset 0x08A2 - CpuWakeUpTimer Enable long CPU Wakeup Timer.
Definition: FspsUpd.h:3096
FSP_S_CONFIG::GpioIrqRoute
UINT8 GpioIrqRoute
Offset 0x0088 - Select GPIO IRQ Route GPIO IRQ Select.
Definition: FspsUpd.h:232
FSP_S_CONFIG::DmiTS2TW
UINT8 DmiTS2TW
Offset 0x071C - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width.
Definition: FspsUpd.h:2088
FSP_S_TEST_CONFIG::PcieEnablePort8xhDecode
UINT8 PcieEnablePort8xhDecode
Offset 0x0A5C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh D...
Definition: FspsUpd.h:3248
FSP_S_CONFIG::PchHdaCodecSxWakeCapability
UINT8 PchHdaCodecSxWakeCapability
Offset 0x0091 - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx...
Definition: FspsUpd.h:263
FSP_S_CONFIG::PchPmSlpSusMinAssert
UINT8 PchPmSlpSusMinAssert
Offset 0x0678 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. ...
Definition: FspsUpd.h:1654
FSP_S_CONFIG::PchEspiBmeMasterSlaveEnabled
UINT8 PchEspiBmeMasterSlaveEnabled
Offset 0x0119 - PCH eSPI Master and Slave BME enabled PCH eSPI Master and Slave BME enabled $EN_DIS...
Definition: FspsUpd.h:432
FSP_S_TEST_CONFIG::PkgCStateDemotion
UINT8 PkgCStateDemotion
Offset 0x080D - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion...
Definition: FspsUpd.h:2797
FSP_S_CONFIG::PmcDbgMsgEn
UINT8 PmcDbgMsgEn
Offset 0x011F - PMC Debug Message Enable When Enabled, PMC HW will send debug messages to trace hub; ...
Definition: FspsUpd.h:452
FSP_S_CONFIG::GnaEnable
UINT8 GnaEnable
Offset 0x021A - Enable or disable GNA device 0=Disable, 1(Default)=Enable $EN_DIS.
Definition: FspsUpd.h:749
FSP_S_TEST_CONFIG::C3StateAutoDemotion
UINT8 C3StateAutoDemotion
Offset 0x08A5 - Enable or Disable C3 Cstate Demotion Enable or Disable C3 Cstate Demotion.
Definition: FspsUpd.h:3114
FSP_S_TEST_CONFIG::Custom2PowerLimit1
UINT32 Custom2PowerLimit1
Offset 0x0880 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for...
Definition: FspsUpd.h:2994
FSP_S_CONFIG::SerialIoDebugUartNumber
UINT8 SerialIoDebugUartNumber
Offset 0x0706 - UART Number For Debug Purpose UART number for debug purpose.
Definition: FspsUpd.h:1976
FSP_S_TEST_CONFIG::PchSbiUnlock
UINT8 PchSbiUnlock
Offset 0x08C2 - PCH Unlock SBI access Deprecated $EN_DIS.
Definition: FspsUpd.h:3174
FSP_S_CONFIG::PchPmPwrBtnOverridePeriod
UINT8 PchPmPwrBtnOverridePeriod
Offset 0x0683 - PCH Pm Pwr Btn Override Period PCH power button override period.
Definition: FspsUpd.h:1715
FSP_S_TEST_CONFIG::PowerLimit1
UINT32 PowerLimit1
Offset 0x0864 - Package Long duration turbo mode power limit Package Long duration turbo mode power l...
Definition: FspsUpd.h:2952
FSP_S_CONFIG::PchPmSlpS0Enable
UINT8 PchPmSlpS0Enable
Offset 0x0687 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idl...
Definition: FspsUpd.h:1737
FSP_S_CONFIG::Enable8254ClockGating
UINT8 Enable8254ClockGating
Offset 0x074F - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support...
Definition: FspsUpd.h:2213
FSP_S_CONFIG::PcieComplianceTestMode
UINT8 PcieComplianceTestMode
Offset 0x0665 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance...
Definition: FspsUpd.h:1557
FSP_S_CONFIG::X2ApicOptOut
UINT8 X2ApicOptOut
Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS...
Definition: FspsUpd.h:755
FSP_S_CONFIG::SataP1TDisp
UINT8 SataP1TDisp
Offset 0x0725 - Port 1 Tdispatch Port 1 Tdispatch.
Definition: FspsUpd.h:2134
FSP_S_TEST_CONFIG::ChapDeviceEnable
UINT8 ChapDeviceEnable
Offset 0x07B1 - Enable/Disable Device 7 Enable: Device 7 enabled, Disable (Default): Device 7 disable...
Definition: FspsUpd.h:2368
FSP_S_CONFIG::SataP1Tinact
UINT8 SataP1Tinact
Offset 0x0728 - Port 1 Tinactive Port 1 Tinactive.
Definition: FspsUpd.h:2150
SI_PCH_DEVICE_INTERRUPT_CONFIG::IntX
UINT8 IntX
Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
Definition: FspsUpd.h:77
FSP_S_TEST_CONFIG::EndOfPostMessage
UINT8 EndOfPostMessage
Offset 0x08BB - End of Post message Test, Send End of Post message.
Definition: FspsUpd.h:3138
FSP_S_CONFIG::PchHdaAudioLinkSsp2
UINT8 PchHdaAudioLinkSsp2
Offset 0x0102 - Enable HD Audio SSP2 Link Enable/disable HD Audio SSP2/I2S link.
Definition: FspsUpd.h:365
FSP_S_CONFIG::PcieDisableRootPortClockGating
UINT8 PcieDisableRootPortClockGating
Offset 0x0662 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for...
Definition: FspsUpd.h:1541
FSP_S_CONFIG::PchT1Level
UINT16 PchT1Level
Offset 0x070F - Thermal Throttling Custimized T1Level Value Custimized T1Level value.
Definition: FspsUpd.h:2022
SI_PCH_INT_PIN
SI_PCH_INT_PIN
Refer to the definition of PCH_INT_PIN.
Definition: FspsUpd.h:64
SI_PCH_DEVICE_INTERRUPT_CONFIG::Device
UINT8 Device
Device number.
Definition: FspsUpd.h:75
SI_PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device...
Definition: FspsUpd.h:74
FSP_S_CONFIG::PchPmSlpAMinAssert
UINT8 PchPmSlpAMinAssert
Offset 0x0679 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy.
Definition: FspsUpd.h:1659
FSP_S_TEST_CONFIG::DebugInterfaceEnable
UINT8 DebugInterfaceEnable
Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features. ...
Definition: FspsUpd.h:2669
FSP_S_CONFIG
Fsp S Configuration.
Definition: FspsUpd.h:86
FSP_S_TEST_CONFIG::MctpBroadcastCycle
UINT8 MctpBroadcastCycle
Offset 0x0A73 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enab...
Definition: FspsUpd.h:3288
FSP_S_CONFIG::VrPowerDeliveryDesign
UINT32 VrPowerDeliveryDesign
Offset 0x0324 - CPU VR Power Delivery Design Used to communicate the power delivery design capability...
Definition: FspsUpd.h:1112
FSP_S_CONFIG::FastPkgCRampDisableIa
UINT8 FastPkgCRampDisableIa
Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew R...
Definition: FspsUpd.h:932
FSP_S_CONFIG::AmtEnabled
UINT8 AmtEnabled
Offset 0x0155 - AMT Switch Enable/Disable.
Definition: FspsUpd.h:571
FSP_S_TEST_CONFIG::SkipPamLock
UINT8 SkipPamLock
Offset 0x07B2 - Skip PAM register lock Enable: PAM register will not be locked by RC...
Definition: FspsUpd.h:2375
FSP_S_TEST_CONFIG::VtdDisable
UINT8 VtdDisable
Offset 0x07BD - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS...
Definition: FspsUpd.h:2425
FSPS_UPD::FspsTestConfig
FSP_S_TEST_CONFIG FspsTestConfig
Offset 0x07AD.
Definition: FspsUpd.h:3309
FSP_S_CONFIG::SataRstOptaneMemory
UINT8 SataRstOptaneMemory
Offset 0x0750 - PCH Sata Rst Optane Memory Optane Memory $EN_DIS.
Definition: FspsUpd.h:2219
FSP_S_CONFIG::PchHdaAudioLinkSndw4
UINT8 PchHdaAudioLinkSndw4
Offset 0x0106 - Enable HD Audio SoundWire#4 Link Enable/disable HD Audio SNDW4 link.
Definition: FspsUpd.h:389
FSP_S_CONFIG::FivrSpreadSpectrum
UINT8 FivrSpreadSpectrum
Offset 0x0312 - FIVR RFI Spread Spectrum PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments.
Definition: FspsUpd.h:1074
FSP_S_CONFIG::PchStartFramePulse
UINT8 PchStartFramePulse
Offset 0x070A - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk...
Definition: FspsUpd.h:2000
FSP_S_TEST_CONFIG::RenderStandby
UINT8 RenderStandby
Offset 0x07BA - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS.
Definition: FspsUpd.h:2407
FSP_S_CONFIG::PcieRpFunctionSwap
UINT8 PcieRpFunctionSwap
Offset 0x0666 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root...
Definition: FspsUpd.h:1564
FSP_S_CONFIG::PcieEnablePeerMemoryWrite
UINT8 PcieEnablePeerMemoryWrite
Offset 0x0663 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are en...
Definition: FspsUpd.h:1547
FSP_S_CONFIG::ScsUfsEnabled
UINT8 ScsUfsEnabled
Offset 0x0145 - Enable Ufs Controller Enable/disable Ufs 2.0 Controller.
Definition: FspsUpd.h:474
FSP_S_TEST_CONFIG::Custom3PowerLimit1
UINT32 Custom3PowerLimit1
Offset 0x0888 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for...
Definition: FspsUpd.h:3006
FSP_S_CONFIG::SataRstIrrt
UINT8 SataRstIrrt
Offset 0x06E5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology.
Definition: FspsUpd.h:1863
FSP_S_CONFIG::PchIshI2c1GpioAssign
UINT8 PchIshI2c1GpioAssign
Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable.
Definition: FspsUpd.h:1290
FSP_S_TEST_CONFIG::TccActivationOffset
UINT8 TccActivationOffset
Offset 0x07D8 - TCC Activation Offset TCC Activation Offset.
Definition: FspsUpd.h:2539
FSP_S_TEST_CONFIG::Custom3ConfigTdpControl
UINT8 Custom3ConfigTdpControl
Offset 0x07E4 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1...
Definition: FspsUpd.h:2608
FSP_S_CONFIG::PchTemperatureHotLevel
UINT16 PchTemperatureHotLevel
Offset 0x0732 - Thermal Device Temperature Decides the temperature.
Definition: FspsUpd.h:2188
FSP_S_CONFIG::SlowSlewRateForSa
UINT8 SlowSlewRateForSa
Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configur...
Definition: FspsUpd.h:953
FSP_S_TEST_CONFIG::CstateLatencyControl0Irtl
UINT16 CstateLatencyControl0Irtl
Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0 Interrupt Response Time Limit...
Definition: FspsUpd.h:2921
FSP_S_TEST_CONFIG::DisableProcHotOut
UINT8 DisableProcHotOut
Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# ...
Definition: FspsUpd.h:2749
FSP_S_CONFIG::PchPmMeWakeSts
UINT8 PchPmMeWakeSts
Offset 0x0688 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) re...
Definition: FspsUpd.h:1743
FSP_S_CONFIG::UnusedUpdSpace21
UINT8 UnusedUpdSpace21
Offset 0x0700.
Definition: FspsUpd.h:1954
FSP_S_TEST_CONFIG::MlcStreamerPrefetcher
UINT8 MlcStreamerPrefetcher
Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; ...
Definition: FspsUpd.h:2645
FSP_S_CONFIG::Enable8254ClockGatingOnS3
UINT8 Enable8254ClockGatingOnS3
Offset 0x0752 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGat...
Definition: FspsUpd.h:2233
FSP_S_CONFIG::SataP0TDisp
UINT8 SataP0TDisp
Offset 0x0721 - Port 0 Tdispatch Port 0 Tdispatch.
Definition: FspsUpd.h:2114
FSP_S_CONFIG::PcieRpPtmMask
UINT32 PcieRpPtmMask
Offset 0x0108 - PTM for PCIE RP Mask Enable/disable Precision Time Measurement for PCIE Root Ports...
Definition: FspsUpd.h:401
FSP_S_CONFIG::ScsEmmcHs400Enabled
UINT8 ScsEmmcHs400Enabled
Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode.
Definition: FspsUpd.h:129
FSP_S_TEST_CONFIG::ThreeStrikeCounterDisable
UINT8 ThreeStrikeCounterDisable
Offset 0x0898 - Set Three Strike Counter Disable False (default): Three Strike counter will be increm...
Definition: FspsUpd.h:3031
FSP_S_TEST_CONFIG::CstateLatencyControl0TimeUnit
UINT8 CstateLatencyControl0TimeUnit
Offset 0x0813 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid va...
Definition: FspsUpd.h:2834
FSP_S_CONFIG::ScsEmmcEnabled
UINT8 ScsEmmcEnabled
Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller.
Definition: FspsUpd.h:123
FSP_S_CONFIG::PchPmSlpS0VmRuntimeControl
UINT8 PchPmSlpS0VmRuntimeControl
Offset 0x0152 - SLP_S0 VM Dynamic Control SLP_S0 Voltage Margining Runtime Control Policy...
Definition: FspsUpd.h:553
Generated on Wed Aug 22 2018 17:48:55 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by   doxygen 1.8.10
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