CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: MemInfoHob.h Source File

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CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide
MemInfoHob.h
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1 /** @file
2  This file contains definitions required for creation of
3  Memory S3 Save data, Memory Info data and Memory Platform
4  data hobs.
5 
6  @copyright
7  Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.<BR>
8  This program and the accompanying materials are licensed and made available under
9  the terms and conditions of the BSD License that accompanies this distribution.
10  The full text of the license may be found at
11  http://opensource.org/licenses/bsd-license.php.
12  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 
14  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 
16 @par Specification Reference:
17 **/
18 #ifndef _MEM_INFO_HOB_H_
19 #define _MEM_INFO_HOB_H_
20 
21 #include <Uefi/UefiMultiPhase.h>
22 #include <Pi/PiBootMode.h>
23 #include <Pi/PiHob.h>
24 
25 #pragma pack (push, 1)
26 
27 extern EFI_GUID gSiMemoryS3DataGuid;
28 extern EFI_GUID gSiMemoryInfoDataGuid;
29 extern EFI_GUID gSiMemoryPlatformDataGuid;
30 
31 #define MAX_NODE 1
32 #define MAX_CH 2
33 #define MAX_DIMM 2
34 
35 ///
36 /// Host reset states from MRC.
37 ///
38 #define WARM_BOOT 2
39 
40 #define R_MC_CHNL_RANK_PRESENT 0x7C
41 #define B_RANK0_PRS BIT0
42 #define B_RANK1_PRS BIT1
43 #define B_RANK2_PRS BIT4
44 #define B_RANK3_PRS BIT5
45 
46 ///
47 /// Defines taken from MRC so avoid having to include MrcInterface.h
48 ///
49 
50 //
51 // Matches MAX_SPD_SAVE define in MRC
52 //
53 #ifndef MAX_SPD_SAVE
54 #define MAX_SPD_SAVE 29
55 #endif
56 
57 //
58 // MRC version description.
59 //
60 typedef struct {
61  UINT8 Major; ///< Major version number
62  UINT8 Minor; ///< Minor version number
63  UINT8 Rev; ///< Revision number
64  UINT8 Build; ///< Build number
65 } SiMrcVersion;
66 
67 //
68 // Matches MrcChannelSts enum in MRC
69 //
70 #ifndef CHANNEL_NOT_PRESENT
71 #define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
72 #endif
73 #ifndef CHANNEL_DISABLED
74 #define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
75 #endif
76 #ifndef CHANNEL_PRESENT
77 #define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
78 #endif
79 
80 //
81 // Matches MrcDimmSts enum in MRC
82 //
83 #ifndef DIMM_ENABLED
84 #define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
85 #endif
86 #ifndef DIMM_DISABLED
87 #define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
88 #endif
89 #ifndef DIMM_PRESENT
90 #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
91 #endif
92 #ifndef DIMM_NOT_PRESENT
93 #define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
94 #endif
95 
96 //
97 // Matches MrcBootMode enum in MRC
98 //
99 #ifndef bmCold
100 #define bmCold 0 // Cold boot
101 #endif
102 #ifndef bmWarm
103 #define bmWarm 1 // Warm boot
104 #endif
105 #ifndef bmS3
106 #define bmS3 2 // S3 resume
107 #endif
108 #ifndef bmFast
109 #define bmFast 3 // Fast boot
110 #endif
111 
112 //
113 // Matches MrcDdrType enum in MRC
114 //
115 #ifndef MRC_DDR_TYPE_DDR4
116 #define MRC_DDR_TYPE_DDR4 0
117 #endif
118 #ifndef MRC_DDR_TYPE_DDR3
119 #define MRC_DDR_TYPE_DDR3 1
120 #endif
121 #ifndef MRC_DDR_TYPE_LPDDR3
122 #define MRC_DDR_TYPE_LPDDR3 2
123 #endif
124 #ifndef CPU_CFL//CNL
125 #ifndef MRC_DDR_TYPE_LPDDR4
126 #define MRC_DDR_TYPE_LPDDR4 3
127 #endif
128 #else//CFL
129 #ifndef MRC_DDR_TYPE_UNKNOWN
130 #define MRC_DDR_TYPE_UNKNOWN 3
131 #endif
132 #endif//CPU_CFL-endif
133 
134 #define MAX_PROFILE_NUM 4 // number of memory profiles supported
135 #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
136 
137 //
138 // DIMM timings
139 //
140 typedef struct {
141  UINT32 tCK; ///< Memory cycle time, in femtoseconds.
142  UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
143  UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
144  UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
145  UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
146  UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
147  UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
148  UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
149  UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
150  UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
151  UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
152  UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
153  UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
154  UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
155  UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
156  UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
157  UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
158  UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
159  UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
160  UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
161  UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
162  UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
163 } MRC_CH_TIMING;
164 
165 typedef struct {
166  UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
167  UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
168  UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
169  UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
170 } MRC_TA_TIMING;
171 
172 ///
173 /// Memory SMBIOS & OC Memory Data Hob
174 ///
175 typedef struct {
176  UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
177  UINT8 DimmId;
178  UINT32 DimmCapacity; ///< DIMM size in MBytes.
179  UINT16 MfgId;
180  UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
181  UINT8 RankInDimm; ///< The number of ranks in this DIMM.
182  UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
183  UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
184  UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
185  UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
186  UINT16 Speed; ///< The maximum capable speed of the device, in MHz.
187 } DIMM_INFO;
188 
189 typedef struct {
190  UINT8 Status; ///< Indicates whether this channel should be used.
191  UINT8 ChannelId;
192  UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
193  MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
194  DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
195  MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
196  MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
197  MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
198  MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
199 } CHANNEL_INFO;
200 
201 typedef struct {
202  UINT8 Status; ///< Indicates whether this controller should be used.
203  UINT16 DeviceId; ///< The PCI device id of this memory controller.
204  UINT8 RevisionId; ///< The PCI revision id of this memory controller.
205  UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
206  CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
207  MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings
208  MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings
209  MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings
210  MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings
211 } CONTROLLER_INFO;
212 
213 typedef struct {
214  UINT8 Revision;
215  UINT16 DataWidth; ///< Data width, in bits, of this memory device
216  /** As defined in SMBIOS 3.0 spec
217  Section 7.18.2 and Table 75
218  **/
219  UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
220  UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
221  UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
222  /** As defined in SMBIOS 3.0 spec
223  Section 7.17.3 and Table 72
224  **/
225  UINT8 ErrorCorrectionType;
226 
227  SiMrcVersion Version;
228  BOOLEAN EccSupport;
229  UINT8 MemoryProfile;
230  UINT32 TotalPhysicalMemorySize;
231  UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
232  UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
233  UINT8 Ratio;
234  UINT8 RefClk;
235  UINT32 VddVoltage[MAX_PROFILE_NUM];
236  CONTROLLER_INFO Controller[MAX_NODE];
237 } MEMORY_INFO_DATA_HOB;
238 
239 /**
240  Memory Platform Data Hob
241 
242  <b>Revision 1:</b>
243  - Initial version.
244  <b>Revision 2:</b>
245  - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
246 **/
247 typedef struct {
248  UINT8 Revision;
249  UINT8 Reserved[3];
250  UINT32 BootMode;
251  UINT32 TsegSize;
252  UINT32 TsegBase;
253  UINT32 PrmrrSize;
254  UINT32 PrmrrBase;
255  UINT32 GttBase;
256  UINT32 MmioSize;
257  UINT32 PciEBaseAddress;
258 #ifdef CPU_CFL
259  UINT32 GdxcIotBase;
260  UINT32 GdxcIotSize;
261  UINT32 GdxcMotBase;
262  UINT32 GdxcMotSize;
263 #endif //CPU_CFL
264 } MEMORY_PLATFORM_DATA;
265 
266 typedef struct {
267  EFI_HOB_GUID_TYPE EfiHobGuidType;
268  MEMORY_PLATFORM_DATA Data;
269  UINT8 *Buffer;
270 } MEMORY_PLATFORM_DATA_HOB;
271 
272 #pragma pack (pop)
273 
274 #endif // _MEM_INFO_HOB_H_
DIMM_INFO::Status
UINT8 Status
See MrcDimmStatus for the definition of this field.
Definition: MemInfoHob.h:176
DIMM_INFO::SpdDramDeviceType
UINT8 SpdDramDeviceType
Save SPD DramDeviceType information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:182
DIMM_INFO::SpdModuleMemoryBusWidth
UINT8 SpdModuleMemoryBusWidth
Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:184
DIMM_INFO::DimmCapacity
UINT32 DimmCapacity
DIMM size in MBytes.
Definition: MemInfoHob.h:178
DIMM_INFO
Memory SMBIOS & OC Memory Data Hob.
Definition: MemInfoHob.h:175
MEMORY_PLATFORM_DATA
Memory Platform Data Hob.
Definition: MemInfoHob.h:247
DIMM_INFO::SpdModuleType
UINT8 SpdModuleType
Save SPD ModuleType information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:183
MAX_SPD_SAVE
#define MAX_SPD_SAVE
Defines taken from MRC so avoid having to include MrcInterface.h.
Definition: MemInfoHob.h:54
DIMM_INFO::Speed
UINT16 Speed
The maximum capable speed of the device, in MHz.
Definition: MemInfoHob.h:186
DIMM_INFO::RankInDimm
UINT8 RankInDimm
The number of ranks in this DIMM.
Definition: MemInfoHob.h:181
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