Memory Latency
This benchmark measures the typical delay when the CPU reads data from system memory. Memory latency time means the penalty measured from the issuing of the read command until the data arrives to the integer registers of the CPU. The code behind this benchmark method is written in Assembly, and uses at least 16 MB memory size with 4 KB page size.
[*NEW*] Since AIDA64 v3.00, memory is accessed in a random pattern, with at least 128-byte stride to avoid the effect of the adjacent cacheline prefetcher; and smaller stride than the TLB-window to minimize the effect of TLB miss penalty.
Memory Latency benchmark test uses only the basic x86 instructions and utilizes only one processor core and one thread.