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STM8L15x Standard Peripherals Drivers
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stm8l15x_tim5.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_tim5.c 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file provides firmware functions to manage the following 00008 * functionalities of the TIM5 peripheral: 00009 * - TimeBase management 00010 * - Output Compare management 00011 * - Input Capture management 00012 * - Interrupts, DMA and flags management 00013 * - Clocks management 00014 * - Synchronization management 00015 * - Specific interface management 00016 * 00017 * @verbatim 00018 * 00019 * =================================================================== 00020 * How to use this driver 00021 * =================================================================== 00022 * This driver provides functions to configure and initialise the TIM5 00023 * peripheral 00024 * These functions are split in 7 groups: 00025 * 00026 * 1. TIM5 TimeBase management: this group includes all needed functions 00027 * to configure the TIM Timebase unit: 00028 * - Set/Get Prescaler 00029 * - Set/Get Autoreload 00030 * - Counter modes configuration 00031 * - Select the One Pulse mode 00032 * - Update Request Configuration 00033 * - Update Disable Configuration 00034 * - Auto-Preload Configuration 00035 * - Enable/Disable the counter 00036 * 00037 * 2. TIM5 Output Compare management: this group includes all needed 00038 * functions to configure the Capture/Compare unit used in Output 00039 * compare mode: 00040 * - Configure each channel, independently, in Output Compare mode 00041 * - Select the output compare modes 00042 * - Select the Polarities of each channel 00043 * - Set/Get the Capture/Compare register values 00044 * - Select the Output Compare Fast mode 00045 * - Select the Output Compare Forced mode 00046 * - Output Compare-Preload Configuration 00047 * - Enable/Disable the Capture/Compare Channels 00048 * 00049 * 3. TIM5 Input Capture management: this group includes all needed 00050 * functions to configure the Capture/Compare unit used in 00051 * Input Capture mode: 00052 * - Configure each channel in input capture mode 00053 * - Configure Channel1/2 in PWM Input mode 00054 * - Set the Input Capture Prescaler 00055 * - Get the Capture/Compare values 00056 * 00057 * 4. TIM5 interrupts, DMA and flags management 00058 * - Enable/Disable interrupt sources 00059 * - Get flags status 00060 * - Clear flags/ Pending bits 00061 * - Enable/Disable DMA requests 00062 * - Select CaptureCompare DMA request 00063 * 00064 * 5. TIM5 clocks management: this group includes all needed functions 00065 * to configure the clock controller unit: 00066 * - Select internal/External clock 00067 * - Select the external clock mode: ETR(Mode1/Mode2) or TIx 00068 * 00069 * 6. TIM5 synchronization management: this group includes all needed 00070 * functions to configure the Synchronization unit: 00071 * - Select Input Trigger 00072 * - Select Output Trigger 00073 * - Select Master Slave Mode 00074 * - ETR Configuration when used as external trigger 00075 * 00076 * 7. TIM5 specific interface management, this group includes all 00077 * needed functions to use the specific TIM5 interface: 00078 * - Encoder Interface Configuration 00079 * - Select Hall Sensor 00080 * 00081 * @endverbatim 00082 * 00083 ****************************************************************************** 00084 * @attention 00085 * 00086 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00087 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00088 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00089 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00090 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00091 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00092 * 00093 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00094 ****************************************************************************** 00095 */ 00096 00097 /* Includes ------------------------------------------------------------------*/ 00098 #include "stm8l15x_TIM5.h" 00099 00100 /** @addtogroup STM8L15x_StdPeriph_Driver 00101 * @{ 00102 */ 00103 00104 /** @defgroup TIM5 00105 * @brief TIM5 driver modules 00106 * @{ 00107 */ 00108 00109 /* Private typedef -----------------------------------------------------------*/ 00110 /* Private define ------------------------------------------------------------*/ 00111 /* Private macro -------------------------------------------------------------*/ 00112 /* Private variables ---------------------------------------------------------*/ 00113 /* Private function prototypes -----------------------------------------------*/ 00114 static void TI1_Config(TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 00115 TIM5_ICSelection_TypeDef TIM5_ICSelection, 00116 uint8_t TIM5_ICFilter); 00117 static void TI2_Config(TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 00118 TIM5_ICSelection_TypeDef TIM5_ICSelection, 00119 uint8_t TIM5_ICFilter); 00120 00121 00122 /** @defgroup TIM5_Private_Functions 00123 * @{ 00124 */ 00125 00126 /** @defgroup TIM5_Group1 TimeBase management functions 00127 * @brief TimeBase management functions 00128 * 00129 @verbatim 00130 =============================================================================== 00131 TimeBase management functions 00132 =============================================================================== 00133 00134 =================================================================== 00135 TIM5 Driver: how to use it in Timing(Time base) Mode 00136 =================================================================== 00137 To use the Timer in Timing(Time base) mode, the following steps are mandatory: 00138 00139 1. Enable TIM5 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM5, ENABLE) function. 00140 00141 2. Call TIM5_TimeBaseInit() to configure the Time Base unit with the 00142 corresponding configuration. 00143 00144 3. Enable global interrupts if you need to generate the update interrupt. 00145 00146 4. Enable the corresponding interrupt using the function TIM5_ITConfig(TIM5_IT_Update) 00147 00148 5. Call the TIM5_Cmd(ENABLE) function to enable the TIM5 counter. 00149 00150 Note1: All other functions can be used separately to modify, if needed, 00151 a specific feature of the Timer. 00152 00153 @endverbatim 00154 * @{ 00155 */ 00156 00157 /** 00158 * @brief Deinitialize the TIM5 peripheral registers to their default reset values. 00159 * @param None 00160 * @retval None 00161 */ 00162 void TIM5_DeInit(void) 00163 { 00164 TIM5->CR1 = TIM_CR1_RESET_VALUE; 00165 TIM5->CR2 = TIM_CR2_RESET_VALUE; 00166 TIM5->SMCR = TIM_SMCR_RESET_VALUE; 00167 TIM5->ETR = TIM_ETR_RESET_VALUE; 00168 TIM5->IER = TIM_IER_RESET_VALUE; 00169 TIM5->SR2 = TIM_SR2_RESET_VALUE; 00170 00171 /* Disable channels */ 00172 TIM5->CCER1 = TIM_CCER1_RESET_VALUE; 00173 /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */ 00174 TIM5->CCMR1 = 0x01;/*TIM5_ICxSource_TIxFPx */ 00175 TIM5->CCMR2 = 0x01;/*TIM5_ICxSource_TIxFPx */ 00176 00177 /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */ 00178 TIM5->CCER1 = TIM_CCER1_RESET_VALUE; 00179 TIM5->CCMR1 = TIM_CCMR1_RESET_VALUE; 00180 TIM5->CCMR2 = TIM_CCMR2_RESET_VALUE; 00181 00182 TIM5->CNTRH = TIM_CNTRH_RESET_VALUE; 00183 TIM5->CNTRL = TIM_CNTRL_RESET_VALUE; 00184 00185 TIM5->PSCR = TIM_PSCR_RESET_VALUE; 00186 00187 TIM5->ARRH = TIM_ARRH_RESET_VALUE; 00188 TIM5->ARRL = TIM_ARRL_RESET_VALUE; 00189 00190 TIM5->CCR1H = TIM_CCR1H_RESET_VALUE; 00191 TIM5->CCR1L = TIM_CCR1L_RESET_VALUE; 00192 TIM5->CCR2H = TIM_CCR2H_RESET_VALUE; 00193 TIM5->CCR2L = TIM_CCR2L_RESET_VALUE; 00194 00195 00196 TIM5->OISR = TIM_OISR_RESET_VALUE; 00197 TIM5->EGR = 0x01;/* TIM_EGR_UG */ 00198 TIM5->BKR = TIM_BKR_RESET_VALUE; 00199 TIM5->SR1 = TIM_SR1_RESET_VALUE; 00200 } 00201 00202 /** 00203 * @brief Initializes the TIM5 Time Base Unit according to the specified parameters. 00204 * @param TIM5_Prescaler: Prescaler 00205 * This parameter can be one of the following values: 00206 * @arg TIM5_Prescaler_1: Time base Prescaler = 1 (No effect) 00207 * @arg TIM5_Prescaler_2: Time base Prescaler = 2 00208 * @arg TIM5_Prescaler_4: Time base Prescaler = 4 00209 * @arg TIM5_Prescaler_8: Time base Prescaler = 8 00210 * @arg TIM5_Prescaler_16: Time base Prescaler = 16 00211 * @arg TIM5_Prescaler_32: Time base Prescaler = 32 00212 * @arg TIM5_Prescaler_64: Time base Prescaler = 64 00213 * @arg TIM5_Prescaler_128: Time base Prescaler = 128 00214 * @param TIM5_CounterMode: Counter mode 00215 * This parameter can be one of the following values: 00216 * @arg TIM5_CounterMode_Up: Counter Up Mode 00217 * @arg TIM5_CounterMode_Down: Counter Down Mode 00218 * @arg TIM5_CounterMode_CenterAligned1: Counter Central aligned Mode 1 00219 * @arg TIM5_CounterMode_CenterAligned2: Counter Central aligned Mode 2 00220 * @arg TIM5_CounterMode_CenterAligned3: Counter Central aligned Mode 3 00221 * @param TIM5_Period: This parameter must be a value between 0x0000 and 0xFFFF. 00222 * @retval None 00223 */ 00224 00225 void TIM5_TimeBaseInit(TIM5_Prescaler_TypeDef TIM5_Prescaler, 00226 TIM5_CounterMode_TypeDef TIM5_CounterMode, 00227 uint16_t TIM5_Period) 00228 { 00229 00230 assert_param(IS_TIM5_PRESCALER(TIM5_Prescaler)); 00231 assert_param(IS_TIM5_COUNTER_MODE(TIM5_CounterMode)); 00232 00233 00234 00235 /* Set the Autoreload value */ 00236 TIM5->ARRH = (uint8_t)(TIM5_Period >> 8) ; 00237 TIM5->ARRL = (uint8_t)(TIM5_Period); 00238 00239 /* Set the Prescaler value */ 00240 TIM5->PSCR = (uint8_t)(TIM5_Prescaler); 00241 00242 /* Select the Counter Mode */ 00243 TIM5->CR1 &= (uint8_t)((uint8_t)(~TIM_CR1_CMS)) & ((uint8_t)(~TIM_CR1_DIR)); 00244 TIM5->CR1 |= (uint8_t)(TIM5_CounterMode); 00245 00246 /* Generate an update event to reload the Prescaler value immediately */ 00247 TIM5->EGR = TIM5_EventSource_Update; 00248 } 00249 00250 /** 00251 * @brief Configures the TIM5 Prescaler. 00252 * @param Prescaler: Specifies the Prescaler Register value 00253 * This parameter can be one of the following values: 00254 * @arg TIM5_Prescaler_1: Time base Prescaler = 1 (No effect) 00255 * @arg TIM5_Prescaler_2: Time base Prescaler = 2 00256 * @arg TIM5_Prescaler_4: Time base Prescaler = 4 00257 * @arg TIM5_Prescaler_8: Time base Prescaler = 8 00258 * @arg TIM5_Prescaler_16: Time base Prescaler = 16 00259 * @arg TIM5_Prescaler_32: Time base Prescaler = 32 00260 * @arg TIM5_Prescaler_64: Time base Prescaler = 64 00261 * @arg TIM5_Prescaler_128: Time base Prescaler = 128 00262 * @param TIM5_PSCReloadMode: Specifies the TIM5 Prescaler Reload mode. 00263 * This parameter can be one of the following values: 00264 * @arg TIM5_PSCReloadMode_Update: Prescaler value is reloaded at every update 00265 * @arg TIM5_PSCReloadMode_Immediate: Prescaler value is reloaded at every update 00266 * @retval None 00267 */ 00268 void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler, 00269 TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode) 00270 { 00271 /* Check the parameters */ 00272 assert_param(IS_TIM5_PRESCALER(Prescaler)); 00273 assert_param(IS_TIM5_PRESCALER_RELOAD(TIM5_PSCReloadMode)); 00274 00275 /* Set the Prescaler value */ 00276 TIM5->PSCR = (uint8_t)(Prescaler); 00277 00278 /* Set or reset the UG Bit */ 00279 if (TIM5_PSCReloadMode == TIM5_PSCReloadMode_Immediate) 00280 { 00281 TIM5->EGR |= TIM_EGR_UG ; 00282 } 00283 else 00284 { 00285 TIM5->EGR &= (uint8_t)(~TIM_EGR_UG) ; 00286 } 00287 } 00288 00289 /** 00290 * @brief Specifies the TIM5 Counter Mode to be used. 00291 * @param TIM5_CounterMode: Specifies the Counter Mode to be used 00292 * This parameter can be one of the following values: 00293 * @arg TIM5_CounterMode_Up: Counter Up Mode 00294 * @arg TIM5_CounterMode_Down: Counter Down Mode 00295 * @arg TIM5_CounterMode_CenterAligned1: Counter Central aligned Mode 1 00296 * @arg TIM5_CounterMode_CenterAligned2: Counter Central aligned Mode 2 00297 * @arg TIM5_CounterMode_CenterAligned3: Counter Central aligned Mode 3 00298 * @retval None 00299 */ 00300 void TIM5_CounterModeConfig(TIM5_CounterMode_TypeDef TIM5_CounterMode) 00301 { 00302 uint8_t tmpcr1 = 0; 00303 00304 /* Check the parameters */ 00305 assert_param(IS_TIM5_COUNTER_MODE(TIM5_CounterMode)); 00306 00307 tmpcr1 = TIM5->CR1; 00308 00309 /* Reset the CMS and DIR Bits */ 00310 tmpcr1 &= (uint8_t)((uint8_t)(~TIM_CR1_CMS) & (uint8_t)(~TIM_CR1_DIR)); 00311 00312 /* Set the Counter Mode */ 00313 tmpcr1 |= (uint8_t)TIM5_CounterMode; 00314 00315 TIM5->CR1 = tmpcr1; 00316 } 00317 00318 /** 00319 * @brief Sets the TIM5 Counter Register value. 00320 * @param Counter: Specifies the Counter register new value. 00321 * This parameter is between 0x0000 and 0xFFFF. 00322 * @retval None 00323 */ 00324 void TIM5_SetCounter(uint16_t Counter) 00325 { 00326 00327 /* Set the Counter Register value */ 00328 TIM5->CNTRH = (uint8_t)(Counter >> 8); 00329 TIM5->CNTRL = (uint8_t)(Counter); 00330 } 00331 00332 /** 00333 * @brief Sets the TIM5 Autoreload Register value. 00334 * @param Autoreload: Specifies the Autoreload register new value. 00335 * This parameter is between 0x0000 and 0xFFFF. 00336 * @retval None 00337 */ 00338 void TIM5_SetAutoreload(uint16_t Autoreload) 00339 { 00340 /* Set the Autoreload Register value */ 00341 TIM5->ARRH = (uint8_t)(Autoreload >> 8); 00342 TIM5->ARRL = (uint8_t)(Autoreload); 00343 } 00344 00345 /** 00346 * @brief Gets the TIM5 Counter value. 00347 * @param None 00348 * @retval Counter Register value. 00349 */ 00350 uint16_t TIM5_GetCounter(void) 00351 { 00352 uint16_t tmpcnt = 0; 00353 uint8_t tmpcntrl, tmpcntrh; 00354 00355 tmpcntrh = TIM5->CNTRH; 00356 tmpcntrl = TIM5->CNTRL; 00357 00358 tmpcnt = (uint16_t)(tmpcntrl); 00359 tmpcnt |= (uint16_t)((uint16_t)tmpcntrh << 8); 00360 /* Get the Counter Register value */ 00361 return ((uint16_t)tmpcnt); 00362 } 00363 00364 /** 00365 * @brief Gets the TIM5 Prescaler value. 00366 * @param None 00367 * @retval TIM5 Prescaler, it can be one of the following values: 00368 * - TIM5_Prescaler_1: Time base Prescaler = 1 (No effect) 00369 * - TIM5_Prescaler_2: Time base Prescaler = 2 00370 * - TIM5_Prescaler_4: Time base Prescaler = 4 00371 * - TIM5_Prescaler_8: Time base Prescaler = 8 00372 * - TIM5_Prescaler_16: Time base Prescaler = 16 00373 * - TIM5_Prescaler_32: Time base Prescaler = 32 00374 * - TIM5_Prescaler_64: Time base Prescaler = 64 00375 * - TIM5_Prescaler_128: Time base Prescaler = 128 00376 */ 00377 TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void) 00378 { 00379 /* Get the Prescaler Register value */ 00380 return ((TIM5_Prescaler_TypeDef)TIM5->PSCR); 00381 } 00382 00383 /** 00384 * @brief Enables or Disables the TIM5 Update event. 00385 * @param NewState: The new state of the TIM5 peripheral Preload register. 00386 * This parameter can be ENABLE or DISABLE 00387 * @retval None 00388 */ 00389 00390 void TIM5_UpdateDisableConfig(FunctionalState NewState) 00391 { 00392 /* Check the parameters */ 00393 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00394 00395 /* Set or Reset the UDIS Bit */ 00396 if (NewState != DISABLE) 00397 { 00398 TIM5->CR1 |= TIM_CR1_UDIS; 00399 } 00400 else 00401 { 00402 TIM5->CR1 &= (uint8_t)(~TIM_CR1_UDIS); 00403 } 00404 } 00405 00406 /** 00407 * @brief Selects the TIM5 Update Request Interrupt source. 00408 * @param TIM5_UpdateSource: Specifies the Update source. 00409 * This parameter can be one of the following values: 00410 * @arg TIM5_UpdateSource_Global: Global Update request source 00411 * @arg TIM5_UpdateSource_Regular: Regular Update request source 00412 * @retval None 00413 */ 00414 void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource) 00415 { 00416 /* Check the parameters */ 00417 assert_param(IS_TIM5_UPDATE_SOURCE(TIM5_UpdateSource)); 00418 00419 /* Set or Reset the URS Bit */ 00420 if (TIM5_UpdateSource == TIM5_UpdateSource_Regular) 00421 { 00422 TIM5->CR1 |= TIM_CR1_URS ; 00423 } 00424 else 00425 { 00426 TIM5->CR1 &= (uint8_t)(~TIM_CR1_URS); 00427 } 00428 } 00429 00430 /** 00431 * @brief Enables or disables TIM5 peripheral Preload register on ARR. 00432 * @param NewState: The new state of the TIM5 peripheral Preload register. 00433 * This parameter can be ENABLE or DISABLE 00434 * @retval None 00435 */ 00436 void TIM5_ARRPreloadConfig(FunctionalState NewState) 00437 { 00438 /* Check the parameters */ 00439 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00440 00441 /* Set or Reset the ARPE Bit */ 00442 if (NewState != DISABLE) 00443 { 00444 TIM5->CR1 |= TIM_CR1_ARPE; 00445 } 00446 else 00447 { 00448 TIM5->CR1 &= (uint8_t)(~TIM_CR1_ARPE); 00449 } 00450 } 00451 00452 /** 00453 * @brief Selects the TIM�s One Pulse Mode. 00454 * @param TIM5_OPMode: Specifies the OPM Mode to be used. 00455 * This parameter can be one of the following values: 00456 * @arg TIM5_OPMode_Single: Single one Pulse mode (OPM Active) 00457 * @arg TIM5_OPMode_Repetitive: Single one Pulse mode (OPM Active) 00458 * @retval None 00459 */ 00460 void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode) 00461 { 00462 /* Check the parameters */ 00463 assert_param(IS_TIM5_OPM_MODE(TIM5_OPMode)); 00464 00465 /* Set or Reset the OPM Bit */ 00466 if (TIM5_OPMode == TIM5_OPMode_Single) 00467 { 00468 TIM5->CR1 |= TIM_CR1_OPM ; 00469 } 00470 else 00471 { 00472 TIM5->CR1 &= (uint8_t)(~TIM_CR1_OPM); 00473 } 00474 } 00475 00476 /** 00477 * @brief Enables or disables the TIM5 peripheral. 00478 * @param NewState: The new state of the TIM5 peripheral. 00479 * This parameter can be ENABLE or DISABLE 00480 * @retval None 00481 */ 00482 void TIM5_Cmd(FunctionalState NewState) 00483 { 00484 /* Check the parameters */ 00485 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00486 00487 /* set or Reset the CEN Bit */ 00488 if (NewState != DISABLE) 00489 { 00490 TIM5->CR1 |= TIM_CR1_CEN; 00491 } 00492 else 00493 { 00494 TIM5->CR1 &= (uint8_t)(~TIM_CR1_CEN); 00495 } 00496 } 00497 00498 /** 00499 * @} 00500 */ 00501 00502 /** @defgroup TIM5_Group2 Output Compare management functions 00503 * @brief Output Compare management functions 00504 * 00505 @verbatim 00506 =============================================================================== 00507 Output Compare management functions 00508 =============================================================================== 00509 00510 =================================================================== 00511 TIM5 Driver: how to use it in Output Compare Mode 00512 =================================================================== 00513 To use the Timer in Output Compare mode, the following steps are mandatory: 00514 00515 1. Enable TIM5 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM5, ENABLE) function. 00516 00517 2. Configure the TIM5 pins in output mode by configuring the corresponding GPIO pins 00518 00519 3. Configure the Time base unit as described in the first part of this driver, if needed, 00520 otherwise the Timer will run with the default configuration: 00521 - Autoreload value = 0xFFFF 00522 - Prescaler value = 0x0000 00523 - Counter mode = Up counting 00524 00525 4. Call TIM5_OCxInit() to configure the channel x with the desired parameters 00526 including: 00527 - TIM5 Output Compare mode: TIM5_OCMode 00528 - TIM5 Output State: TIM5_OutputState 00529 - TIM5 Pulse value: TIM5_Pulse 00530 - TIM5 Output Compare Polarity: TIM5_OCPolarity 00531 - TIM5 Output Idle State: TIM5_OCIdleState 00532 00533 5. Call the TIM5_Cmd(ENABLE) function to enable the TIM5 counter. 00534 00535 Note1: All other functions can be used separately to modify, if needed, 00536 a specific feature of the Timer. 00537 00538 Note2: If the corresponding interrupt or DMA request are needed, the user should: 00539 1. Enable global interrupts (or the DMA) to use the TIM5 interrupts (or DMA requests). 00540 2. Enable the corresponding interrupt (or DMA request) using the function 00541 TIM5_ITConfig(TIM5_IT_CCx) (or TIM5_DMACmd(TIM5_DMASource_CCx)) 00542 00543 @endverbatim 00544 * @{ 00545 */ 00546 00547 /** 00548 * @brief Initializes the TIM5 Channel1 according to the specified parameters. 00549 * @param TIM5_OCMode: Output Compare Mode 00550 * This parameter can be one of the following values: 00551 * @arg TIM5_OCMode_Timing: Timing (Frozen) Mode 00552 * @arg TIM5_OCMode_Active: Active Mode 00553 * @arg TIM5_OCMode_Inactive: Inactive Mode 00554 * @arg TIM5_OCMode_Toggle: Toggle Mode 00555 * @arg TIM5_OCMode_PWM1: PWM Mode 1 00556 * @arg TIM5_OCMode_PWM2: PWM Mode 2 00557 * @param TIM5_OutputState: Output state 00558 * This parameter can be one of the following values: 00559 * @arg TIM5_OutputState_Disable: Output compare State disabled (channel output disabled) 00560 * @arg TIM5_OutputState_Enable: Output compare State enabled (channel output enabled) 00561 * @param TIM5_Pulse: This parameter must be a value between 0x0000 and 0xFFFF. 00562 * @param TIM5_OCPolarity: Polarity 00563 * This parameter can be one of the following values: 00564 * @arg TIM5_OCPolarity_High: Output compare polarity = High 00565 * @arg TIM5_OCPolarity_Low: Output compare polarity = Low 00566 * @param TIM5_OCIdleState: Output Compare Idle State 00567 * This parameter can be one of the following values: 00568 * @arg TIM5_OCIdleState_Reset: Output Compare Idle state = Reset 00569 * @arg TIM5_OCIdleState_Set: Output Compare Idle state = Set 00570 * @retval None 00571 */ 00572 void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode, 00573 TIM5_OutputState_TypeDef TIM5_OutputState, 00574 uint16_t TIM5_Pulse, 00575 TIM5_OCPolarity_TypeDef TIM5_OCPolarity, 00576 TIM5_OCIdleState_TypeDef TIM5_OCIdleState) 00577 { 00578 uint8_t tmpccmr1 = 0; 00579 00580 /* Check the parameters */ 00581 assert_param(IS_TIM5_OC_MODE(TIM5_OCMode)); 00582 assert_param(IS_TIM5_OUTPUT_STATE(TIM5_OutputState)); 00583 assert_param(IS_TIM5_OC_POLARITY(TIM5_OCPolarity)); 00584 assert_param(IS_TIM5_OCIDLE_STATE(TIM5_OCIdleState)); 00585 00586 tmpccmr1 = TIM5->CCMR1; 00587 00588 /* Disable the Channel 1: Reset the CCE Bit */ 00589 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E); 00590 /* Reset the Output Compare Bits */ 00591 tmpccmr1 &= (uint8_t)(~TIM_CCMR_OCM); 00592 00593 /* Set the Output Compare Mode */ 00594 tmpccmr1 |= (uint8_t)TIM5_OCMode; 00595 00596 TIM5->CCMR1 = tmpccmr1; 00597 00598 /* Set the Output State */ 00599 if (TIM5_OutputState == TIM5_OutputState_Enable) 00600 { 00601 TIM5->CCER1 |= TIM_CCER1_CC1E; 00602 } 00603 else 00604 { 00605 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E); 00606 } 00607 00608 /* Set the Output Polarity */ 00609 if (TIM5_OCPolarity == TIM5_OCPolarity_Low) 00610 { 00611 TIM5->CCER1 |= TIM_CCER1_CC1P; 00612 } 00613 else 00614 { 00615 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P); 00616 } 00617 00618 /* Set the Output Idle state */ 00619 if (TIM5_OCIdleState == TIM5_OCIdleState_Set) 00620 { 00621 TIM5->OISR |= TIM_OISR_OIS1; 00622 } 00623 else 00624 { 00625 TIM5->OISR &= (uint8_t)(~TIM_OISR_OIS1); 00626 } 00627 00628 /* Set the Pulse value */ 00629 TIM5->CCR1H = (uint8_t)(TIM5_Pulse >> 8); 00630 TIM5->CCR1L = (uint8_t)(TIM5_Pulse); 00631 } 00632 00633 /** 00634 * @brief Initializes the TIM5 Channel2 according to the specified parameters. 00635 * @param TIM5_OCMode: Output Compare Mode 00636 * This parameter can be one of the following values: 00637 * @arg TIM5_OCMode_Timing: Timing (Frozen) Mode 00638 * @arg TIM5_OCMode_Active: Active Mode 00639 * @arg TIM5_OCMode_Inactive: Inactive Mode 00640 * @arg TIM5_OCMode_Toggle: Toggle Mode 00641 * @arg TIM5_OCMode_PWM1: PWM Mode 1 00642 * @arg TIM5_OCMode_PWM2: PWM Mode 2 00643 * @param TIM5_OutputState: Output state 00644 * This parameter can be one of the following values: 00645 * @arg TIM5_OutputState_Disable: Output compare State disabled (channel output disabled) 00646 * @arg TIM5_OutputState_Enable: Output compare State enabled (channel output enabled) 00647 * @param TIM5_Pulse: This parameter must be a value between 0x0000 and 0xFFFF. 00648 * @param TIM5_OCPolarity: Polarity 00649 * This parameter can be one of the following values: 00650 * @arg TIM5_OCPolarity_High: Output compare polarity = High 00651 * @arg TIM5_OCPolarity_Low: Output compare polarity = Low 00652 * @param TIM5_OCIdleState: Output Compare Idle State 00653 * This parameter can be one of the following values: 00654 * @arg TIM5_OCIdleState_Reset: Output Compare Idle state = Reset 00655 * @arg TIM5_OCIdleState_Set: Output Compare Idle state = Set 00656 * @retval None 00657 */ 00658 void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode, 00659 TIM5_OutputState_TypeDef TIM5_OutputState, 00660 uint16_t TIM5_Pulse, 00661 TIM5_OCPolarity_TypeDef TIM5_OCPolarity, 00662 TIM5_OCIdleState_TypeDef TIM5_OCIdleState) 00663 { 00664 uint8_t tmpccmr2 = 0; 00665 00666 /* Check the parameters */ 00667 assert_param(IS_TIM5_OC_MODE(TIM5_OCMode)); 00668 assert_param(IS_TIM5_OUTPUT_STATE(TIM5_OutputState)); 00669 assert_param(IS_TIM5_OC_POLARITY(TIM5_OCPolarity)); 00670 assert_param(IS_TIM5_OCIDLE_STATE(TIM5_OCIdleState)); 00671 00672 tmpccmr2 = TIM5->CCMR2; 00673 00674 /* Disable the Channel 2: Reset the CCE Bit */ 00675 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E); 00676 00677 /* Reset the Output Compare Bits */ 00678 tmpccmr2 &= (uint8_t)(~TIM_CCMR_OCM); 00679 00680 /* Set the Output Compare Mode */ 00681 tmpccmr2 |= (uint8_t)TIM5_OCMode; 00682 00683 TIM5->CCMR2 = tmpccmr2; 00684 00685 /* Set the Output State */ 00686 if (TIM5_OutputState == TIM5_OutputState_Enable) 00687 { 00688 TIM5->CCER1 |= TIM_CCER1_CC2E; 00689 } 00690 else 00691 { 00692 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E); 00693 } 00694 00695 /* Set the Output Polarity */ 00696 if (TIM5_OCPolarity == TIM5_OCPolarity_Low) 00697 { 00698 TIM5->CCER1 |= TIM_CCER1_CC2P; 00699 } 00700 else 00701 { 00702 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P); 00703 } 00704 00705 00706 /* Set the Output Idle state */ 00707 if (TIM5_OCIdleState == TIM5_OCIdleState_Set) 00708 { 00709 TIM5->OISR |= TIM_OISR_OIS2; 00710 } 00711 else 00712 { 00713 TIM5->OISR &= (uint8_t)(~TIM_OISR_OIS2); 00714 } 00715 00716 /* Set the Pulse value */ 00717 TIM5->CCR2H = (uint8_t)(TIM5_Pulse >> 8); 00718 TIM5->CCR2L = (uint8_t)(TIM5_Pulse); 00719 } 00720 00721 /** 00722 * @brief Configures the Break feature, dead time, Lock level, the OSSI, 00723 * and the AOE(automatic output enable). 00724 * @param TIM5_OSSIState: Off-State Selection for Idle mode states. 00725 * This parameter can be one of the following values: 00726 * @arg TIM5_OSSIState_Enable: Off-State Selection for Idle mode enabled 00727 * @arg TIM5_OSSIState_Disable: Off-State Selection for Idle mode disabled 00728 * @param TIM5_LockLevel: Lock level. 00729 * This parameter can be one of the following values: 00730 * @arg TIM5_LockLevel_Off: Lock option disabled 00731 * @arg TIM5_LockLevel_1: Select Lock Level 1 00732 * @arg TIM5_LockLevel_2: Select Lock Level 2 00733 * @arg TIM5_LockLevel_3: Select Lock Level 3 00734 * @param TIM5_BreakState: Break Input enable/disable . 00735 * This parameter can be one of the following values: 00736 * @arg TIM5_BreakState_Disable: Break State disabled (break option disabled) 00737 * @arg TIM5_BreakState_Enable: Break State enabled (break option enabled) 00738 * @param TIM5_BreakPolarity: Break Polarity. 00739 * This parameter can be one of the following values: 00740 * @arg TIM5_BreakPolarity_High: if Break, channel polarity = High 00741 * @arg TIM5_BreakPolarity_Low: if Break, channel polarity = Low 00742 * @param TIM5_AutomaticOutput: TIM5 AOE Bit Set/Reset . 00743 * This parameter can be one of the following values: 00744 * @arg TIM5_AutomaticOutput_Enable: Automatic Output option enabled 00745 * @arg TIM5_AutomaticOutput_Disable: Automatic Output option disabled 00746 * @retval None 00747 */ 00748 void TIM5_BKRConfig(TIM5_OSSIState_TypeDef TIM5_OSSIState, 00749 TIM5_LockLevel_TypeDef TIM5_LockLevel, 00750 TIM5_BreakState_TypeDef TIM5_BreakState, 00751 TIM5_BreakPolarity_TypeDef TIM5_BreakPolarity, 00752 TIM5_AutomaticOutput_TypeDef TIM5_AutomaticOutput) 00753 00754 { 00755 /* Check the parameters */ 00756 assert_param(IS_TIM5_OSSI_STATE(TIM5_OSSIState)); 00757 assert_param(IS_TIM5_LOCK_LEVEL(TIM5_LockLevel)); 00758 assert_param(IS_TIM5_BREAK_STATE(TIM5_BreakState)); 00759 assert_param(IS_TIM5_BREAK_POLARITY(TIM5_BreakPolarity)); 00760 assert_param(IS_TIM5_AUTOMATIC_OUTPUT_STATE(TIM5_AutomaticOutput)); 00761 00762 00763 00764 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSI State, 00765 the dead time value and the Automatic Output Enable Bit */ 00766 TIM5->BKR = (uint8_t)((uint8_t)((uint8_t)((uint8_t)((uint8_t)TIM5_OSSIState | (uint8_t)TIM5_LockLevel) | \ 00767 (uint8_t)((uint8_t)TIM5_BreakState | (uint8_t)TIM5_BreakPolarity)) | \ 00768 TIM5_AutomaticOutput)); 00769 } 00770 00771 /** 00772 * @brief Enables or disables the TIM5 peripheral Main Outputs. 00773 * @param NewState: The new state of the TIM5 peripheral. 00774 * This parameter can be ENABLE or DISABLE 00775 * @retval None 00776 */ 00777 void TIM5_CtrlPWMOutputs(FunctionalState NewState) 00778 { 00779 /* Check the parameters */ 00780 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00781 00782 /* Set or Reset the MOE Bit */ 00783 00784 if (NewState != DISABLE) 00785 { 00786 TIM5->BKR |= TIM_BKR_MOE ; 00787 } 00788 else 00789 { 00790 TIM5->BKR &= (uint8_t)(~TIM_BKR_MOE) ; 00791 } 00792 } 00793 00794 /** 00795 * @brief Selects the TIM5 Output Compare Mode. This function disables the 00796 * selected channel before changing the Output Compare Mode. User has to 00797 * enable this channel using TIM5_CCxCmd and TIM5_CCxNCmd functions. 00798 * @param TIM5_Channel: Specifies the TIM5 Channel. 00799 * This parameter can be one of the following values: 00800 * @arg TIM5_Channel_1: Channel 1 00801 * @arg TIM5_Channel_2: Channel 2 00802 * @param TIM5_OCMode: Specifies the TIM5 Output Compare Mode. 00803 * This parameter can be one of the following values: 00804 * @arg TIM5_OCMode_Timing: Timing (Frozen) Mode 00805 * @arg TIM5_OCMode_Active: Active Mode 00806 * @arg TIM5_OCMode_Inactive: Inactive Mode 00807 * @arg TIM5_OCMode_Toggle: Toggle Mode 00808 * @arg TIM5_OCMode_PWM1: PWM Mode 1 00809 * @arg TIM5_OCMode_PWM2: PWM Mode 2 00810 * @retval None 00811 */ 00812 void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, 00813 TIM5_OCMode_TypeDef TIM5_OCMode) 00814 { 00815 /* Check the parameters */ 00816 assert_param(IS_TIM5_CHANNEL(TIM5_Channel)); 00817 assert_param(IS_TIM5_OCM(TIM5_OCMode)); 00818 00819 if (TIM5_Channel == TIM5_Channel_1) 00820 { 00821 /* Disable the Channel 1: Reset the CCE Bit */ 00822 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E); 00823 00824 /* Reset the Output Compare Bits */ 00825 TIM5->CCMR1 &= (uint8_t)(~TIM_CCMR_OCM); 00826 00827 /* Set the Output Compare Mode */ 00828 TIM5->CCMR1 |= (uint8_t)TIM5_OCMode; 00829 } 00830 else /* if (TIM5_Channel == TIM5_Channel_2) */ 00831 { 00832 /* Disable the Channel 2: Reset the CCE Bit */ 00833 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E); 00834 00835 /* Reset the Output Compare Bits */ 00836 TIM5->CCMR2 &= (uint8_t)(~TIM_CCMR_OCM); 00837 00838 /* Set the Output Compare Mode */ 00839 TIM5->CCMR2 |= (uint8_t)TIM5_OCMode; 00840 } 00841 } 00842 00843 /** 00844 * @brief Sets the TIM5 Capture Compare1 Register value. 00845 * @param Compare: Specifies the Capture Compare1 register new value. 00846 * This parameter is between 0x0000 and 0xFFFF. 00847 * @retval None 00848 */ 00849 void TIM5_SetCompare1(uint16_t Compare) 00850 { 00851 /* Set the Capture Compare1 Register value */ 00852 TIM5->CCR1H = (uint8_t)(Compare >> 8); 00853 TIM5->CCR1L = (uint8_t)(Compare); 00854 } 00855 00856 /** 00857 * @brief Sets the TIM5 Capture Compare2 Register value. 00858 * @param Compare: Specifies the Capture Compare2 register new value. 00859 * This parameter is between 0x0000 and 0xFFFF. 00860 * @retval None 00861 */ 00862 void TIM5_SetCompare2(uint16_t Compare) 00863 { 00864 /* Set the Capture Compare2 Register value */ 00865 TIM5->CCR2H = (uint8_t)(Compare >> 8); 00866 TIM5->CCR2L = (uint8_t)(Compare); 00867 } 00868 00869 /** 00870 * @brief Forces the TIM5 Channel1 output waveform to active or inactive level. 00871 * @param TIM5_ForcedAction: Specifies the forced Action to be set to the output waveform. 00872 * This parameter can be one of the following values: 00873 * @arg TIM5_ForcedAction_Active: Output Reference is forced low 00874 * @arg TIM5_ForcedAction_Inactive: Output Reference is forced high 00875 * @retval None 00876 */ 00877 void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction) 00878 { 00879 uint8_t tmpccmr1 = 0; 00880 00881 /* Check the parameters */ 00882 assert_param(IS_TIM5_FORCED_ACTION(TIM5_ForcedAction)); 00883 00884 tmpccmr1 = TIM5->CCMR1; 00885 00886 /* Reset the OCM Bits */ 00887 tmpccmr1 &= (uint8_t)(~TIM_CCMR_OCM); 00888 00889 /* Configure The Forced output Mode */ 00890 tmpccmr1 |= (uint8_t)TIM5_ForcedAction; 00891 00892 TIM5->CCMR1 = tmpccmr1; 00893 } 00894 00895 /** 00896 * @brief Forces the TIM5 Channel2 output waveform to active or inactive level. 00897 * @param TIM5_ForcedAction: Specifies the forced Action to be set to the output waveform. 00898 * This parameter can be one of the following values: 00899 * @arg TIM5_ForcedAction_Active: Output Reference is forced low 00900 * @arg TIM5_ForcedAction_Inactive: Output Reference is forced high 00901 * @retval None 00902 */ 00903 void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction) 00904 { 00905 uint8_t tmpccmr2 = 0; 00906 00907 /* Check the parameters */ 00908 assert_param(IS_TIM5_FORCED_ACTION(TIM5_ForcedAction)); 00909 00910 tmpccmr2 = TIM5->CCMR2; 00911 00912 /* Reset the OCM Bits */ 00913 tmpccmr2 &= (uint8_t)(~TIM_CCMR_OCM); 00914 00915 /* Configure The Forced output Mode */ 00916 tmpccmr2 |= (uint8_t)TIM5_ForcedAction; 00917 00918 TIM5->CCMR2 = tmpccmr2; 00919 } 00920 00921 /** 00922 * @brief Enables or disables the TIM5 peripheral Preload Register on CCR1. 00923 * @param NewState: The new state of the Capture Compare Preload register. 00924 * This parameter can be ENABLE or DISABLE 00925 * @retval None 00926 */ 00927 void TIM5_OC1PreloadConfig(FunctionalState NewState) 00928 { 00929 /* Check the parameters */ 00930 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00931 00932 /* Set or Reset the OC1PE Bit */ 00933 if (NewState != DISABLE) 00934 { 00935 TIM5->CCMR1 |= TIM_CCMR_OCxPE ; 00936 } 00937 else 00938 { 00939 TIM5->CCMR1 &= (uint8_t)(~TIM_CCMR_OCxPE) ; 00940 } 00941 } 00942 00943 /** 00944 * @brief Enables or disables the TIM5 peripheral Preload Register on CCR2. 00945 * @param NewState: The new state of the Capture Compare Preload register. 00946 * This parameter can be ENABLE or DISABLE 00947 * @retval None 00948 */ 00949 void TIM5_OC2PreloadConfig(FunctionalState NewState) 00950 { 00951 /* Check the parameters */ 00952 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00953 00954 /* Set or Reset the OC2PE Bit */ 00955 if (NewState != DISABLE) 00956 { 00957 TIM5->CCMR2 |= TIM_CCMR_OCxPE ; 00958 } 00959 else 00960 { 00961 TIM5->CCMR2 &= (uint8_t)(~TIM_CCMR_OCxPE) ; 00962 } 00963 } 00964 00965 /** 00966 * @brief Configures the TIM5 Capture Compare 1 Fast feature. 00967 * @param NewState: The new state of the Output Compare Fast Enable bit. 00968 * This parameter can be ENABLE or DISABLE 00969 * @retval None 00970 */ 00971 void TIM5_OC1FastConfig(FunctionalState NewState) 00972 { 00973 /* Check the parameters */ 00974 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00975 00976 /* Set or Reset the OC1FE Bit */ 00977 if (NewState != DISABLE) 00978 { 00979 TIM5->CCMR1 |= TIM_CCMR_OCxFE ; 00980 } 00981 else 00982 { 00983 TIM5->CCMR1 &= (uint8_t)(~TIM_CCMR_OCxFE) ; 00984 } 00985 } 00986 00987 /** 00988 * @brief Configures the TIM5 Capture Compare 2 Fast feature. 00989 * @param NewState: The new state of the Output Compare Fast Enable bit. 00990 * This parameter can be ENABLE or DISABLE 00991 * @retval None 00992 */ 00993 00994 void TIM5_OC2FastConfig(FunctionalState NewState) 00995 { 00996 /* Check the parameters */ 00997 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00998 00999 /* Set or Reset the OC2FE Bit */ 01000 if (NewState != DISABLE) 01001 { 01002 TIM5->CCMR2 |= TIM_CCMR_OCxFE ; 01003 } 01004 else 01005 { 01006 TIM5->CCMR2 &= (uint8_t)(~TIM_CCMR_OCxFE) ; 01007 } 01008 } 01009 01010 /** 01011 * @brief Configures the TIM5 Channel 1 polarity. 01012 * @param TIM5_OCPolarity: Specifies the OC1 Polarity. 01013 * This parameter can be one of the following values: 01014 * @arg TIM5_OCPolarity_High: Output compare polarity = High 01015 * @arg TIM5_OCPolarity_Low: Output compare polarity = Low 01016 * @retval None 01017 */ 01018 void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity) 01019 { 01020 /* Check the parameters */ 01021 assert_param(IS_TIM5_OC_POLARITY(TIM5_OCPolarity)); 01022 01023 /* Set or Reset the CC1P Bit */ 01024 if (TIM5_OCPolarity == TIM5_OCPolarity_Low) 01025 { 01026 TIM5->CCER1 |= TIM_CCER1_CC1P ; 01027 } 01028 else 01029 { 01030 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P) ; 01031 } 01032 } 01033 01034 /** 01035 * @brief Configures the TIM5 Channel 2 polarity. 01036 * @param TIM5_OCPolarity: Specifies the OC2 Polarity. 01037 * This parameter can be one of the following values: 01038 * @arg TIM5_OCPolarity_High: Output compare polarity = High 01039 * @arg TIM5_OCPolarity_Low: Output compare polarity = Low 01040 * @retval None 01041 */ 01042 void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity) 01043 { 01044 /* Check the parameters */ 01045 assert_param(IS_TIM5_OC_POLARITY(TIM5_OCPolarity)); 01046 01047 /* Set or Reset the CC2P Bit */ 01048 if (TIM5_OCPolarity == TIM5_OCPolarity_Low) 01049 { 01050 TIM5->CCER1 |= TIM_CCER1_CC2P ; 01051 } 01052 else 01053 { 01054 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ; 01055 } 01056 } 01057 01058 /** 01059 * @brief Enables or disables the TIM5 Capture Compare Channel x. 01060 * @param TIM5_Channel: Specifies the TIM5 Channel. 01061 * This parameter can be one of the following values: 01062 * @arg TIM5_Channel_1: Channel 1 01063 * @arg TIM5_Channel_2: Channel 2 01064 * @param NewState: Specifies the TIM5 Channel CCxE bit new state. 01065 * This parameter can be ENABLE or DISABLE 01066 * @retval None 01067 */ 01068 void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, 01069 FunctionalState NewState) 01070 { 01071 /* Check the parameters */ 01072 assert_param(IS_TIM5_CHANNEL(TIM5_Channel)); 01073 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01074 01075 if (TIM5_Channel == TIM5_Channel_1) 01076 { 01077 /* Set or Reset the CC1E Bit */ 01078 if (NewState != DISABLE) 01079 { 01080 TIM5->CCER1 |= TIM_CCER1_CC1E ; 01081 } 01082 else 01083 { 01084 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E) ; 01085 } 01086 01087 } 01088 else /* if (TIM5_Channel == TIM5_Channel_2) */ 01089 { 01090 /* Set or Reset the CC2E Bit */ 01091 if (NewState != DISABLE) 01092 { 01093 TIM5->CCER1 |= TIM_CCER1_CC2E; 01094 } 01095 else 01096 { 01097 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E) ; 01098 } 01099 } 01100 } 01101 01102 /** @defgroup TIM5_Group3 Input Capture management functions 01103 * @brief Input Capture management functions 01104 * 01105 @verbatim 01106 =============================================================================== 01107 Input Capture management functions 01108 =============================================================================== 01109 01110 =================================================================== 01111 TIM5 Driver: how to use it in Input Capture Mode 01112 =================================================================== 01113 To use the Timer in Input Capture mode, the following steps are mandatory: 01114 01115 1. Enable TIM5 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM5, ENABLE) function. 01116 01117 2. Configure the TIM5 pins in input mode by configuring the corresponding GPIO pins 01118 01119 3. Configure the Time base unit as described in the first part of this driver, if needed, 01120 otherwise the Timer will run with the default configuration: 01121 - Autoreload value = 0xFFFF 01122 - Prescaler value = 0x0 01123 - Counter mode = Up counting 01124 01125 4. Call TIM5_ICInit() to configure the desired channel to measure only 01126 frequency or duty cycle of the input signal using the corresponding configuration: 01127 - TIM5 Channel: TIM5_Channel 01128 - TIM5 Input Capture polarity: TIM5_ICPolarity 01129 - TIM5 Input Capture selection: TIM5_ICSelection 01130 - TIM5 Input Capture Prescaler: TIM5_ICPSC 01131 - TIM5 Input Capture filter value 01132 or, 01133 Call TIM5_PWMIConfig() to configure the desired channels with the 01134 corresponding configuration and to measure the frequency and the duty 01135 cycle of the input signal. 01136 01137 5. Enable global interrupts or the DMA to read the measured frequency. 01138 01139 6. Enable the corresponding interrupt (or DMA request) to read the captured value, 01140 using the function TIM5_ITConfig(TIM5_IT_CCx) (or TIM5_DMACmd(TIM5_DMASource_CCx)) 01141 01142 7. Call the TIM5_Cmd(ENABLE) function to enable the TIM5 counter. 01143 01144 8. Use TIM5_GetCapturex() to read the captured value corresponding to 01145 channel x. 01146 01147 Note1: All other functions can be used separately to modify, if needed, 01148 a specific feature of the Timer. 01149 01150 @endverbatim 01151 * @{ 01152 */ 01153 01154 /** 01155 * @brief Initializes the TIM5 peripheral according to the specified parameters. 01156 * @param TIM5_Channel: TIM5 Channel 01157 * This parameter can be one of the following values: 01158 * @arg TIM5_Channel_1: Channel 1 01159 * @arg TIM5_Channel_2: Channel 2 01160 * @param TIM5_ICPolarity: Input Capture Polarity 01161 * This parameter can be one of the following values: 01162 * @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge 01163 * @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge 01164 * @param TIM5_ICSelection: Input Capture Selection 01165 * This parameter can be one of the following values: 01166 * @arg TIM5_ICSelection_DirectTI: Input Capture mapped on the direct input 01167 * @arg TIM5_ICSelection_IndirectTI: Input Capture mapped on the indirect input 01168 * @arg TIM5_ICSelection_TRGI: Input Capture mapped on the Trigger Input 01169 * @param TIM5_ICPrescaler: Input Capture Prescaler 01170 * This parameter can be one of the following values: 01171 * @arg TIM5_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event) 01172 * @arg TIM5_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events) 01173 * @arg TIM5_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events) 01174 * @arg TIM5_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 01175 * @param TIM5_ICFilter: This parameter must be a value between 0x00 and 0x0F. 01176 * @retval None 01177 */ 01178 void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel, 01179 TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 01180 TIM5_ICSelection_TypeDef TIM5_ICSelection, 01181 TIM5_ICPSC_TypeDef TIM5_ICPrescaler, 01182 uint8_t TIM5_ICFilter) 01183 { 01184 /* Check the parameters */ 01185 assert_param(IS_TIM5_CHANNEL(TIM5_Channel)); 01186 01187 if (TIM5_Channel == TIM5_Channel_1) 01188 { 01189 /* TI1 Configuration */ 01190 TI1_Config(TIM5_ICPolarity, TIM5_ICSelection, TIM5_ICFilter); 01191 01192 /* Set the Input Capture Prescaler value */ 01193 TIM5_SetIC1Prescaler(TIM5_ICPrescaler); 01194 } 01195 else /* if (TIM5_Channel == TIM5_Channel_2) */ 01196 { 01197 /* TI2 Configuration */ 01198 TI2_Config(TIM5_ICPolarity, TIM5_ICSelection, TIM5_ICFilter); 01199 01200 /* Set the Input Capture Prescaler value */ 01201 TIM5_SetIC2Prescaler(TIM5_ICPrescaler); 01202 } 01203 } 01204 01205 /** 01206 * @brief Configures the TIM5 peripheral in PWM Input Mode according to the 01207 * specified parameters. 01208 * @param TIM5_Channel: TIM5 Channel 01209 * This parameter can be one of the following values: 01210 * @arg TIM5_Channel_1: Channel 1 01211 * @arg TIM5_Channel_2: Channel 2 01212 * @param TIM5_ICPolarity: Input Capture Polarity 01213 * This parameter can be one of the following values: 01214 * @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge 01215 * @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge 01216 * @param TIM5_ICSelection: Input Capture Selection 01217 * This parameter can be one of the following values: 01218 * @arg TIM5_ICSelection_DirectTI: Input Capture mapped on the direct input 01219 * @arg TIM5_ICSelection_IndirectTI: Input Capture mapped on the indirect input 01220 * @arg TIM5_ICSelection_TRGI: Input Capture mapped on the Trigger Input 01221 * @param TIM5_ICPrescaler: Input Capture Prescaler 01222 * This parameter can be one of the following values: 01223 * @arg TIM5_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event) 01224 * @arg TIM5_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events) 01225 * @arg TIM5_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events) 01226 * @arg TIM5_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 01227 * @retval None 01228 */ 01229 void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel, 01230 TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 01231 TIM5_ICSelection_TypeDef TIM5_ICSelection, 01232 TIM5_ICPSC_TypeDef TIM5_ICPrescaler, 01233 uint8_t TIM5_ICFilter) 01234 { 01235 uint8_t icpolarity = TIM5_ICPolarity_Rising; 01236 uint8_t icselection = TIM5_ICSelection_DirectTI; 01237 01238 /* Check the parameters */ 01239 assert_param(IS_TIM5_CHANNEL(TIM5_Channel)); 01240 01241 /* Select the Opposite Input Polarity */ 01242 if (TIM5_ICPolarity == TIM5_ICPolarity_Rising) 01243 { 01244 icpolarity = TIM5_ICPolarity_Falling; 01245 } 01246 else 01247 { 01248 icpolarity = TIM5_ICPolarity_Rising; 01249 } 01250 01251 /* Select the Opposite Input */ 01252 if (TIM5_ICSelection == TIM5_ICSelection_DirectTI) 01253 { 01254 icselection = TIM5_ICSelection_IndirectTI; 01255 } 01256 else 01257 { 01258 icselection = TIM5_ICSelection_DirectTI; 01259 } 01260 01261 if (TIM5_Channel == TIM5_Channel_1) 01262 { 01263 /* TI1 Configuration */ 01264 TI1_Config(TIM5_ICPolarity, TIM5_ICSelection, 01265 TIM5_ICFilter); 01266 01267 /* Set the Input Capture Prescaler value */ 01268 TIM5_SetIC1Prescaler(TIM5_ICPrescaler); 01269 01270 /* TI2 Configuration */ 01271 TI2_Config((TIM5_ICPolarity_TypeDef)icpolarity, (TIM5_ICSelection_TypeDef)icselection, TIM5_ICFilter); 01272 01273 /* Set the Input Capture Prescaler value */ 01274 TIM5_SetIC2Prescaler(TIM5_ICPrescaler); 01275 } 01276 else 01277 { 01278 /* TI2 Configuration */ 01279 TI2_Config(TIM5_ICPolarity, TIM5_ICSelection, 01280 TIM5_ICFilter); 01281 01282 /* Set the Input Capture Prescaler value */ 01283 TIM5_SetIC2Prescaler(TIM5_ICPrescaler); 01284 01285 /* TI1 Configuration */ 01286 TI1_Config((TIM5_ICPolarity_TypeDef)icpolarity, (TIM5_ICSelection_TypeDef)icselection, TIM5_ICFilter); 01287 01288 /* Set the Input Capture Prescaler value */ 01289 TIM5_SetIC1Prescaler(TIM5_ICPrescaler); 01290 } 01291 } 01292 01293 /** 01294 * @brief Gets the TIM5 Input Capture 1 value. 01295 * @param None 01296 * @retval Capture Compare 1 Register value. 01297 */ 01298 uint16_t TIM5_GetCapture1(void) 01299 { 01300 uint16_t tmpccr1 = 0; 01301 uint8_t tmpccr1l, tmpccr1h; 01302 01303 tmpccr1h = TIM5->CCR1H; 01304 tmpccr1l = TIM5->CCR1L; 01305 01306 tmpccr1 = (uint16_t)(tmpccr1l); 01307 tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8); 01308 /* Get the Capture 1 Register value */ 01309 return ((uint16_t)tmpccr1); 01310 } 01311 01312 /** 01313 * @brief Gets the TIM5 Input Capture 2 value. 01314 * @param None 01315 * @retval Capture Compare 2 Register value. 01316 */ 01317 uint16_t TIM5_GetCapture2(void) 01318 { 01319 uint16_t tmpccr2 = 0; 01320 uint8_t tmpccr2l, tmpccr2h; 01321 01322 tmpccr2h = TIM5->CCR2H; 01323 tmpccr2l = TIM5->CCR2L; 01324 01325 tmpccr2 = (uint16_t)(tmpccr2l); 01326 tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8); 01327 /* Get the Capture 2 Register value */ 01328 return ((uint16_t)tmpccr2); 01329 } 01330 01331 /** 01332 * @brief Sets the TIM5 Input Capture 1 prescaler. 01333 * @param TIM5_IC1Prescaler: Specifies the Input Capture prescaler new value 01334 * This parameter can be one of the following values: 01335 * @arg TIM5_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event) 01336 * @arg TIM5_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events) 01337 * @arg TIM5_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events) 01338 * @arg TIM5_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 01339 * @retval None 01340 */ 01341 void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler) 01342 { 01343 uint8_t tmpccmr1 = 0; 01344 01345 /* Check the parameters */ 01346 assert_param(IS_TIM5_IC_PRESCALER(TIM5_IC1Prescaler)); 01347 01348 tmpccmr1 = TIM5->CCMR1; 01349 01350 /* Reset the IC1PSC Bits */ 01351 tmpccmr1 &= (uint8_t)(~TIM_CCMR_ICxPSC); 01352 01353 /* Set the IC1PSC value */ 01354 tmpccmr1 |= (uint8_t)TIM5_IC1Prescaler; 01355 01356 TIM5->CCMR1 = tmpccmr1; 01357 } 01358 01359 /** 01360 * @brief Sets the TIM5 Input Capture 2 prescaler. 01361 * @param TIM5_IC2Prescaler: Specifies the Input Capture prescaler new value 01362 * This parameter can be one of the following values: 01363 * @arg TIM5_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event) 01364 * @arg TIM5_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events) 01365 * @arg TIM5_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events) 01366 * @arg TIM5_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 01367 * @retval None 01368 */ 01369 void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler) 01370 { 01371 uint8_t tmpccmr2 = 0; 01372 01373 /* Check the parameters */ 01374 assert_param(IS_TIM5_IC_PRESCALER(TIM5_IC2Prescaler)); 01375 01376 tmpccmr2 = TIM5->CCMR2; 01377 01378 /* Reset the IC2PSC Bits */ 01379 tmpccmr2 &= (uint8_t)(~TIM_CCMR_ICxPSC); 01380 01381 /* Set the IC2PSC value */ 01382 tmpccmr2 |= (uint8_t)TIM5_IC2Prescaler; 01383 01384 TIM5->CCMR2 = tmpccmr2; 01385 } 01386 01387 /** 01388 * @} 01389 */ 01390 01391 /** @defgroup TIM5_Group4 Interrupts DMA and flags management functions 01392 * @brief Interrupts, DMA and flags management functions 01393 * 01394 @verbatim 01395 =============================================================================== 01396 Interrupts, DMA and flags management functions 01397 =============================================================================== 01398 01399 @endverbatim 01400 * @{ 01401 */ 01402 01403 /** 01404 * @brief Enables or disables the specified TIM5 interrupts. 01405 * @param TIM5_IT: Specifies the TIM5 interrupts sources to be enabled or disabled. 01406 * This parameter can be any combination of the following values: 01407 * @arg TIM5_IT_Update: Update 01408 * @arg TIM5_IT_CC1: Capture Compare Channel1 01409 * @arg TIM5_IT_CC2: Capture Compare Channel2 01410 * @arg TIM5_IT_Trigger: Trigger 01411 * @arg TIM5_IT_Break: Break 01412 * @param NewState: The new state of the TIM5 peripheral. 01413 * This parameter can be ENABLE or DISABLE 01414 * @retval None 01415 */ 01416 void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState) 01417 { 01418 /* Check the parameters */ 01419 assert_param(IS_TIM5_IT(TIM5_IT)); 01420 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01421 01422 if (NewState != DISABLE) 01423 { 01424 /* Enable the Interrupt sources */ 01425 TIM5->IER |= (uint8_t)TIM5_IT; 01426 } 01427 else 01428 { 01429 /* Disable the Interrupt sources */ 01430 TIM5->IER &= (uint8_t)(~(uint8_t)TIM5_IT); 01431 } 01432 } 01433 01434 /** 01435 * @brief Configures the TIM5 event to be generated by software. 01436 * @param TIM5_EventSource: Specifies the event source. 01437 * This parameter can be any combination of the following values: 01438 * @arg TIM5_EventSource_Update: Update 01439 * @arg TIM5_EventSource_CC1: Capture Compare Channel1 01440 * @arg TIM5_EventSource_CC2: Capture Compare Channel2 01441 * @arg TIM5_EventSource_Trigger: Trigger 01442 * @arg TIM5_EventSource_Break: Break 01443 * @retval None 01444 */ 01445 void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource) 01446 { 01447 /* Check the parameters */ 01448 assert_param(IS_TIM5_EVENT_SOURCE((uint8_t)TIM5_EventSource)); 01449 01450 /* Set the event sources */ 01451 TIM5->EGR |= (uint8_t)TIM5_EventSource; 01452 } 01453 01454 /** 01455 * @brief Checks whether the specified TIM5 flag is set or not. 01456 * @param TIM5_FLAG: Specifies the flag to check. 01457 * This parameter can be any combination of the following values: 01458 * @arg TIM5_FLAG_Update: Update 01459 * @arg TIM5_FLAG_CC1: Capture Compare Channel1 01460 * @arg TIM5_FLAG_CC2: Capture Compare Channel2 01461 * @arg TIM5_FLAG_Trigger: Trigger 01462 * @arg TIM5_FLAG_Break: Break 01463 * @arg TIM5_FLAG_CC1OF: Capture compare 1 over capture 01464 * @arg TIM5_FLAG_CC2OF: Capture compare 2 over capture 01465 * @retval FlagStatus: The new state of TIM5_FLAG (SET or RESET) 01466 */ 01467 FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG) 01468 { 01469 FlagStatus bitstatus = RESET; 01470 uint8_t tim5_flag_l = 0, tim5_flag_h = 0; 01471 01472 /* Check the parameters */ 01473 assert_param(IS_TIM5_GET_FLAG(TIM5_FLAG)); 01474 01475 tim5_flag_l = (uint8_t)(TIM5->SR1 & (uint8_t)(TIM5_FLAG)); 01476 tim5_flag_h = (uint8_t)(TIM5->SR2 & (uint8_t)((uint16_t)TIM5_FLAG >> 8)); 01477 01478 if ((uint8_t)(tim5_flag_l | tim5_flag_h) != 0) 01479 { 01480 bitstatus = SET; 01481 } 01482 else 01483 { 01484 bitstatus = RESET; 01485 } 01486 return ((FlagStatus)bitstatus); 01487 } 01488 01489 /** 01490 * @brief Clears the TIM�s pending flags. 01491 * @param TIM5_FLAG: Specifies the flag to clear. 01492 * This parameter can be any combination of the following values: 01493 * @arg TIM5_FLAG_Update: Update 01494 * @arg TIM5_FLAG_CC1: Capture Compare Channel1 01495 * @arg TIM5_FLAG_CC2: Capture Compare Channel2 01496 * @arg TIM5_FLAG_Trigger: Trigger 01497 * @arg TIM5_FLAG_Break: Break 01498 * @retval None 01499 */ 01500 void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG) 01501 { 01502 /* Check the parameters */ 01503 assert_param(IS_TIM5_CLEAR_FLAG((uint16_t)TIM5_FLAG)); 01504 /* Clear the flags (rc_w0) clear this bit by writing 0. Writing �1� has no effect*/ 01505 TIM5->SR1 = (uint8_t)(~(uint8_t)(TIM5_FLAG)); 01506 TIM5->SR2 = (uint8_t)(~(uint8_t)((uint16_t)TIM5_FLAG >> 8)); 01507 } 01508 01509 /** 01510 * @brief Checks whether the TIM5 interrupt has occurred or not. 01511 * @param TIM5_IT: Specifies the TIM5 interrupt source to check. 01512 * This parameter can be any combination of the following values: 01513 * @arg TIM5_IT_Update: Update 01514 * @arg TIM5_IT_CC1: Capture Compare Channel1 01515 * @arg TIM5_IT_CC2: Capture Compare Channel2 01516 * @arg TIM5_IT_Trigger: Trigger 01517 * @arg TIM5_IT_Break: Break 01518 * @retval ITStatus: The new state of the TIM5_IT (SET or RESET) 01519 */ 01520 ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT) 01521 { 01522 ITStatus bitstatus = RESET; 01523 01524 uint8_t TIM5_itStatus = 0x0, TIM5_itEnable = 0x0; 01525 01526 /* Check the parameters */ 01527 assert_param(IS_TIM5_GET_IT(TIM5_IT)); 01528 01529 TIM5_itStatus = (uint8_t)(TIM5->SR1 & (uint8_t)TIM5_IT); 01530 01531 TIM5_itEnable = (uint8_t)(TIM5->IER & (uint8_t)TIM5_IT); 01532 01533 if ((TIM5_itStatus != (uint8_t)RESET ) && (TIM5_itEnable != (uint8_t)RESET)) 01534 { 01535 bitstatus = (ITStatus)SET; 01536 } 01537 else 01538 { 01539 bitstatus = (ITStatus)RESET; 01540 } 01541 return ((ITStatus)bitstatus); 01542 } 01543 01544 /** 01545 * @brief Clears the TIM's interrupt pending bits. 01546 * @param TIM5_IT: Specifies the pending bit to clear. 01547 * This parameter can be any combination of the following values: 01548 * @arg TIM5_IT_Update: Update 01549 * @arg TIM5_IT_CC1: Capture Compare Channel1 01550 * @arg TIM5_IT_CC2: Capture Compare Channel2 01551 * @arg TIM5_IT_Trigger: Trigger 01552 * @arg TIM5_IT_Break: Break 01553 * @retval None 01554 */ 01555 void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT) 01556 { 01557 /* Check the parameters */ 01558 assert_param(IS_TIM5_IT(TIM5_IT)); 01559 01560 /* Clear the IT pending Bit */ 01561 TIM5->SR1 = (uint8_t)(~(uint8_t)TIM5_IT); 01562 } 01563 01564 /** 01565 * @brief Enables or disables the TIM5 DMA Requests. 01566 * @param TIM5_DMASource: specifies the DMA Request sources. 01567 * This parameter can be any combination of the following values: 01568 * @arg TIM5_DMASource_Update: TIM5 DMA Update Request 01569 * @arg TIM5_DMASource_CC1: TIM5 DMA CC1 Request 01570 * @arg TIM5_DMASource_CC2: TIM5 DMA CC2 Request 01571 * @param NewState: new state of the DMA Request sources. 01572 * This parameter can be: ENABLE or DISABLE. 01573 * @retval None 01574 */ 01575 void TIM5_DMACmd( TIM5_DMASource_TypeDef TIM5_DMASource, FunctionalState NewState) 01576 { 01577 /* Check the parameters */ 01578 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01579 assert_param(IS_TIM5_DMA_SOURCE(TIM5_DMASource)); 01580 01581 if (NewState != DISABLE) 01582 { 01583 /* Enable the DMA sources */ 01584 TIM5->DER |= TIM5_DMASource; 01585 } 01586 else 01587 { 01588 /* Disable the DMA sources */ 01589 TIM5->DER &= (uint8_t)(~TIM5_DMASource); 01590 } 01591 } 01592 01593 /** 01594 * @brief Selects the TIM5 peripheral Capture Compare DMA source. 01595 * @param NewState: new state of the Capture Compare DMA source. 01596 * This parameter can be: ENABLE or DISABLE. 01597 * @retval None 01598 */ 01599 void TIM5_SelectCCDMA(FunctionalState NewState) 01600 { 01601 /* Check the parameters */ 01602 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01603 01604 if (NewState != DISABLE) 01605 { 01606 /* Set the CCDS Bit */ 01607 TIM5->CR2 |= TIM_CR2_CCDS; 01608 } 01609 else 01610 { 01611 /* Reset the CCDS Bit */ 01612 TIM5->CR2 &= (uint8_t)(~TIM_CR2_CCDS); 01613 } 01614 } 01615 01616 /** 01617 * @} 01618 */ 01619 01620 /** @defgroup TIM5_Group5 Clocks management functions 01621 * @brief Clocks management functions 01622 * 01623 @verbatim 01624 =============================================================================== 01625 Clocks management functions 01626 =============================================================================== 01627 01628 @endverbatim 01629 * @{ 01630 */ 01631 01632 /** 01633 * @brief Enables the TIM5 internal Clock. 01634 * @par Parameters: 01635 * None 01636 * @retval None 01637 */ 01638 void TIM5_InternalClockConfig(void) 01639 { 01640 /* Disable slave mode to clock the prescaler directly with the internal clock */ 01641 TIM5->SMCR &= (uint8_t)(~TIM_SMCR_SMS); 01642 } 01643 01644 /** 01645 * @brief Configures the TIM5 Trigger as External Clock. 01646 * @param TIM5_TIxExternalCLKSource: Specifies Trigger source. 01647 * This parameter can be one of the following values: 01648 * @arg TIM5_TIxExternalCLK1Source_TI1ED: External Clock mode 1 source = TI1ED 01649 * @arg TIM5_TIxExternalCLK1Source_TI1: External Clock mode 1 source = TI1 01650 * @arg TIM5_TIxExternalCLK1Source_TI2: External Clock mode 1 source = TI2 01651 * @param TIM5_ICPolarity: Specifies the TIx Polarity. 01652 * This parameter can be one of the following values: 01653 * @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge 01654 * @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge 01655 * @param ICFilter: Specifies the filter value. 01656 * This parameter must be a value between 0x00 and 0x0F 01657 * @retval None 01658 */ 01659 void TIM5_TIxExternalClockConfig(TIM5_TIxExternalCLK1Source_TypeDef TIM5_TIxExternalCLKSource, 01660 TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 01661 uint8_t ICFilter) 01662 { 01663 /* Check the parameters */ 01664 assert_param(IS_TIM5_TIXCLK_SOURCE(TIM5_TIxExternalCLKSource)); 01665 assert_param(IS_TIM5_IC_POLARITY(TIM5_ICPolarity)); 01666 assert_param(IS_TIM5_IC_FILTER(ICFilter)); 01667 01668 /* Configure the TIM5 Input Clock Source */ 01669 if (TIM5_TIxExternalCLKSource == TIM5_TIxExternalCLK1Source_TI2) 01670 { 01671 TI2_Config(TIM5_ICPolarity, TIM5_ICSelection_DirectTI, ICFilter); 01672 } 01673 else 01674 { 01675 TI1_Config(TIM5_ICPolarity, TIM5_ICSelection_DirectTI, ICFilter); 01676 } 01677 01678 /* Select the Trigger source */ 01679 TIM5_SelectInputTrigger((TIM5_TRGSelection_TypeDef)TIM5_TIxExternalCLKSource); 01680 01681 /* Select the External clock mode1 */ 01682 TIM5->SMCR |= (uint8_t)(TIM5_SlaveMode_External1); 01683 } 01684 01685 /** 01686 * @brief Configures the TIM5 External clock Mode1. 01687 * @param TIM5_ExtTRGPrescaler: Specifies the external Trigger Prescaler. 01688 * This parameter can be one of the following values: 01689 * @arg TIM5_ExtTRGPSC_OFF: No External Trigger prescaler 01690 * @arg TIM5_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2) 01691 * @arg TIM5_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4) 01692 * @arg TIM5_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8) 01693 * @param TIM5_ExtTRGPolarity: Specifies the external Trigger Polarity. 01694 * This parameter can be one of the following values: 01695 * @arg TIM5_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted 01696 * @arg TIM5_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted 01697 * @param ExtTRGFilter: Specifies the External Trigger Filter. 01698 * This parameter must be a value between 0x00 and 0x0F 01699 * @retval None 01700 */ 01701 void TIM5_ETRClockMode1Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler, 01702 TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity, 01703 uint8_t ExtTRGFilter) 01704 { 01705 /* Configure the ETR Clock source */ 01706 TIM5_ETRConfig(TIM5_ExtTRGPrescaler, TIM5_ExtTRGPolarity, ExtTRGFilter); 01707 01708 /* Select the External clock mode1 */ 01709 TIM5->SMCR &= (uint8_t)(~TIM_SMCR_SMS); 01710 TIM5->SMCR |= (uint8_t)(TIM5_SlaveMode_External1); 01711 01712 /* Select the Trigger selection: ETRF */ 01713 TIM5->SMCR &= (uint8_t)(~TIM_SMCR_TS); 01714 TIM5->SMCR |= (uint8_t)((TIM5_TRGSelection_TypeDef)TIM5_TRGSelection_ETRF); 01715 } 01716 01717 /** 01718 * @brief Configures the TIM5 External clock Mode2. 01719 * @param TIM5_ExtTRGPrescaler: Specifies the external Trigger Prescaler. 01720 * This parameter can be one of the following values: 01721 * @arg TIM5_ExtTRGPSC_OFF: No External Trigger prescaler 01722 * @arg TIM5_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2) 01723 * @arg TIM5_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4) 01724 * @arg TIM5_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8) 01725 * @param TIM5_ExtTRGPolarity: Specifies the external Trigger Polarity. 01726 * This parameter can be one of the following values: 01727 * @arg TIM5_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted 01728 * @arg TIM5_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted 01729 * @param ExtTRGFilter: Specifies the External Trigger Filter. 01730 * This parameter must be a value between 0x00 and 0x0F 01731 * @retval None 01732 */ 01733 void TIM5_ETRClockMode2Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler, 01734 TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity, 01735 uint8_t ExtTRGFilter) 01736 { 01737 /* Configure the ETR Clock source */ 01738 TIM5_ETRConfig(TIM5_ExtTRGPrescaler, TIM5_ExtTRGPolarity, ExtTRGFilter); 01739 01740 /* Enable the External clock mode2 */ 01741 TIM5->ETR |= TIM_ETR_ECE ; 01742 } 01743 01744 /** 01745 * @} 01746 */ 01747 01748 /** @defgroup TIM5_Group6 Synchronization management functions 01749 * @brief Synchronization management functions 01750 * 01751 @verbatim 01752 =============================================================================== 01753 Synchronization management functions 01754 =============================================================================== 01755 01756 =================================================================== 01757 TIM5 Driver: how to use it in synchronization Mode 01758 =================================================================== 01759 Case of two/several Timers 01760 ************************** 01761 1. If TIM5 is used as master to other timers use the following functions: 01762 - TIM5_SelectOutputTrigger() 01763 - TIM5_SelectMasterSlaveMode() 01764 2. If TIM5 is used as slave to other timers use the following functions: 01765 - TIM5_SelectInputTrigger() 01766 - TIM5_SelectSlaveMode() 01767 01768 Case of Timers and external trigger (TRIG pin) 01769 ******************************************** 01770 1. Configure the External trigger using TIM5_ETRConfig() 01771 2. Configure the Slave Timer using the following functions: 01772 - TIM5_SelectInputTrigger() 01773 - TIM5_SelectSlaveMode() 01774 01775 @endverbatim 01776 * @{ 01777 */ 01778 01779 /** 01780 * @brief Selects the TIM5 Input Trigger source. 01781 * @param TIM5_InputTriggerSource: Specifies Input Trigger source. 01782 * This parameter can be one of the following values: 01783 * @arg TIM5_TRGSelection_TIM4: TRIG Input source = TIM TRIG Output 01784 * @arg TIM5_TRGSelection_TIM1: TRIG Input source = TIM TRIG Output 01785 * @arg TIM5_TRGSelection_TIM3: TRIG Input source = TIM TRIG Output 01786 * @arg TIM5_TRGSelection_TIM2: TRIG Input source = TIM TRIG Output 01787 * @arg TIM5_TRGSelection_TI1F_ED: TRIG Input source = TI1F_ED (TI1 Edge Detector) 01788 * @arg TIM5_TRGSelection_TI1FP1: TRIG Input source = TI1FP1 (Filtred Timer Input 1) 01789 * @arg TIM5_TRGSelection_TI2FP2: TRIG Input source = TI2FP2 (Filtred Timer Input 2) 01790 * @arg TIM5_TRGSelection_ETRF: TRIG Input source = ETRF (External Trigger Input ) 01791 * @retval None 01792 */ 01793 void TIM5_SelectInputTrigger(TIM5_TRGSelection_TypeDef TIM5_InputTriggerSource) 01794 { 01795 uint8_t tmpsmcr = 0; 01796 01797 /* Check the parameters */ 01798 assert_param(IS_TIM5_TRIGGER_SELECTION(TIM5_InputTriggerSource)); 01799 01800 tmpsmcr = TIM5->SMCR; 01801 01802 /* Select the Trigger Source */ 01803 tmpsmcr &= (uint8_t)(~TIM_SMCR_TS); 01804 tmpsmcr |= (uint8_t)TIM5_InputTriggerSource; 01805 01806 TIM5->SMCR = (uint8_t)tmpsmcr; 01807 } 01808 01809 /** 01810 * @brief Selects the TIM5 Trigger Output Mode. 01811 * @param TIM5_TRGOSource: Specifies the Trigger Output source. 01812 * This parameter can be one of the following values: 01813 * @arg TIM5_TRGOSource_Reset: Trigger Output source = Reset 01814 * @arg TIM5_TRGOSource_Enable: Trigger Output source = TIM5 is enabled 01815 * @arg TIM5_TRGOSource_Update: Trigger Output source = Update event 01816 * @arg TIM5_TRGOSource_OC1: Trigger Output source = output compare channel1 01817 * @arg TIM5_TRGOSource_OC1REF: Trigger Output source = output compare channel 1 reference 01818 * @arg TIM5_TRGOSource_OC2REF: Trigger Output source = output compare channel 2 reference 01819 * @retval None 01820 */ 01821 void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource) 01822 { 01823 uint8_t tmpcr2 = 0; 01824 01825 /* Check the parameters */ 01826 assert_param(IS_TIM5_TRGO_SOURCE(TIM5_TRGOSource)); 01827 01828 tmpcr2 = TIM5->CR2; 01829 01830 /* Reset the MMS Bits */ 01831 tmpcr2 &= (uint8_t)(~TIM_CR2_MMS); 01832 01833 /* Select the TRGO source */ 01834 tmpcr2 |= (uint8_t)TIM5_TRGOSource; 01835 01836 TIM5->CR2 = tmpcr2; 01837 } 01838 01839 /** 01840 * @brief Selects the TIM5 Slave Mode. 01841 * @param TIM5_SlaveMode: Specifies the TIM5 Slave Mode. 01842 * This parameter can be one of the following values: 01843 * @arg TIM5_SlaveMode_Reset: Slave Mode Selection = Reset 01844 * @arg TIM5_SlaveMode_Gated: Slave Mode Selection = Gated 01845 * @arg TIM5_SlaveMode_Trigger: Slave Mode Selection = Trigger 01846 * @arg TIM5_SlaveMode_External1: Slave Mode Selection = External 1 01847 * @retval None 01848 */ 01849 void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode) 01850 { 01851 uint8_t tmpsmcr = 0; 01852 01853 /* Check the parameters */ 01854 assert_param(IS_TIM5_SLAVE_MODE(TIM5_SlaveMode)); 01855 01856 tmpsmcr = TIM5->SMCR; 01857 01858 /* Reset the SMS Bits */ 01859 tmpsmcr &= (uint8_t)(~TIM_SMCR_SMS); 01860 01861 /* Select the Slave Mode */ 01862 tmpsmcr |= (uint8_t)TIM5_SlaveMode; 01863 01864 TIM5->SMCR = tmpsmcr; 01865 } 01866 01867 /** 01868 * @brief Sets or Resets the TIM5 Master/Slave Mode. 01869 * @param NewState: The new state of the synchronization between TIM5 and its slaves (through TRGO). 01870 * This parameter can be ENABLE or DISABLE 01871 * @retval None 01872 */ 01873 void TIM5_SelectMasterSlaveMode(FunctionalState NewState) 01874 { 01875 /* Check the parameters */ 01876 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01877 01878 /* Set or Reset the MSM Bit */ 01879 if (NewState != DISABLE) 01880 { 01881 TIM5->SMCR |= TIM_SMCR_MSM; 01882 } 01883 else 01884 { 01885 TIM5->SMCR &= (uint8_t)(~TIM_SMCR_MSM); 01886 } 01887 } 01888 01889 /** 01890 * @brief Configures the TIM5 External Trigger. 01891 * @param TIM5_ExtTRGPrescaler: Specifies the external Trigger Prescaler. 01892 * This parameter can be one of the following values: 01893 * @arg TIM5_ExtTRGPSC_OFF: No External Trigger prescaler 01894 * @arg TIM5_ExtTRGPSC_DIV2: External Trigger prescaler = 2 (ETRP frequency divided by 2) 01895 * @arg TIM5_ExtTRGPSC_DIV4: External Trigger prescaler = 4 (ETRP frequency divided by 4) 01896 * @arg TIM5_ExtTRGPSC_DIV8: External Trigger prescaler = 8 (ETRP frequency divided by 8) 01897 * @param TIM5_ExtTRGPolarity: Specifies the external Trigger Polarity. 01898 * This parameter can be one of the following values: 01899 * @arg TIM5_ExtTRGPolarity_Inverted: External Trigger Polarity = inverted 01900 * @arg TIM5_ExtTRGPolarity_NonInverted: External Trigger Polarity = non inverted 01901 * @param ExtTRGFilter: Specifies the External Trigger Filter. 01902 * This parameter must be a value between 0x00 and 0x0F 01903 * @retval None 01904 */ 01905 void TIM5_ETRConfig(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler, 01906 TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity, 01907 uint8_t ExtTRGFilter) 01908 { 01909 /* Check the parameters */ 01910 assert_param(IS_TIM5_EXT_PRESCALER(TIM5_ExtTRGPrescaler)); 01911 assert_param(IS_TIM5_EXT_POLARITY(TIM5_ExtTRGPolarity)); 01912 assert_param(IS_TIM5_EXT_FILTER(ExtTRGFilter)); 01913 01914 /* Set the Prescaler, the Filter value and the Polarity */ 01915 TIM5->ETR |= (uint8_t)((uint8_t)((uint8_t)TIM5_ExtTRGPrescaler | (uint8_t)TIM5_ExtTRGPolarity) 01916 | (uint8_t)ExtTRGFilter); 01917 } 01918 01919 /** 01920 * @} 01921 */ 01922 01923 /** @defgroup TIM5_Group7 Specific interface management functions 01924 * @brief Specific interface management functions 01925 * 01926 @verbatim 01927 =============================================================================== 01928 Specific interface management functions 01929 =============================================================================== 01930 01931 @endverbatim 01932 * @{ 01933 */ 01934 01935 /** 01936 * @brief Configures the TIM5 Encoder Interface. 01937 * @param TIM5_EncoderMode: Specifies the TIM5 Encoder Mode. 01938 * This parameter can be one of the following values: 01939 * @arg TIM5_EncoderMode_TI1: Encoder mode 1 01940 * @arg TIM5_EncoderMode_TI2: Encoder mode 2 01941 * @arg TIM5_EncoderMode_TI12: Encoder mode 3 01942 * @param TIM5_IC1Polarity: Specifies the IC1 Polarity. 01943 * This parameter can be one of the following values: 01944 * @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge 01945 * @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge 01946 * @param TIM5_IC2Polarity: Specifies the IC2 Polarity. 01947 * This parameter can be one of the following values: 01948 * @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge 01949 * @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge 01950 * @retval None 01951 */ 01952 void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode, 01953 TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, 01954 TIM5_ICPolarity_TypeDef TIM5_IC2Polarity) 01955 { 01956 uint8_t tmpsmcr = 0; 01957 uint8_t tmpccmr1 = 0; 01958 uint8_t tmpccmr2 = 0; 01959 01960 /* Check the parameters */ 01961 assert_param(IS_TIM5_ENCODER_MODE(TIM5_EncoderMode)); 01962 assert_param(IS_TIM5_IC_POLARITY(TIM5_IC1Polarity)); 01963 assert_param(IS_TIM5_IC_POLARITY(TIM5_IC2Polarity)); 01964 01965 tmpsmcr = TIM5->SMCR; 01966 tmpccmr1 = TIM5->CCMR1; 01967 tmpccmr2 = TIM5->CCMR2; 01968 01969 /* Set the encoder Mode */ 01970 tmpsmcr &= (uint8_t)(TIM_SMCR_MSM | TIM_SMCR_TS) ; 01971 tmpsmcr |= (uint8_t)TIM5_EncoderMode; 01972 01973 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ 01974 tmpccmr1 &= (uint8_t)(~TIM_CCMR_CCxS); 01975 tmpccmr2 &= (uint8_t)(~TIM_CCMR_CCxS); 01976 tmpccmr1 |= TIM_CCMR_TIxDirect_Set; 01977 tmpccmr2 |= TIM_CCMR_TIxDirect_Set; 01978 01979 /* Set the TI1 and the TI2 Polarities */ 01980 if (TIM5_IC1Polarity == TIM5_ICPolarity_Falling) 01981 { 01982 TIM5->CCER1 |= TIM_CCER1_CC1P ; 01983 } 01984 else 01985 { 01986 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P) ; 01987 } 01988 01989 if (TIM5_IC2Polarity == TIM5_ICPolarity_Falling) 01990 { 01991 TIM5->CCER1 |= TIM_CCER1_CC2P ; 01992 } 01993 else 01994 { 01995 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ; 01996 } 01997 01998 TIM5->SMCR = tmpsmcr; 01999 TIM5->CCMR1 = tmpccmr1; 02000 TIM5->CCMR2 = tmpccmr2; 02001 } 02002 02003 /** 02004 * @brief Enables or Disables the TIM�s Hall sensor interface. 02005 * @param NewState: The new state of the TIM5 Hall sensor interface. 02006 * This parameter can be ENABLE or DISABLE 02007 * @retval None 02008 */ 02009 void TIM5_SelectHallSensor(FunctionalState NewState) 02010 { 02011 /* Check the parameters */ 02012 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02013 02014 /* Set or Reset the TI1S Bit */ 02015 if (NewState != DISABLE) 02016 { 02017 TIM5->CR2 |= TIM_CR2_TI1S; 02018 } 02019 else 02020 { 02021 TIM5->CR2 &= (uint8_t)(~TIM_CR2_TI1S); 02022 } 02023 } 02024 02025 /** 02026 * @} 02027 */ 02028 02029 /** 02030 * @brief Configure the TI1 as Input. 02031 * @param TIM5_ICPolarity: Input Capture Polarity 02032 * This parameter can be one of the following values: 02033 * @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge 02034 * @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge 02035 * @param TIM5_ICSelection: Specifies the input to be used. 02036 * This parameter can be one of the following values: 02037 * @arg TIM5_ICSelection_DirectTI: Input Capture mapped on the direct input 02038 * @arg TIM5_ICSelection_IndirectTI: Input Capture mapped on the indirect input 02039 * @arg TIM5_ICSelection_TRGI: Input Capture mapped on the Trigger Input 02040 * @param TIM5_ICFilter: Specifies the Input Capture Filter. 02041 * This parameter must be a value between 0x00 and 0x0F. 02042 * @retval None 02043 */ 02044 static void TI1_Config(TIM5_ICPolarity_TypeDef TIM5_ICPolarity, \ 02045 TIM5_ICSelection_TypeDef TIM5_ICSelection, \ 02046 uint8_t TIM5_ICFilter) 02047 { 02048 uint8_t tmpccmr1 = 0; 02049 uint8_t tmpicpolarity = TIM5_ICPolarity; 02050 tmpccmr1 = TIM5->CCMR1; 02051 02052 /* Check the parameters */ 02053 assert_param(IS_TIM5_IC_POLARITY(TIM5_ICPolarity)); 02054 assert_param(IS_TIM5_IC_SELECTION(TIM5_ICSelection)); 02055 assert_param(IS_TIM5_IC_FILTER(TIM5_ICFilter)); 02056 02057 /* Disable the Channel 1: Reset the CCE Bit */ 02058 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1E); 02059 02060 /* Select the Input and set the filter */ 02061 tmpccmr1 &= (uint8_t)(~TIM_CCMR_CCxS) & (uint8_t)(~TIM_CCMR_ICxF); 02062 tmpccmr1 |= (uint8_t)(((uint8_t)(TIM5_ICSelection)) | ((uint8_t)(TIM5_ICFilter << 4))); 02063 02064 TIM5->CCMR1 = tmpccmr1; 02065 02066 /* Select the Polarity */ 02067 if (tmpicpolarity == (uint8_t)(TIM5_ICPolarity_Falling)) 02068 { 02069 TIM5->CCER1 |= TIM_CCER1_CC1P; 02070 } 02071 else 02072 { 02073 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC1P); 02074 } 02075 02076 /* Set the CCE Bit */ 02077 TIM5->CCER1 |= TIM_CCER1_CC1E; 02078 } 02079 02080 /** 02081 * @brief Configure the TI2 as Input. 02082 * @param TIM5_ICPolarity: Input Capture Polarity 02083 * This parameter can be one of the following values: 02084 * @arg TIM5_ICPolarity_Rising: Input Capture on Rising Edge 02085 * @arg TIM5_ICPolarity_Falling: Input Capture on Falling Edge 02086 * @param TIM5_ICSelection: Specifies the input to be used. 02087 * This parameter can be one of the following values: 02088 * @arg TIM5_ICSelection_DirectTI: Input Capture mapped on the direct input 02089 * @arg TIM5_ICSelection_IndirectTI: Input Capture mapped on the indirect input 02090 * @arg TIM5_ICSelection_TRGI: Input Capture mapped on the Trigger Input 02091 * @param TIM5_ICFilter: Specifies the Input Capture Filter. 02092 * This parameter must be a value between 0x00 and 0x0F. 02093 * @retval None 02094 */ 02095 static void TI2_Config(TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 02096 TIM5_ICSelection_TypeDef TIM5_ICSelection, 02097 uint8_t TIM5_ICFilter) 02098 { 02099 uint8_t tmpccmr2 = 0; 02100 uint8_t tmpicpolarity = TIM5_ICPolarity; 02101 02102 /* Check the parameters */ 02103 assert_param(IS_TIM5_IC_POLARITY(TIM5_ICPolarity)); 02104 assert_param(IS_TIM5_IC_SELECTION(TIM5_ICSelection)); 02105 assert_param(IS_TIM5_IC_FILTER(TIM5_ICFilter)); 02106 02107 tmpccmr2 = TIM5->CCMR2; 02108 02109 /* Disable the Channel 2: Reset the CCE Bit */ 02110 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2E); 02111 02112 /* Select the Input and set the filter */ 02113 tmpccmr2 &= (uint8_t)(~TIM_CCMR_CCxS) & (uint8_t)(~TIM_CCMR_ICxF); 02114 tmpccmr2 |= (uint8_t)(((uint8_t)(TIM5_ICSelection)) | ((uint8_t)(TIM5_ICFilter << 4))); 02115 02116 TIM5->CCMR2 = tmpccmr2; 02117 02118 /* Select the Polarity */ 02119 if (tmpicpolarity == TIM5_ICPolarity_Falling) 02120 { 02121 TIM5->CCER1 |= TIM_CCER1_CC2P ; 02122 } 02123 else 02124 { 02125 TIM5->CCER1 &= (uint8_t)(~TIM_CCER1_CC2P) ; 02126 } 02127 02128 /* Set the CCE Bit */ 02129 TIM5->CCER1 |= TIM_CCER1_CC2E; 02130 } 02131 02132 /** 02133 * @} 02134 */ 02135 02136 /** 02137 * @} 02138 */ 02139 02140 /** 02141 * @} 02142 */ 02143 02144 /** 02145 * @} 02146 */ 02147 02148 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/