STM8L15x Standard Peripherals Drivers
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stm8l15x_tim1.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_tim1.c 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file provides firmware functions to manage the following 00008 * functionalities of the TIM1 peripheral: 00009 * - TimeBase management 00010 * - Output Compare management 00011 * - Input Capture management 00012 * - Interrupts, DMA and flags management 00013 * - Clocks management 00014 * - Synchronization management 00015 * - Specific interface management 00016 * 00017 * @verbatim 00018 * 00019 * =================================================================== 00020 * How to use this driver 00021 * =================================================================== 00022 * This driver provides functions to configure and initialise the TIM1 00023 * peripheral 00024 * These functions are split in 7 groups: 00025 * 00026 * 1. TIM1 TimeBase management: this group includes all needed functions 00027 * to configure the TIM Timebase unit: 00028 * - Set/Get Prescaler 00029 * - Set/Get Autoreload 00030 * - Counter modes configuration 00031 * - Select the One Pulse mode 00032 * - Update Request Configuration 00033 * - Update Disable Configuration 00034 * - Auto-Preload Configuration 00035 * - Enable/Disable the counter 00036 * 00037 * 2. TIM1 Output Compare management: this group includes all needed 00038 * functions to configure the Capture/Compare unit used in Output 00039 * compare mode: 00040 * - Configure each channel, independently, in Output Compare mode 00041 * - Select the output compare modes 00042 * - Select the Polarities of each channel 00043 * - Set/Get the Capture/Compare register values 00044 * - Select the Output Compare Fast mode 00045 * - Select the Output Compare Forced mode 00046 * - Output Compare-Preload Configuration 00047 * - Clear Output Compare Reference 00048 * - Select the OCREF Clear signal 00049 * - Enable/Disable the Capture/Compare Channels 00050 * 00051 * 3. TIM1 Input Capture management: this group includes all needed 00052 * functions to configure the Capture/Compare unit used in 00053 * Input Capture mode: 00054 * - Configure each channel in input capture mode 00055 * - Configure Channel1/2 in PWM Input mode 00056 * - Set the Input Capture Prescaler 00057 * - Get the Capture/Compare values 00058 * 00059 * 4. TIM1 interrupts, DMA and flags management 00060 * - Enable/Disable interrupt sources 00061 * - Get flags status 00062 * - Clear flags/ Pending bits 00063 * - Enable/Disable DMA requests 00064 * - Configure DMA burst mode 00065 * - Select CaptureCompare DMA request 00066 * 00067 * 5. TIM1 clocks management: this group includes all needed functions 00068 * to configure the clock controller unit: 00069 * - Select internal/External clock 00070 * - Select the external clock mode: ETR(Mode1/Mode2) or TIx 00071 * 00072 * 6. TIM1 synchronization management: this group includes all needed 00073 * functions to configure the Synchronization unit: 00074 * - Select Input Trigger 00075 * - Select Output Trigger 00076 * - Select Master Slave Mode 00077 * - ETR Configuration when used as external trigger 00078 * 00079 * 7. TIM1 specific interface management, this group includes all 00080 * needed functions to use the specific TIM1 interface: 00081 * - Encoder Interface Configuration 00082 * - Select Hall Sensor 00083 * 00084 * @endverbatim 00085 * 00086 ****************************************************************************** 00087 * @attention 00088 * 00089 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00090 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00091 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00092 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00093 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00094 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00095 * 00096 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00097 ****************************************************************************** 00098 */ 00099 00100 /* Includes ------------------------------------------------------------------*/ 00101 #include "stm8l15x_tim1.h" 00102 00103 /** @addtogroup STM8L15x_StdPeriph_Driver 00104 * @{ 00105 */ 00106 00107 /** @defgroup TIM1 00108 * @brief TIM1 driver modules 00109 * @{ 00110 */ 00111 00112 /* Private typedef -----------------------------------------------------------*/ 00113 /* Private define ------------------------------------------------------------*/ 00114 /* Private macro -------------------------------------------------------------*/ 00115 /* Private variables ---------------------------------------------------------*/ 00116 /* Private function prototypes -----------------------------------------------*/ 00117 /** @defgroup TIM1_Private_Functions_Prototypes 00118 * @{ 00119 */ 00120 00121 static void TI1_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, 00122 uint8_t TIM1_ICFilter); 00123 static void TI2_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, 00124 uint8_t TIM1_ICFilter); 00125 static void TI3_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, 00126 uint8_t TIM1_ICFilter); 00127 static void TI4_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, 00128 uint8_t TIM1_ICFilter); 00129 00130 /** 00131 * @} 00132 */ 00133 00134 /* Private functions ---------------------------------------------------------*/ 00135 /** @defgroup TIM1_Private_Functions 00136 * @{ 00137 */ 00138 00139 /** @defgroup TIM1_Group1 TimeBase management functions 00140 * @brief TimeBase management functions 00141 * 00142 @verbatim 00143 =============================================================================== 00144 TimeBase management functions 00145 =============================================================================== 00146 00147 =================================================================== 00148 TIM1 Driver: how to use it in Timing(Time base) Mode 00149 =================================================================== 00150 To use the Timer in Timing(Time base) mode, the following steps are mandatory: 00151 00152 1. Enable TIM1 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM1, ENABLE) function. 00153 00154 2. Call TIM1_TimeBaseInit() to configure the Time Base unit with the 00155 corresponding configuration. 00156 00157 3. Enable global interrupts if you need to generate the update interrupt. 00158 00159 4. Enable the corresponding interrupt using the function TIM1_ITConfig(TIM1_IT_Update) 00160 00161 5. Call the TIM1_Cmd(ENABLE) function to enable the TIM1 counter. 00162 00163 Note1: All other functions can be used separately to modify, if needed, 00164 a specific feature of the Timer. 00165 00166 @endverbatim 00167 * @{ 00168 */ 00169 00170 /** 00171 * @brief Deinitializes the TIM1 peripheral registers to their default reset values. 00172 * @param None 00173 * @retval None 00174 */ 00175 void TIM1_DeInit(void) 00176 { 00177 TIM1->CR1 = TIM1_CR1_RESET_VALUE; 00178 TIM1->CR2 = TIM1_CR2_RESET_VALUE; 00179 TIM1->SMCR = TIM1_SMCR_RESET_VALUE; 00180 TIM1->ETR = TIM1_ETR_RESET_VALUE; 00181 TIM1->IER = TIM1_IER_RESET_VALUE; 00182 00183 /* Disable channels */ 00184 TIM1->CCER1 = TIM1_CCER1_RESET_VALUE; 00185 TIM1->CCER2 = TIM1_CCER2_RESET_VALUE; 00186 /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */ 00187 TIM1->CCMR1 = 0x01; 00188 TIM1->CCMR2 = 0x01; 00189 TIM1->CCMR3 = 0x01; 00190 TIM1->CCMR4 = 0x01; 00191 /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */ 00192 TIM1->CCER1 = TIM1_CCER1_RESET_VALUE; 00193 TIM1->CCER2 = TIM1_CCER2_RESET_VALUE; 00194 TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE; 00195 TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE; 00196 TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE; 00197 TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE; 00198 TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE; 00199 TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE; 00200 TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE; 00201 TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE; 00202 TIM1->ARRH = TIM1_ARRH_RESET_VALUE; 00203 TIM1->ARRL = TIM1_ARRL_RESET_VALUE; 00204 TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE; 00205 TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE; 00206 TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE; 00207 TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE; 00208 TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE; 00209 TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE; 00210 TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE; 00211 TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE; 00212 TIM1->OISR = TIM1_OISR_RESET_VALUE; 00213 TIM1->EGR = 0x01; /* TIM1_EGR_UG */ 00214 TIM1->DTR = TIM1_DTR_RESET_VALUE; 00215 TIM1->BKR = TIM1_BKR_RESET_VALUE; 00216 TIM1->RCR = TIM1_RCR_RESET_VALUE; 00217 TIM1->SR1 = TIM1_SR1_RESET_VALUE; 00218 TIM1->SR2 = TIM1_SR2_RESET_VALUE; 00219 } 00220 00221 /** 00222 * @brief Initializes the TIM1 Time Base Unit according to the specified parameters. 00223 * @param TIM1_Prescaler specifies the Prescaler value. 00224 * @param TIM1_CounterMode specifies the counter mode from 00225 * This parameter can be one of the following values: 00226 * @arg TIM1_CounterMode_Up: Counter mode Up 00227 * @arg TIM1_CounterMode_Down: Counter mode Down 00228 * @arg TIM1_CounterMode_CenterAligned1: Counter mode center aligned 00229 * @arg TIM1_CounterMode_CenterAligned2: Counter mode center aligned 00230 * @arg TIM1_CounterMode_CenterAligned3: Counter mode center aligned 00231 * @param TIM1_Period specifies the Period value. 00232 * @param TIM1_RepetitionCounter specifies the Repetition counter value 00233 * @retval None 00234 */ 00235 void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler, 00236 TIM1_CounterMode_TypeDef TIM1_CounterMode, 00237 uint16_t TIM1_Period, 00238 uint8_t TIM1_RepetitionCounter) 00239 { 00240 /* Check parameters */ 00241 assert_param(IS_TIM1_COUNTER_MODE(TIM1_CounterMode)); 00242 00243 00244 /* Set the Autoreload value */ 00245 TIM1->ARRH = (uint8_t)(TIM1_Period >> 8); 00246 TIM1->ARRL = (uint8_t)(TIM1_Period); 00247 00248 /* Set the Prescaler value */ 00249 TIM1->PSCRH = (uint8_t)(TIM1_Prescaler >> 8); 00250 TIM1->PSCRL = (uint8_t)(TIM1_Prescaler); 00251 00252 /* Select the Counter Mode */ 00253 TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)(~(TIM1_CR1_CMS | TIM1_CR1_DIR))) 00254 | (uint8_t)(TIM1_CounterMode)); 00255 00256 /* Set the Repetition Counter value */ 00257 TIM1->RCR = TIM1_RepetitionCounter; 00258 00259 } 00260 00261 /** 00262 * @brief Configures the TIM1 Prescaler. 00263 * @param Prescaler specifies the Prescaler Register value 00264 * This parameter must be a value between 0x0000 and 0xFFFF 00265 * @param TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode. 00266 * This parameter can be one of the following values 00267 * @arg TIM1_PSCReloadMode_Immediate: The Prescaler is loaded immediately. 00268 * @arg TIM1_PSCReloadMode_Update: The Prescaler is loaded at the update 00269 * event. 00270 * @retval None 00271 */ 00272 00273 void TIM1_PrescalerConfig(uint16_t Prescaler, TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode) 00274 { 00275 /* Check the parameters */ 00276 assert_param(IS_TIM1_PRESCALER_RELOAD(TIM1_PSCReloadMode)); 00277 00278 /* Set the Prescaler value */ 00279 TIM1->PSCRH = (uint8_t)(Prescaler >> 8); 00280 TIM1->PSCRL = (uint8_t)(Prescaler); 00281 00282 /* Set or reset the UG Bit */ 00283 TIM1->EGR = (uint8_t)TIM1_PSCReloadMode; 00284 } 00285 00286 /** 00287 * @brief Specifies the TIM1 Counter Mode to be used. 00288 * @param TIM1_CounterMode specifies the Counter Mode to be used 00289 * This parameter can be one of the following values: 00290 * @arg TIM1_CounterMode_Up: TIM1 Up Counting Mode 00291 * @arg TIM1_CounterMode_Down: TIM1 Down Counting Mode 00292 * @arg TIM1_CounterMode_CenterAligned1: TIM1 Center Aligned Mode1 00293 * @arg TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2 00294 * @arg IM1_CounterMode_CenterAligned3: TIM1 Center Aligned Mode3 00295 * @retval None 00296 */ 00297 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode) 00298 { 00299 /* Check the parameters */ 00300 assert_param(IS_TIM1_COUNTER_MODE(TIM1_CounterMode)); 00301 00302 00303 /* Reset the CMS and DIR Bits & Set the Counter Mode */ 00304 TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)((uint8_t)(~TIM1_CR1_CMS) & (uint8_t)(~TIM1_CR1_DIR))) 00305 | (uint8_t)TIM1_CounterMode); 00306 } 00307 00308 /** 00309 * @brief Sets the TIM1 Counter Register value. 00310 * @param Counter specifies the Counter register new value. 00311 * This parameter is between 0x0000 and 0xFFFF. 00312 * @retval None 00313 */ 00314 void TIM1_SetCounter(uint16_t Counter) 00315 { 00316 /* Set the Counter Register value */ 00317 TIM1->CNTRH = (uint8_t)(Counter >> 8); 00318 TIM1->CNTRL = (uint8_t)(Counter); 00319 } 00320 00321 /** 00322 * @brief Sets the TIM1 Autoreload Register value. 00323 * @param Autoreload specifies the Autoreload register new value. 00324 * This parameter is between 0x0000 and 0xFFFF. 00325 * @retval None 00326 */ 00327 void TIM1_SetAutoreload(uint16_t Autoreload) 00328 { 00329 /* Set the Autoreload Register value */ 00330 TIM1->ARRH = (uint8_t)(Autoreload >> 8); 00331 TIM1->ARRL = (uint8_t)(Autoreload); 00332 } 00333 00334 /** 00335 * @brief Gets the TIM1 Counter value. 00336 * @param None 00337 * @retval Counter Register value. 00338 */ 00339 uint16_t TIM1_GetCounter(void) 00340 { 00341 /* Get the Counter Register value */ 00342 uint16_t tmpcntr = 0; 00343 uint8_t tmpcntrl = 0, tmpcntrh = 0; 00344 00345 tmpcntrh = TIM1->CNTRH; 00346 tmpcntrl = TIM1->CNTRL; 00347 00348 tmpcntr = (uint16_t)(tmpcntrl); 00349 tmpcntr |= (uint16_t)((uint16_t)tmpcntrh << 8); 00350 00351 /* Get the Counter Register value */ 00352 return (uint16_t)tmpcntr; 00353 } 00354 00355 /** 00356 * @brief Gets the TIM1 Prescaler value. 00357 * @param None 00358 * @retval Prescaler Register value. 00359 */ 00360 uint16_t TIM1_GetPrescaler(void) 00361 { 00362 uint16_t tmpreg = 0; 00363 tmpreg = (uint16_t)((uint16_t)TIM1->PSCRH << 8); 00364 /* Get the Prescaler Register value */ 00365 return (uint16_t)(tmpreg | TIM1->PSCRL); 00366 } 00367 00368 /** 00369 * @brief Enables or Disables the TIM1 Update event. 00370 * @param NewState new state of the TIM1 peripheral Preload register. 00371 * This parameter can be ENABLE or DISABLE. 00372 * @retval None 00373 */ 00374 void TIM1_UpdateDisableConfig(FunctionalState NewState) 00375 { 00376 /* Check the parameters */ 00377 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00378 00379 /* Set or Reset the UDIS Bit */ 00380 if (NewState != DISABLE) 00381 { 00382 TIM1->CR1 |= TIM1_CR1_UDIS; 00383 } 00384 else 00385 { 00386 TIM1->CR1 &= (uint8_t)(~TIM1_CR1_UDIS); 00387 } 00388 } 00389 00390 /** 00391 * @brief Selects the TIM1 Update Request Interrupt source. 00392 * @param TIM1_UpdateSource specifies the Update source. 00393 * This parameter can be one of the following values 00394 * @arg TIM1_UpdateSource_Regular 00395 * @arg TIM1_UpdateSource_Global 00396 * @retval None 00397 */ 00398 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource) 00399 { 00400 /* Check the parameters */ 00401 assert_param(IS_TIM1_UPDATE_SOURCE(TIM1_UpdateSource)); 00402 00403 /* Set or Reset the URS Bit */ 00404 if (TIM1_UpdateSource != TIM1_UpdateSource_Global) 00405 { 00406 TIM1->CR1 |= TIM1_CR1_URS; 00407 } 00408 else 00409 { 00410 TIM1->CR1 &= (uint8_t)(~TIM1_CR1_URS); 00411 } 00412 } 00413 00414 /** 00415 * @brief Enables or disables TIM1 peripheral Preload register on ARR. 00416 * @param NewState new state of the TIM1 peripheral Preload register. 00417 * This parameter can be ENABLE or DISABLE. 00418 * @retval None 00419 */ 00420 void TIM1_ARRPreloadConfig(FunctionalState NewState) 00421 { 00422 /* Check the parameters */ 00423 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00424 00425 /* Set or Reset the ARPE Bit */ 00426 if (NewState != DISABLE) 00427 { 00428 TIM1->CR1 |= TIM1_CR1_ARPE; 00429 } 00430 else 00431 { 00432 TIM1->CR1 &= (uint8_t)(~TIM1_CR1_ARPE); 00433 } 00434 } 00435 00436 /** 00437 * @brief Selects the TIM1�s One Pulse Mode. 00438 * @param TIM1_OPMode specifies the OPM Mode to be used. 00439 * This parameter can be one of the following values 00440 * @arg TIM1_OPMode_Single 00441 * @arg TIM1_OPMode_Repetitive 00442 * @retval None 00443 */ 00444 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode) 00445 { 00446 /* Check the parameters */ 00447 assert_param(IS_TIM1_OPM_MODE(TIM1_OPMode)); 00448 00449 /* Set or Reset the OPM Bit */ 00450 if (TIM1_OPMode != TIM1_OPMode_Repetitive) 00451 { 00452 TIM1->CR1 |= TIM1_CR1_OPM; 00453 } 00454 else 00455 { 00456 TIM1->CR1 &= (uint8_t)(~TIM1_CR1_OPM); 00457 } 00458 } 00459 00460 /** 00461 * @brief Enables or disables the TIM1 peripheral. 00462 * @param NewState new state of the TIM1 peripheral. 00463 * This parameter can be ENABLE or DISABLE. 00464 * @retval None 00465 */ 00466 void TIM1_Cmd(FunctionalState NewState) 00467 { 00468 /* Check the parameters */ 00469 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00470 00471 /* set or Reset the CEN Bit */ 00472 if (NewState != DISABLE) 00473 { 00474 TIM1->CR1 |= TIM1_CR1_CEN; 00475 } 00476 else 00477 { 00478 TIM1->CR1 &= (uint8_t)(~TIM1_CR1_CEN); 00479 } 00480 } 00481 00482 /** 00483 * @} 00484 */ 00485 00486 /** @defgroup TIM1_Group2 Output Compare management functions 00487 * @brief Output Compare management functions 00488 * 00489 @verbatim 00490 =============================================================================== 00491 Output Compare management functions 00492 =============================================================================== 00493 00494 =================================================================== 00495 TIM1 Driver: how to use it in Output Compare Mode 00496 =================================================================== 00497 To use the Timer in Output Compare mode, the following steps are mandatory: 00498 00499 1. Enable TIM1 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM1, ENABLE) function. 00500 00501 2. Configure the TIM1 pins in output mode by configuring the corresponding GPIO pins 00502 00503 3. Configure the Time base unit as described in the first part of this driver, if needed, 00504 otherwise the Timer will run with the default configuration: 00505 - Autoreload value = 0xFFFF 00506 - Prescaler value = 0x0000 00507 - Counter mode = Up counting 00508 00509 4. Call TIM1_OCxInit() to configure the channel x with the desired parameters 00510 including: 00511 - TIM1 Output Compare mode: TIM1_OCMode 00512 - TIM1 Output State: TIM1_OutputState 00513 - TIM1 Complementary Output State: TIM1_OutputNState 00514 - TIM1 Pulse value: TIM1_Pulse 00515 - TIM1 Output Compare Polarity : TIM1_OCPolarity 00516 - TIM1 Complementary Output Compare Polarity : TIM1_OCNPolarity 00517 - TIM1 Output Idle State: TIM1_OCIdleState 00518 - TIM1 Complementary Output Idle State: TIM1_OCNIdleState 00519 00520 5. Call the TIM1_Cmd(ENABLE) function to enable the TIM1 counter. 00521 00522 Note1: All other functions can be used separately to modify, if needed, 00523 a specific feature of the Timer. 00524 00525 Note2: If the corresponding interrupt or DMA request are needed, the user should: 00526 1. Enable global interrupts (or the DMA) to use the TIM1 interrupts (or DMA requests). 00527 2. Enable the corresponding interrupt (or DMA request) using the function 00528 TIM1_ITConfig(TIM1_IT_CCx) (or TIM1_DMACmd(TIM1_DMASource_CCx)) 00529 00530 @endverbatim 00531 * @{ 00532 */ 00533 00534 /** 00535 * @brief Initializes the TIM1 Channel1 according to the specified parameters. 00536 * @param TIM1_OCMode specifies the Output Compare mode 00537 * This parameter can be one of the following values: 00538 * @arg TIM1_OCMode_Timing: OC Mode Timing 00539 * @arg TIM1_OCMode_Active: OC Mode Active 00540 * @arg TIM1_OCMode_Inactive: OC Mode Inactive 00541 * @arg TIM1_OCMode_Toggle: OC Mode Toggle 00542 * @arg TIM1_OCMode_PWM1: OC Mode PWM1 00543 * @arg TIM1_OCMode_PWM2: OC Mode PWM2 00544 * @param TIM1_OutputState specifies the Output State 00545 * This parameter can be one of the following values: 00546 * @arg TIM1_OutputState_Disable: Output state disable 00547 * @arg TIM1_OutputState_Enable: Output state enable 00548 * @param TIM1_OutputNState specifies the Complementary Output State 00549 * This parameter can be one of the following values: 00550 * @arg TIM1_OutputNState_Disable: Output N state disable 00551 * @arg TIM1_OutputNState_Enable: Output N state enable 00552 * @param TIM1_Pulse specifies the Pulse width value. 00553 * @param TIM1_OCPolarity specifies the Output Compare Polarity 00554 * This parameter can be one of the following values: 00555 * @arg TIM1_OCPolarity_High: Output Compare active low 00556 * @arg TIM1_OCPolarity_Low: Output Compare active high 00557 * @param TIM1_OCNPolarity specifies the Complementary Output Compare Polarity 00558 * This parameter can be one of the following values: 00559 * @arg TIM1_OCNPolarity_High: Complementary Output Compare active low 00560 * @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high 00561 * @param TIM1_OCIdleState specifies the Output Compare Idle State 00562 * This parameter can be one of the following values: 00563 * @arg TIM1_OCIdleState_Set: Output Compare Idle state set 00564 * @arg TIM1_OCIdleState_Reset: Output Compare Idle state reset 00565 * @param TIM1_OCNIdleState specifies the Complementary Output Compare Idle State 00566 * This parameter can be one of the following values: 00567 * @arg TIM1_OCNIdleState_Set: Complementary Output Compare Idle state set 00568 * @arg TIM1_OCNIdleState_Reset: Complementary Output Compare Idle state reset 00569 * @retval None 00570 */ 00571 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode, 00572 TIM1_OutputState_TypeDef TIM1_OutputState, 00573 TIM1_OutputNState_TypeDef TIM1_OutputNState, 00574 uint16_t TIM1_Pulse, 00575 TIM1_OCPolarity_TypeDef TIM1_OCPolarity, 00576 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, 00577 TIM1_OCIdleState_TypeDef TIM1_OCIdleState, 00578 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState) 00579 { 00580 /* Check the parameters */ 00581 assert_param(IS_TIM1_OC_MODE(TIM1_OCMode)); 00582 assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OutputState)); 00583 assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OutputNState)); 00584 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); 00585 assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity)); 00586 assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCIdleState)); 00587 assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCNIdleState)); 00588 00589 /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , 00590 the Output N State, the Output Polarity & the Output N Polarity*/ 00591 TIM1->CCER1 &= (uint8_t)(~(TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE 00592 | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP)); 00593 /* Set the Output State & Set the Output N State & Set the Output Polarity 00594 & Set the Output N Polarity */ 00595 TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC1E) 00596 | (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC1NE)) 00597 | (uint8_t)( (uint8_t)(TIM1_OCPolarity & TIM1_CCER1_CC1P) 00598 | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC1NP))); 00599 00600 /* Reset the Output Compare Bits & Set the Output Compare Mode */ 00601 TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) 00602 | (uint8_t)TIM1_OCMode); 00603 00604 /* Reset the Output Idle state & the Output N Idle state bits */ 00605 TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N)); 00606 /* Set the Output Idle state & the Output N Idle state configuration */ 00607 TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OCIdleState & TIM1_OISR_OIS1) 00608 | (uint8_t)(TIM1_OCNIdleState & TIM1_OISR_OIS1N)); 00609 00610 /* Set the Pulse value */ 00611 TIM1->CCR1H = (uint8_t)(TIM1_Pulse >> 8); 00612 TIM1->CCR1L = (uint8_t)(TIM1_Pulse); 00613 } 00614 00615 /** 00616 * @brief Initializes the TIM1 Channel2 according to the specified parameters. 00617 * @param TIM1_OCMode specifies the Output Compare mode 00618 * This parameter can be one of the following values: 00619 * @arg TIM1_OCMode_Timing: OC Mode Timing 00620 * @arg TIM1_OCMode_Active: OC Mode Active 00621 * @arg TIM1_OCMode_Inactive: OC Mode Inactive 00622 * @arg TIM1_OCMode_Toggle: OC Mode Toggle 00623 * @arg TIM1_OCMode_PWM1: OC Mode PWM1 00624 * @arg TIM1_OCMode_PWM2: OC Mode PWM2 00625 * @param TIM1_OutputState specifies the Output State 00626 * This parameter can be one of the following values: 00627 * @arg TIM1_OutputState_Disable: Output state disable 00628 * @arg TIM1_OutputState_Enable: Output state enable 00629 * @param TIM1_OutputNState specifies the Complementary Output State 00630 * This parameter can be one of the following values: 00631 * @arg TIM1_OutputNState_Disable: Output N state disable 00632 * @arg TIM1_OutputNState_Enable: Output N state enable 00633 * @param TIM1_Pulse specifies the Pulse width value. 00634 * @param TIM1_OCPolarity specifies the Output Compare Polarity 00635 * This parameter can be one of the following values: 00636 * @arg TIM1_OCPolarity_High: Output Compare active low 00637 * @arg TIM1_OCPolarity_Low: Output Compare active high 00638 * @param TIM1_OCNPolarity specifies the Complementary Output Compare 00639 * This parameter can be one of the following values: 00640 * @arg TIM1_OCNPolarity_High: Complementary Output Compare active low 00641 * @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high 00642 * @param TIM1_OCIdleState specifies the Output Compare Idle State 00643 * This parameter can be one of the following values: 00644 * @arg TIM1_OCIdleState_Set: Output Compare Idle state set 00645 * @arg TIM1_OCIdleState_Reset: Output Compare Idle state reset 00646 * @param TIM1_OCNIdleState specifies the Complementary Output Compare Idle State 00647 * This parameter can be one of the following values: 00648 * @arg TIM1_OCNIdleState_Set: Complementary Output Compare Idle state set 00649 * @arg TIM1_OCNIdleState_Reset: Complementary Output Compare Idle state reset 00650 * @retval None 00651 */ 00652 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode, 00653 TIM1_OutputState_TypeDef TIM1_OutputState, 00654 TIM1_OutputNState_TypeDef TIM1_OutputNState, 00655 uint16_t TIM1_Pulse, 00656 TIM1_OCPolarity_TypeDef TIM1_OCPolarity, 00657 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, 00658 TIM1_OCIdleState_TypeDef TIM1_OCIdleState, 00659 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState) 00660 { 00661 00662 /* Check the parameters */ 00663 assert_param(IS_TIM1_OC_MODE(TIM1_OCMode)); 00664 assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OutputState)); 00665 assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OutputNState)); 00666 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); 00667 assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity)); 00668 assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCIdleState)); 00669 assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCNIdleState)); 00670 00671 /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, 00672 the Output N State, the Output Polarity & the Output N Polarity*/ 00673 TIM1->CCER1 &= (uint8_t)(~(TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE | TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP)); 00674 00675 /* Set the Output State & Set the Output N State & Set the Output Polarity & Set the Output N Polarity */ 00676 TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC2E) | (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC2NE)) 00677 | (uint8_t) ((uint8_t)(TIM1_OCPolarity & TIM1_CCER1_CC2P) | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC2NP))); 00678 00679 /* Reset the Output Compare Bits & Set the Output Compare Mode */ 00680 TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode); 00681 00682 /* Reset the Output Idle state & the Output N Idle state bits */ 00683 TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N)); 00684 /* Set the Output Idle state & the Output N Idle state configuration */ 00685 TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS2 & TIM1_OCIdleState) | (uint8_t)(TIM1_OISR_OIS2N & TIM1_OCNIdleState)); 00686 00687 /* Set the Pulse value */ 00688 TIM1->CCR2H = (uint8_t)(TIM1_Pulse >> 8); 00689 TIM1->CCR2L = (uint8_t)(TIM1_Pulse); 00690 } 00691 00692 /** 00693 * @brief Initializes the TIM1 Channel3 according to the specified parameters. 00694 * @param TIM1_OCMode specifies the Output Compare mode 00695 * This parameter can be one of the following values: 00696 * @arg TIM1_OCMode_Timing: OC Mode Timing 00697 * @arg TIM1_OCMode_Active: OC Mode Active 00698 * @arg TIM1_OCMode_Inactive: OC Mode Inactive 00699 * @arg TIM1_OCMode_Toggle: OC Mode Toggle 00700 * @arg TIM1_OCMode_PWM1: OC Mode PWM1 00701 * @arg TIM1_OCMode_PWM2: OC Mode PWM2 00702 * @param TIM1_OutputState specifies the Output State 00703 * This parameter can be one of the following values: 00704 * @arg TIM1_OutputState_Disable: Output state disable 00705 * @arg TIM1_OutputState_Enable: Output state enable 00706 * @param TIM1_OutputNState specifies the Complementary Output State 00707 * This parameter can be one of the following values: 00708 * @arg TIM1_OutputNState_Disable: Output N state disable 00709 * @arg TIM1_OutputNState_Enable: Output N state enable 00710 * @param TIM1_Pulse specifies the Pulse width value. 00711 * @param TIM1_OCPolarity specifies the Output Compare Polarity 00712 * This parameter can be one of the following values: 00713 * @arg TIM1_OCPolarity_High: Output Compare active low 00714 * @arg TIM1_OCPolarity_Low: Output Compare active high 00715 * @param TIM1_OCNPolarity specifies the Complementary Output Compare Polarity 00716 * This parameter can be one of the following values: 00717 * @arg TIM1_OCNPolarity_High: Complementary Output Compare active low 00718 * @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high 00719 * @param TIM1_OCIdleState specifies the Output Compare Idle State 00720 * This parameter can be one of the following values: 00721 * @arg TIM1_OCIdleState_Set: Output Compare Idle state set 00722 * @arg TIM1_OCIdleState_Reset: Output Compare Idle state reset 00723 * @param TIM1_OCNIdleState specifies the Complementary Output Compare Idle State 00724 * This parameter can be one of the following values: 00725 * @arg TIM1_OCNIdleState_Set: Complementary Output Compare Idle state set 00726 * @arg TIM1_OCNIdleState_Reset: Complementary Output Compare Idle state reset 00727 * @retval None 00728 */ 00729 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode, 00730 TIM1_OutputState_TypeDef TIM1_OutputState, 00731 TIM1_OutputNState_TypeDef TIM1_OutputNState, 00732 uint16_t TIM1_Pulse, 00733 TIM1_OCPolarity_TypeDef TIM1_OCPolarity, 00734 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, 00735 TIM1_OCIdleState_TypeDef TIM1_OCIdleState, 00736 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState) 00737 { 00738 00739 /* Check the parameters */ 00740 assert_param(IS_TIM1_OC_MODE(TIM1_OCMode)); 00741 assert_param(IS_TIM1_OUTPUT_STATE(TIM1_OutputState)); 00742 assert_param(IS_TIM1_OUTPUTN_STATE(TIM1_OutputNState)); 00743 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); 00744 assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity)); 00745 assert_param(IS_TIM1_OCIDLE_STATE(TIM1_OCIdleState)); 00746 assert_param(IS_TIM1_OCNIDLE_STATE(TIM1_OCNIdleState)); 00747 00748 /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, 00749 the Output N State, the Output Polarity & the Output N Polarity */ 00750 TIM1->CCER2 &= (uint8_t)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP)); 00751 00752 /* Set the Output State & Set the Output N State & Set the Output Polarity & Set the Output N Polarity */ 00753 TIM1->CCER2 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER2_CC3E) | (uint8_t)(TIM1_OutputNState & TIM1_CCER2_CC3NE)) 00754 | (uint8_t)((uint8_t)(TIM1_OCPolarity & TIM1_CCER2_CC3P) | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER2_CC3NP))); 00755 00756 /* Reset the Output Compare Bits & Set the Output Compare Mode */ 00757 TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode); 00758 00759 /* Reset the Output Idle state & the Output N Idle state bits */ 00760 TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N)); 00761 /* Set the Output Idle state & the Output N Idle state configuration */ 00762 TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS3 & TIM1_OCIdleState) | (uint8_t) (TIM1_OISR_OIS3N & TIM1_OCNIdleState)); 00763 00764 /* Set the Pulse value */ 00765 TIM1->CCR3H = (uint8_t)(TIM1_Pulse >> 8); 00766 TIM1->CCR3L = (uint8_t)(TIM1_Pulse); 00767 } 00768 00769 /** 00770 * @brief Configures the Break feature, dead time, Lock level, the OSSI, 00771 * and the AOE(automatic output enable). 00772 * @param TIM1_OSSIState specifies the OSSIS State 00773 * This parameter can be one of the following values: 00774 * @arg TIM1_OSSIState_Enable: OSSIS State enabled 00775 * @arg TIM1_OSSIState_Disable: OSSIS State disabled 00776 * @param TIM1_LockLevel specifies the lock level 00777 * This parameter can be one of the following values: 00778 * @arg TIM1_LockLevel_Off: No lock level 00779 * @arg TIM1_LockLevel_1: Lock level 1 00780 * @arg TIM1_LockLevel_2: Lock level 2 00781 * @arg TIM1_LockLevel_3: Lock level 3 00782 * @param TIM1_DeadTime specifies the dead time value. 00783 * @param TIM1_Break specifies the Break state 00784 * This parameter can be one of the following values: 00785 * @arg TIM1_BreakState_Enable: Break enabled 00786 * @arg TIM1_BreakState_Disable: Break disabled 00787 * @param TIM1_BreakPolarity specifies the Break polarity 00788 * This parameter can be one of the following values: 00789 * @arg TIM1_BreakPolarity_Low: Break polarity high 00790 * @arg TIM1_BreakPolarity_High: Break polarity low 00791 * @param TIM1_AutomaticOutput specifies the Automatic Output configuration 00792 * This parameter can be one of the following values: 00793 * @arg TIM1_AutomaticOutput_Enable: Automatic Output enabled 00794 * @arg TIM1_AutomaticOutput_Disable: Automatic Output disabled 00795 * @retval None 00796 */ 00797 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState, 00798 TIM1_LockLevel_TypeDef TIM1_LockLevel, 00799 uint8_t TIM1_DeadTime, 00800 TIM1_BreakState_TypeDef TIM1_Break, 00801 TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, 00802 TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput) 00803 { 00804 00805 /* Check the parameters */ 00806 assert_param(IS_TIM1_OSSI_STATE(TIM1_OSSIState)); 00807 assert_param(IS_TIM1_LOCK_LEVEL(TIM1_LockLevel)); 00808 assert_param(IS_TIM1_BREAK_STATE(TIM1_Break)); 00809 assert_param(IS_TIM1_BREAK_POLARITY(TIM1_BreakPolarity)); 00810 assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE(TIM1_AutomaticOutput)); 00811 00812 TIM1->DTR = (uint8_t)(TIM1_DeadTime); 00813 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSI State, 00814 the dead time value and the Automatic Output Enable Bit */ 00815 00816 TIM1->BKR = (uint8_t)((uint8_t)((uint8_t)TIM1_OSSIState | (uint8_t)TIM1_LockLevel) 00817 | (uint8_t)((uint8_t)((uint8_t)TIM1_Break | (uint8_t)TIM1_BreakPolarity) 00818 | (uint8_t)TIM1_AutomaticOutput)); 00819 00820 } 00821 00822 /** 00823 * @brief Enables or disables the TIM1 peripheral Main Outputs. 00824 * @param NewState new state of the TIM1 peripheral. 00825 * This parameter can be ENABLE or DISABLE. 00826 * @retval None 00827 */ 00828 void TIM1_CtrlPWMOutputs(FunctionalState NewState) 00829 { 00830 /* Check the parameters */ 00831 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00832 00833 /* Set or Reset the MOE Bit */ 00834 00835 if (NewState != DISABLE) 00836 { 00837 TIM1->BKR |= TIM1_BKR_MOE; 00838 } 00839 else 00840 { 00841 TIM1->BKR &= (uint8_t)(~TIM1_BKR_MOE); 00842 } 00843 } 00844 00845 /** 00846 * @brief Selects the TIM1 Output Compare Mode. This function disables the 00847 * selected channel before changing the Output Compare Mode. 00848 * @note User has to enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions. 00849 * @param TIM1_Channel specifies the TIM1 Channel. 00850 * This parameter can be one of the following values: 00851 * @arg TIM1_Channel_1: TIM1 Channel1 00852 * @arg TIM1_Channel_2: TIM1 Channel2 00853 * @arg TIM1_Channel_3: TIM1 Channel3 00854 * @arg TIM1_Channel_4: TIM1 Channel4 00855 * @param TIM1_OCMode specifies the TIM1 Output Compare Mode. 00856 * This parameter can be one of the following values: 00857 * @arg TIM1_OCMode_Timing: OC Mode Timing 00858 * @arg TIM1_OCMode_Active: OC Mode Active 00859 * @arg TIM1_OCMode_Inactive: OC Mode Inactive 00860 * @arg TIM1_OCMode_Toggle: OC Mode Toggle 00861 * @arg TIM1_OCMode_PWM1: OC Mode PWM1 00862 * @arg TIM1_OCMode_PWM2: OC Mode PWM2 00863 * @retval None 00864 */ 00865 void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode) 00866 { 00867 /* Check the parameters */ 00868 assert_param(IS_TIM1_CHANNEL(TIM1_Channel)); 00869 assert_param(IS_TIM1_OCM(TIM1_OCMode)); 00870 00871 if (TIM1_Channel == TIM1_Channel_1) 00872 { 00873 /* Disable the Channel 1: Reset the CCE Bit */ 00874 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E); 00875 00876 /* Reset the Output Compare Bits & Set the Output Compare Mode */ 00877 TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode); 00878 } 00879 else if (TIM1_Channel == TIM1_Channel_2) 00880 { 00881 /* Disable the Channel 2: Reset the CCE Bit */ 00882 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E); 00883 00884 /* Reset the Output Compare Bits & Set the Output Compare Mode */ 00885 TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode); 00886 } 00887 else 00888 { 00889 /* Disable the Channel 3: Reset the CCE Bit */ 00890 TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E); 00891 00892 /* Reset the Output Compare Bits & Set the Output Compare Mode */ 00893 TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_OCMode); 00894 00895 } 00896 } 00897 00898 /** 00899 * @brief Sets the TIM1 Capture Compare1 Register value. 00900 * @param Compare1 specifies the Capture Compare1 register new value. 00901 * This parameter is between 0x0000 and 0xFFFF. 00902 * @retval None 00903 */ 00904 void TIM1_SetCompare1(uint16_t Compare1) 00905 { 00906 /* Set the Capture Compare1 Register value */ 00907 TIM1->CCR1H = (uint8_t)(Compare1 >> 8); 00908 TIM1->CCR1L = (uint8_t)(Compare1); 00909 00910 } 00911 00912 /** 00913 * @brief Sets the TIM1 Capture Compare2 Register value. 00914 * @param Compare2 specifies the Capture Compare2 register new value. 00915 * This parameter is between 0x0000 and 0xFFFF. 00916 * @retval None 00917 */ 00918 void TIM1_SetCompare2(uint16_t Compare2) 00919 { 00920 /* Set the Capture Compare2 Register value */ 00921 TIM1->CCR2H = (uint8_t)(Compare2 >> 8); 00922 TIM1->CCR2L = (uint8_t)(Compare2); 00923 } 00924 00925 /** 00926 * @brief Sets the TIM1 Capture Compare3 Register value. 00927 * @param Compare3 specifies the Capture Compare3 register new value. 00928 * This parameter is between 0x0000 and 0xFFFF. 00929 * @retval None 00930 */ 00931 void TIM1_SetCompare3(uint16_t Compare3) 00932 { 00933 /* Set the Capture Compare3 Register value */ 00934 TIM1->CCR3H = (uint8_t)(Compare3 >> 8); 00935 TIM1->CCR3L = (uint8_t)(Compare3); 00936 } 00937 00938 /** 00939 * @brief Sets the TIM1 Capture Compare4 Register value. 00940 * @param Compare4 specifies the Capture Compare4 register new value. 00941 * This parameter is between 0x0000 and 0xFFFF. 00942 * @retval None 00943 */ 00944 void TIM1_SetCompare4(uint16_t Compare4) 00945 { 00946 /* Set the Capture Compare4 Register value */ 00947 TIM1->CCR4H = (uint8_t)(Compare4 >> 8); 00948 TIM1->CCR4L = (uint8_t)(Compare4); 00949 } 00950 00951 /** 00952 * @brief Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit. 00953 * @param NewState new state of the Capture Compare Preload Control bit. 00954 * This parameter can be ENABLE or DISABLE. 00955 * @retval None 00956 */ 00957 void TIM1_CCPreloadControl(FunctionalState NewState) 00958 { 00959 /* Check the parameters */ 00960 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00961 00962 /* Set or Reset the CCPC Bit */ 00963 if (NewState != DISABLE) 00964 { 00965 TIM1->CR2 |= TIM1_CR2_CCPC; 00966 } 00967 else 00968 { 00969 TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCPC); 00970 } 00971 } 00972 00973 /** 00974 * @brief Forces the TIM1 Channel1 output waveform to active or inactive level. 00975 * @param TIM1_ForcedAction specifies the forced Action to be set to the output waveform. 00976 * This parameter can be one of the following values: 00977 * @arg TIM1_ForcedAction_Active: Force active level on OC1REF 00978 * @arg TIM1_ForcedAction_Inactive: Force inactive level on OC1REF. 00979 * @retval None 00980 */ 00981 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction) 00982 { 00983 /* Check the parameters */ 00984 assert_param(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); 00985 00986 /* Reset the OCM Bits & Configure the Forced output Mode */ 00987 TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_ForcedAction); 00988 } 00989 00990 /** 00991 * @brief Forces the TIM1 Channel2 output waveform to active or inactive level. 00992 * @param TIM1_ForcedAction specifies the forced Action to be set to the output waveform. 00993 * This parameter can be one of the following values: 00994 * @arg TIM1_ForcedAction_Active: Force active level on OC2REF 00995 * @arg TIM1_ForcedAction_Inactive: Force inactive level on OC2REF. 00996 * @retval None 00997 */ 00998 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction) 00999 { 01000 /* Check the parameters */ 01001 assert_param(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); 01002 01003 /* Reset the OCM Bits & Configure the Forced output Mode */ 01004 TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_ForcedAction); 01005 } 01006 01007 /** 01008 * @brief Forces the TIM1 Channel3 output waveform to active or inactive level. 01009 * @param TIM1_ForcedAction specifies the forced Action to be set to the output waveform. 01010 * This parameter can be one of the following values: 01011 * @arg TIM1_ForcedAction_Active: Force active level on OC3REF 01012 * @arg TIM1_ForcedAction_Inactive: Force inactive level on OC3REF. 01013 * @retval None 01014 */ 01015 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction) 01016 { 01017 /* Check the parameters */ 01018 assert_param(IS_TIM1_FORCED_ACTION(TIM1_ForcedAction)); 01019 01020 /* Reset the OCM Bits */ /* Configure The Forced output Mode */ 01021 TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | (uint8_t)TIM1_ForcedAction); 01022 } 01023 01024 /** 01025 * @brief Enables or disables the TIM1 peripheral Preload Register on CCR1. 01026 * @param NewState new state of the Capture Compare Preload register. 01027 * This parameter can be ENABLE or DISABLE. 01028 * @retval None 01029 */ 01030 void TIM1_OC1PreloadConfig(FunctionalState NewState) 01031 { 01032 /* Check the parameters */ 01033 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01034 01035 /* Set or Reset the OC1PE Bit */ 01036 if (NewState != DISABLE) 01037 { 01038 TIM1->CCMR1 |= TIM1_CCMR_OCxPE; 01039 } 01040 else 01041 { 01042 TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxPE); 01043 } 01044 } 01045 01046 /** 01047 * @brief Enables or disables the TIM1 peripheral Preload Register on CCR2. 01048 * @param NewState new state of the Capture Compare Preload register. 01049 * This parameter can be ENABLE or DISABLE. 01050 * @retval None 01051 */ 01052 void TIM1_OC2PreloadConfig(FunctionalState NewState) 01053 { 01054 /* Check the parameters */ 01055 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01056 01057 /* Set or Reset the OC2PE Bit */ 01058 if (NewState != DISABLE) 01059 { 01060 TIM1->CCMR2 |= TIM1_CCMR_OCxPE; 01061 } 01062 else 01063 { 01064 TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxPE); 01065 } 01066 } 01067 01068 /** 01069 * @brief Enables or disables the TIM1 peripheral Preload Register on CCR3. 01070 * @param NewState new state of the Capture Compare Preload register. 01071 * This parameter can be ENABLE or DISABLE. 01072 * @retval None 01073 */ 01074 void TIM1_OC3PreloadConfig(FunctionalState NewState) 01075 { 01076 /* Check the parameters */ 01077 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01078 01079 /* Set or Reset the OC3PE Bit */ 01080 if (NewState != DISABLE) 01081 { 01082 TIM1->CCMR3 |= TIM1_CCMR_OCxPE; 01083 } 01084 else 01085 { 01086 TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxPE); 01087 } 01088 } 01089 01090 /** 01091 * @brief Enables or disables the TIM1 peripheral Preload Register on CCR4. 01092 * @param NewState new state of the Capture Compare Preload register. 01093 * This parameter can be ENABLE or DISABLE. 01094 * @retval None 01095 */ 01096 void TIM1_OC4PreloadConfig(FunctionalState NewState) 01097 { 01098 /* Check the parameters */ 01099 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01100 01101 /* Set or Reset the OC4PE Bit */ 01102 if (NewState != DISABLE) 01103 { 01104 TIM1->CCMR4 |= TIM1_CCMR_OCxPE; 01105 } 01106 else 01107 { 01108 TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxPE); 01109 } 01110 } 01111 01112 /** 01113 * @brief Configures the TIM1 Capture Compare 1 Fast feature. 01114 * @param NewState new state of the Output Compare Fast Enable bit. 01115 * This parameter can be ENABLE or DISABLE. 01116 * @retval None 01117 */ 01118 void TIM1_OC1FastConfig(FunctionalState NewState) 01119 { 01120 /* Check the parameters */ 01121 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01122 01123 /* Set or Reset the OC1FE Bit */ 01124 if (NewState != DISABLE) 01125 { 01126 TIM1->CCMR1 |= TIM1_CCMR_OCxFE; 01127 } 01128 else 01129 { 01130 TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxFE); 01131 } 01132 } 01133 01134 /** 01135 * @brief Configures the TIM1 Capture Compare 2 Fast feature. 01136 * @param NewState new state of the Output Compare Fast Enable bit. 01137 * This parameter can be ENABLE or DISABLE. 01138 * @retval None 01139 */ 01140 void TIM1_OC2FastConfig(FunctionalState NewState) 01141 { 01142 /* Check the parameters */ 01143 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01144 01145 /* Set or Reset the OC2FE Bit */ 01146 if (NewState != DISABLE) 01147 { 01148 TIM1->CCMR2 |= TIM1_CCMR_OCxFE; 01149 } 01150 else 01151 { 01152 TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxFE); 01153 } 01154 } 01155 01156 /** 01157 * @brief Configures the TIM1 Capture Compare 3 Fast feature. 01158 * @param NewState new state of the Output Compare Fast Enable bit. 01159 * This parameter can be ENABLE or DISABLE. 01160 * @retval None 01161 */ 01162 void TIM1_OC3FastConfig(FunctionalState NewState) 01163 { 01164 /* Check the parameters */ 01165 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01166 01167 /* Set or Reset the OC3FE Bit */ 01168 if (NewState != DISABLE) 01169 { 01170 TIM1->CCMR3 |= TIM1_CCMR_OCxFE; 01171 } 01172 else 01173 { 01174 TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxFE); 01175 } 01176 } 01177 01178 /** 01179 * @brief Clears or safeguards the OC1REF signal. 01180 * @param NewState new state of the Output Compare 1 Clear Enable bit. 01181 * This parameter can be ENABLE or DISABLE. 01182 * @retval None 01183 */ 01184 void TIM1_ClearOC1Ref(FunctionalState NewState) 01185 { 01186 /* Check the parameters */ 01187 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01188 01189 /* Set or Reset the OC1CE Bit */ 01190 if (NewState != DISABLE) 01191 { 01192 TIM1->CCMR1 |= TIM1_CCMR_OCxCE; 01193 } 01194 else 01195 { 01196 TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxCE); 01197 } 01198 } 01199 01200 /** 01201 * @brief Clears or safeguards the OC2REF signal. 01202 * @param NewState new state of the Output Compare 2 Clear Enable bit. 01203 * This parameter can be ENABLE or DISABLE. 01204 * @retval None 01205 */ 01206 void TIM1_ClearOC2Ref(FunctionalState NewState) 01207 { 01208 /* Check the parameters */ 01209 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01210 01211 /* Set or Reset the OC2CE Bit */ 01212 if (NewState != DISABLE) 01213 { 01214 TIM1->CCMR2 |= TIM1_CCMR_OCxCE; 01215 } 01216 else 01217 { 01218 TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxCE); 01219 } 01220 } 01221 01222 /** 01223 * @brief Clears or safeguards the OC3REF signal. 01224 * @param NewState new state of the Output Compare 3 Clear Enable bit. 01225 * This parameter can be ENABLE or DISABLE. 01226 * @retval None 01227 */ 01228 void TIM1_ClearOC3Ref(FunctionalState NewState) 01229 { 01230 /* Check the parameters */ 01231 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01232 01233 /* Set or Reset the OC3CE Bit */ 01234 if (NewState != DISABLE) 01235 { 01236 TIM1->CCMR3 |= TIM1_CCMR_OCxCE; 01237 } 01238 else 01239 { 01240 TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxCE); 01241 } 01242 } 01243 01244 /** 01245 * @brief Clears or safeguards the OC4REF signal. 01246 * @param NewState new state of the Output Compare 4 Clear Enable bit. 01247 * This parameter can be ENABLE or DISABLE. 01248 * @retval None 01249 */ 01250 void TIM1_ClearOC4Ref(FunctionalState NewState) 01251 { 01252 /* Check the parameters */ 01253 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01254 01255 /* Set or Reset the OC4CE Bit */ 01256 if (NewState != DISABLE) 01257 { 01258 TIM1->CCMR4 |= TIM1_CCMR_OCxCE; 01259 } 01260 else 01261 { 01262 TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxCE); 01263 } 01264 } 01265 01266 /** 01267 * @brief Configures the TIM1 Channel 1 polarity. 01268 * @param TIM1_OCPolarity specifies the OC1 Polarity. 01269 * This parameter can be one of the following values: 01270 * @arg TIM1_OCPolarity_High: Output Compare active low 01271 * @arg TIM1_OCPolarity_Low: Output Compare active high 01272 * @retval None 01273 */ 01274 void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity) 01275 { 01276 /* Check the parameters */ 01277 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); 01278 01279 /* Set or Reset the CC1P Bit */ 01280 if (TIM1_OCPolarity != TIM1_OCPolarity_High) 01281 { 01282 TIM1->CCER1 |= TIM1_CCER1_CC1P; 01283 } 01284 else 01285 { 01286 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P); 01287 } 01288 } 01289 01290 /** 01291 * @brief Configures the TIM1 Channel 1N polarity. 01292 * @param TIM1_OCNPolarity specifies the OC1N Polarity. 01293 * This parameter can be one of the following values: 01294 * @arg TIM1_OCNPolarity_High: Complementary Output Compare active low 01295 * @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high 01296 * @retval None 01297 */ 01298 void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity) 01299 { 01300 /* Check the parameters */ 01301 assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity)); 01302 01303 /* Set or Reset the CC3P Bit */ 01304 if (TIM1_OCNPolarity != TIM1_OCNPolarity_High) 01305 { 01306 TIM1->CCER1 |= TIM1_CCER1_CC1NP; 01307 } 01308 else 01309 { 01310 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NP); 01311 } 01312 } 01313 01314 /** 01315 * @brief Configures the TIM1 Channel 2 polarity. 01316 * @param TIM1_OCPolarity specifies the OC2 Polarity. 01317 * This parameter can be one of the following values: 01318 * @arg TIM1_OCPolarity_High: Output Compare active low 01319 * @arg TIM1_OCPolarity_Low: Output Compare active high 01320 * @retval None 01321 */ 01322 void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity) 01323 { 01324 /* Check the parameters */ 01325 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); 01326 01327 /* Set or Reset the CC2P Bit */ 01328 if (TIM1_OCPolarity != TIM1_OCPolarity_High) 01329 { 01330 TIM1->CCER1 |= TIM1_CCER1_CC2P; 01331 } 01332 else 01333 { 01334 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P); 01335 } 01336 } 01337 01338 /** 01339 * @brief Configures the TIM1 Channel 2N polarity. 01340 * @param TIM1_OCNPolarity specifies the OC2N Polarity. 01341 * This parameter can be one of the following values: 01342 * @arg TIM1_OCNPolarity_High: Complementary Output Compare active low 01343 * @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high 01344 * @retval None 01345 */ 01346 void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity) 01347 { 01348 /* Check the parameters */ 01349 assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity)); 01350 01351 /* Set or Reset the CC3P Bit */ 01352 if (TIM1_OCNPolarity != TIM1_OCNPolarity_High) 01353 { 01354 TIM1->CCER1 |= TIM1_CCER1_CC2NP; 01355 } 01356 else 01357 { 01358 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NP); 01359 } 01360 } 01361 01362 /** 01363 * @brief Configures the TIM1 Channel 3 polarity. 01364 * @param TIM1_OCPolarity specifies the OC3 Polarity. 01365 * This parameter can be one of the following values: 01366 * @arg TIM1_OCPolarity_High: Output Compare active low 01367 * @arg TIM1_OCPolarity_Low: Output Compare active high 01368 * @retval None 01369 */ 01370 void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity) 01371 { 01372 /* Check the parameters */ 01373 assert_param(IS_TIM1_OC_POLARITY(TIM1_OCPolarity)); 01374 01375 /* Set or Reset the CC3P Bit */ 01376 if (TIM1_OCPolarity != TIM1_OCPolarity_High) 01377 { 01378 TIM1->CCER2 |= TIM1_CCER2_CC3P; 01379 } 01380 else 01381 { 01382 TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P); 01383 } 01384 } 01385 01386 /** 01387 * @brief Configures the TIM1 Channel 3N polarity. 01388 * @param TIM1_OCNPolarity specifies the OC3N Polarity. 01389 * This parameter can be one of the following values: 01390 * @arg TIM1_OCNPolarity_High: Complementary Output Compare active low 01391 * @arg TIM1_OCNPolarity_Low: Complementary Output Compare active high 01392 * @retval None 01393 */ 01394 void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity) 01395 { 01396 /* Check the parameters */ 01397 assert_param(IS_TIM1_OCN_POLARITY(TIM1_OCNPolarity)); 01398 01399 /* Set or Reset the CC3P Bit */ 01400 if (TIM1_OCNPolarity != TIM1_OCNPolarity_High) 01401 { 01402 TIM1->CCER2 |= TIM1_CCER2_CC3NP; 01403 } 01404 else 01405 { 01406 TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NP); 01407 } 01408 } 01409 01410 /** 01411 * @brief Selects the OCReference Clear source. 01412 * @param TIM1_OCReferenceClear: specifies the OCReference Clear source. 01413 * This parameter can be one of the following values: 01414 * @arg TIM1_OCReferenceClear_ETRF: OCReference Clear source ETR 01415 * @arg TIM1_OCReferenceClear_OCREFCLR: OCReference Clear source OCREF 01416 * @retval None 01417 */ 01418 void TIM1_SelectOCREFClear(TIM1_OCReferenceClear_TypeDef TIM1_OCReferenceClear) 01419 { 01420 /* Check the parameters */ 01421 assert_param(IS_TIM1_OCREFERENCECECLEAR_SOURCE(TIM1_OCReferenceClear)); 01422 01423 /* Set the TIM1_OCReferenceClear source */ 01424 TIM1->SMCR &= (uint8_t) (~TIM1_SMCR_OCCS); 01425 TIM1->SMCR |= (uint8_t) TIM1_OCReferenceClear; 01426 } 01427 01428 /** 01429 * @brief Selects the TIM1 peripheral Commutation event. 01430 * @param NewState new state of the Commutation event. 01431 * This parameter can be ENABLE or DISABLE. 01432 * @retval None 01433 */ 01434 void TIM1_SelectCOM(FunctionalState NewState) 01435 { 01436 /* Check the parameters */ 01437 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01438 01439 /* Set or Reset the CCUS Bit */ 01440 if (NewState != DISABLE) 01441 { 01442 TIM1->CR2 |= TIM1_CR2_CCUS; 01443 } 01444 else 01445 { 01446 TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCUS); 01447 } 01448 } 01449 01450 /** 01451 * @brief Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4). 01452 * @param TIM1_Channel specifies the TIM1 Channel. 01453 * This parameter can be one of the following values: 01454 * @arg TIM1_Channel_1: TIM1 Channel1 01455 * @arg TIM1_Channel_2: TIM1 Channel2 01456 * @arg TIM1_Channel_3: TIM1 Channel3 01457 * @arg TIM1_CHANNEL_4: TIM1 Channel4 01458 * @param NewState specifies the TIM1 Channel CCxE bit new state. 01459 * This parameter can be: ENABLE or DISABLE. 01460 * @retval None 01461 */ 01462 void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState) 01463 { 01464 /* Check the parameters */ 01465 assert_param(IS_TIM1_CHANNEL(TIM1_Channel)); 01466 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01467 01468 if (TIM1_Channel == TIM1_Channel_1) 01469 { 01470 /* Set or Reset the CC1E Bit */ 01471 if (NewState != DISABLE) 01472 { 01473 TIM1->CCER1 |= TIM1_CCER1_CC1E; 01474 } 01475 else 01476 { 01477 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E); 01478 } 01479 } 01480 else if (TIM1_Channel == TIM1_Channel_2) 01481 { 01482 /* Set or Reset the CC2E Bit */ 01483 if (NewState != DISABLE) 01484 { 01485 TIM1->CCER1 |= TIM1_CCER1_CC2E; 01486 } 01487 else 01488 { 01489 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E); 01490 } 01491 } 01492 else if (TIM1_Channel == TIM1_Channel_3) 01493 { 01494 /* Set or Reset the CC3E Bit */ 01495 if (NewState != DISABLE) 01496 { 01497 TIM1->CCER2 |= TIM1_CCER2_CC3E; 01498 } 01499 else 01500 { 01501 TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E); 01502 } 01503 } 01504 else 01505 { 01506 /* Set or Reset the CC4E Bit */ 01507 if (NewState != DISABLE) 01508 { 01509 TIM1->CCER2 |= TIM1_CCER2_CC4E; 01510 } 01511 else 01512 { 01513 TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E); 01514 } 01515 } 01516 } 01517 01518 /** 01519 * @brief Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3). 01520 * @param TIM1_Channel specifies the TIM1 Channel. 01521 * This parameter can be one of the following values: 01522 * @arg TIM1_Channel_1: TIM1 Channel1 01523 * @arg TIM1_Channel_2: TIM1 Channel2 01524 * @arg TIM1_Channel_3: TIM1 Channel3 01525 * @param NewState specifies the TIM1 Channel CCxNE bit new state. 01526 * This parameter can be: ENABLE or DISABLE. 01527 * @retval None 01528 */ 01529 void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState) 01530 { 01531 /* Check the parameters */ 01532 assert_param(IS_TIM1_COMPLEMENTARY_CHANNEL(TIM1_Channel)); 01533 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01534 01535 if (TIM1_Channel == TIM1_Channel_1) 01536 { 01537 /* Set or Reset the CC1NE Bit */ 01538 if (NewState != DISABLE) 01539 { 01540 TIM1->CCER1 |= TIM1_CCER1_CC1NE; 01541 } 01542 else 01543 { 01544 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NE); 01545 } 01546 } 01547 else if (TIM1_Channel == TIM1_Channel_2) 01548 { 01549 /* Set or Reset the CC2NE Bit */ 01550 if (NewState != DISABLE) 01551 { 01552 TIM1->CCER1 |= TIM1_CCER1_CC2NE; 01553 } 01554 else 01555 { 01556 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NE); 01557 } 01558 } 01559 else 01560 { 01561 /* Set or Reset the CC3NE Bit */ 01562 if (NewState != DISABLE) 01563 { 01564 TIM1->CCER2 |= TIM1_CCER2_CC3NE; 01565 } 01566 else 01567 { 01568 TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NE); 01569 } 01570 } 01571 } 01572 01573 /** 01574 * @} 01575 */ 01576 01577 /** @defgroup TIM1_Group3 Input Capture management functions 01578 * @brief Input Capture management functions 01579 * 01580 @verbatim 01581 =============================================================================== 01582 Input Capture management functions 01583 =============================================================================== 01584 01585 =================================================================== 01586 TIM1 Driver: how to use it in Input Capture Mode 01587 =================================================================== 01588 To use the Timer in Input Capture mode, the following steps are mandatory: 01589 01590 1. Enable TIM1 clock using CLK_PeripheralClockConfig(CLK_Peripheral_TIM1, ENABLE) function. 01591 01592 2. Configure the TIM1 pins in input mode by configuring the corresponding GPIO pins 01593 01594 3. Configure the Time base unit as described in the first part of this driver, if needed, 01595 otherwise the Timer will run with the default configuration: 01596 - Autoreload value = 0xFFFF 01597 - Prescaler value = 0x0000 01598 - Counter mode = Up counting 01599 01600 4. Call TIM1_ICInit() to configure the desired channel to measure only 01601 frequency or duty cycle of the input signal using the corresponding configuration: 01602 - TIM1 Channel: TIM1_Channel 01603 - TIM1 Input Capture polarity: TIM1_ICPolarity 01604 - TIM1 Input Capture selection: TIM1_ICSelection 01605 - TIM1 Input Capture Prescaler: TIM1_ICPSC 01606 - TIM1 Input Capture filter value 01607 or, 01608 Call TIM1_PWMIConfig() to configure the desired channels with the 01609 corresponding configuration and to measure the frequency and the duty 01610 cycle of the input signal. 01611 01612 5. Enable global interrupts or the DMA to read the measured frequency. 01613 01614 6. Enable the corresponding interrupt (or DMA request) to read the captured value, 01615 using the function TIM1_ITConfig(TIM1_IT_CCx) (or TIM1_DMACmd(TIM1_DMASource_CCx)) 01616 01617 7. Call the TIM1_Cmd(ENABLE) function to enable the TIM1 counter. 01618 01619 8. Use TIM1_GetCapturex() to read the captured value corresponding to 01620 channel x. 01621 01622 Note1: All other functions can be used separately to modify, if needed, 01623 a specific feature of the Timer. 01624 01625 @endverbatim 01626 * @{ 01627 */ 01628 01629 /** 01630 * @brief Initializes the TIM1 peripheral according to the specified parameters. 01631 * @param TIM1_Channel specifies the input capture channel 01632 * This parameter can be one of the following values: 01633 * @arg TIM1_Channel_1: TIM1 Channel1 01634 * @arg TIM1_Channel_2: TIM1 Channel2 01635 * @arg TIM1_Channel_3: TIM1 Channel3 01636 * @arg TIM1_Channel_4: TIM1 Channel4 01637 * @param TIM1_ICPolarity specifies the Input capture polarity 01638 * This parameter can be one of the following values: 01639 * @arg TIM1_ICPolarity_Rising: Input capture polarity rising 01640 * @arg TIM1_ICPolarity_Falling: Input capture polarity falling 01641 * @param TIM1_ICSelection specifies the Input capture source selection 01642 * This parameter can be one of the following values: 01643 * @arg TIM1_ICSelection_DirectTI: TIM1 Input x is selected to be connected to ICx. 01644 * @arg TIM1_ICSelection_IndirectTI: TIM1 Input x is selected to be connected to ICy. 01645 * @arg TIM1_ICSelection_TRGI: TIM1 Input x is selected to be connected to the TRGI 01646 * @param TIM1_ICPrescaler specifies the Input capture Prescaler 01647 * This parameter can be one of the following values: 01648 * @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event) 01649 * @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events) 01650 * @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events) 01651 * @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 01652 * @param TIM1_ICFilter specifies the Input capture filter value. 01653 * @note If the channel 3 is selected the TIM1_ICSelection_IndirectTI parameter is forbidden. 01654 * @note If the channel 4 is selected the TIM1_ICSelection_DirectTI parameter is forbidden. 01655 * @retval None 01656 */ 01657 01658 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel, 01659 TIM1_ICPolarity_TypeDef TIM1_ICPolarity, 01660 TIM1_ICSelection_TypeDef TIM1_ICSelection, 01661 TIM1_ICPSC_TypeDef TIM1_ICPrescaler, 01662 uint8_t TIM1_ICFilter) 01663 { 01664 01665 /* Check the parameters */ 01666 assert_param(IS_TIM1_CHANNEL(TIM1_Channel)); 01667 assert_param(IS_TIM1_IC_POLARITY(TIM1_ICPolarity)); 01668 assert_param(IS_TIM1_IC_SELECTION(TIM1_ICSelection)); 01669 assert_param(IS_TIM1_IC_PRESCALER(TIM1_ICPrescaler)); 01670 assert_param(IS_TIM1_IC_FILTER(TIM1_ICFilter)); 01671 01672 if (TIM1_Channel == TIM1_Channel_1) 01673 { 01674 /* TI1 Configuration */ 01675 TI1_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter); 01676 /* Set the Input Capture Prescaler value */ 01677 TIM1_SetIC1Prescaler(TIM1_ICPrescaler); 01678 } 01679 else if (TIM1_Channel == TIM1_Channel_2) 01680 { 01681 /* TI2 Configuration */ 01682 TI2_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter); 01683 /* Set the Input Capture Prescaler value */ 01684 TIM1_SetIC2Prescaler(TIM1_ICPrescaler); 01685 } 01686 else if (TIM1_Channel == TIM1_Channel_3) 01687 { 01688 /* TI3 Configuration */ 01689 TI3_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter); 01690 /* Set the Input Capture Prescaler value */ 01691 TIM1_SetIC3Prescaler(TIM1_ICPrescaler); 01692 } 01693 else 01694 { 01695 /* TI4 Configuration */ 01696 TI4_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter); 01697 /* Set the Input Capture Prescaler value */ 01698 TIM1_SetIC4Prescaler(TIM1_ICPrescaler); 01699 } 01700 } 01701 01702 /** 01703 * @brief Configures the TIM1 peripheral in PWM Input Mode according to the 01704 * specified parameters. 01705 * @param TIM1_Channel specifies the input capture channel 01706 * This parameter can be one of the following values: 01707 * @arg TIM1_Channel_1: TIM1 Channel1 01708 * @arg TIM1_Channel_2: TIM1 Channel2 01709 * @param TIM1_ICPolarity specifies the Input capture polarity 01710 * This parameter can be one of the following values: 01711 * @arg TIM1_ICPolarity_Rising: Input capture polarity rising 01712 * @arg TIM1_ICPolarity_Falling: Input capture polarity falling 01713 * @param TIM1_ICSelection specifies the Input capture source selection 01714 * This parameter can be one of the following values: 01715 * @arg TIM1_ICSelection_DirectTI: TIM1 Input x is selected to be connected to ICx. 01716 * @arg TIM1_ICSelection_IndirectTI: TIM1 Input x is selected to be connected to ICy. 01717 * @arg TIM1_ICSelection_TRGI: TIM1 Input x is selected to be connected to the TRGI 01718 * @param TIM1_ICPrescaler specifies the Input capture Prescaler 01719 * This parameter can be one of the following values: 01720 * @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event) 01721 * @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events) 01722 * @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events) 01723 * @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 01724 * @param TIM1_ICFilter specifies the Input capture filter value. 01725 * @retval None 01726 */ 01727 void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel, 01728 TIM1_ICPolarity_TypeDef TIM1_ICPolarity, 01729 TIM1_ICSelection_TypeDef TIM1_ICSelection, 01730 TIM1_ICPSC_TypeDef TIM1_ICPrescaler, 01731 uint8_t TIM1_ICFilter) 01732 { 01733 TIM1_ICPolarity_TypeDef icpolarity = TIM1_ICPolarity_Rising; 01734 TIM1_ICSelection_TypeDef icselection = TIM1_ICSelection_DirectTI; 01735 01736 /* Check the parameters */ 01737 assert_param(IS_TIM1_PWMI_CHANNEL(TIM1_Channel)); 01738 assert_param(IS_TIM1_IC_POLARITY(TIM1_ICPolarity)); 01739 assert_param(IS_TIM1_IC_SELECTION(TIM1_ICSelection)); 01740 assert_param(IS_TIM1_IC_PRESCALER(TIM1_ICPrescaler)); 01741 01742 /* Select the Opposite Input Polarity */ 01743 if (TIM1_ICPolarity != TIM1_ICPolarity_Falling) 01744 { 01745 icpolarity = TIM1_ICPolarity_Falling; 01746 } 01747 else 01748 { 01749 icpolarity = TIM1_ICPolarity_Rising; 01750 } 01751 01752 /* Select the Opposite Input */ 01753 if (TIM1_ICSelection == TIM1_ICSelection_DirectTI) 01754 { 01755 icselection = TIM1_ICSelection_IndirectTI; 01756 } 01757 else 01758 { 01759 icselection = TIM1_ICSelection_DirectTI; 01760 } 01761 01762 if (TIM1_Channel == TIM1_Channel_1) 01763 { 01764 /* TI1 Configuration */ 01765 TI1_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter); 01766 01767 /* Set the Input Capture Prescaler value */ 01768 TIM1_SetIC1Prescaler(TIM1_ICPrescaler); 01769 01770 /* TI2 Configuration */ 01771 TI2_Config(icpolarity, icselection, TIM1_ICFilter); 01772 01773 /* Set the Input Capture Prescaler value */ 01774 TIM1_SetIC2Prescaler(TIM1_ICPrescaler); 01775 } 01776 else 01777 { 01778 /* TI2 Configuration */ 01779 TI2_Config(TIM1_ICPolarity, TIM1_ICSelection, TIM1_ICFilter); 01780 01781 /* Set the Input Capture Prescaler value */ 01782 TIM1_SetIC2Prescaler(TIM1_ICPrescaler); 01783 01784 /* TI1 Configuration */ 01785 TI1_Config(icpolarity, icselection, TIM1_ICFilter); 01786 01787 /* Set the Input Capture Prescaler value */ 01788 TIM1_SetIC1Prescaler(TIM1_ICPrescaler); 01789 } 01790 } 01791 01792 /** 01793 * @brief Gets the TIM1 Input Capture 1 value. 01794 * @param None 01795 * @retval Capture Compare 1 Register value. 01796 */ 01797 uint16_t TIM1_GetCapture1(void) 01798 { 01799 /* Get the Capture 1 Register value */ 01800 01801 uint16_t tmpccr1 = 0; 01802 uint8_t tmpccr1l = 0, tmpccr1h = 0; 01803 01804 tmpccr1h = TIM1->CCR1H; 01805 tmpccr1l = TIM1->CCR1L; 01806 01807 tmpccr1 = (uint16_t)(tmpccr1l); 01808 tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8); 01809 /* Get the Capture 1 Register value */ 01810 return (uint16_t)tmpccr1; 01811 } 01812 01813 /** 01814 * @brief Gets the TIM1 Input Capture 2 value. 01815 * @param None 01816 * @retval Capture Compare 2 Register value. 01817 */ 01818 uint16_t TIM1_GetCapture2(void) 01819 { 01820 /* Get the Capture 2 Register value */ 01821 01822 uint16_t tmpccr2 = 0; 01823 uint8_t tmpccr2l = 0, tmpccr2h = 0; 01824 01825 tmpccr2h = TIM1->CCR2H; 01826 tmpccr2l = TIM1->CCR2L; 01827 01828 tmpccr2 = (uint16_t)(tmpccr2l); 01829 tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8); 01830 /* Get the Capture 2 Register value */ 01831 return (uint16_t)tmpccr2; 01832 } 01833 01834 /** 01835 * @brief Gets the TIM1 Input Capture 3 value. 01836 * @param None 01837 * @retval Capture Compare 3 Register value. 01838 */ 01839 uint16_t TIM1_GetCapture3(void) 01840 { 01841 /* Get the Capture 3 Register value */ 01842 uint16_t tmpccr3 = 0; 01843 uint8_t tmpccr3l = 0, tmpccr3h = 0; 01844 01845 tmpccr3h = TIM1->CCR3H; 01846 tmpccr3l = TIM1->CCR3L; 01847 01848 tmpccr3 = (uint16_t)(tmpccr3l); 01849 tmpccr3 |= (uint16_t)((uint16_t)tmpccr3h << 8); 01850 /* Get the Capture 3 Register value */ 01851 return (uint16_t)tmpccr3; 01852 } 01853 01854 /** 01855 * @brief Gets the TIM1 Input Capture 4 value. 01856 * @param None 01857 * @retval Capture Compare 4 Register value. 01858 */ 01859 uint16_t TIM1_GetCapture4(void) 01860 { 01861 /* Get the Capture 4 Register value */ 01862 uint16_t tmpccr4 = 0; 01863 uint8_t tmpccr4l = 0, tmpccr4h = 0; 01864 01865 tmpccr4h = TIM1->CCR4H; 01866 tmpccr4l = TIM1->CCR4L; 01867 01868 tmpccr4 = (uint16_t)(tmpccr4l); 01869 tmpccr4 |= (uint16_t)((uint16_t)tmpccr4h << 8); 01870 /* Get the Capture 4 Register value */ 01871 return (uint16_t)tmpccr4; 01872 } 01873 01874 /** 01875 * @brief Sets the TIM1 Input Capture 1 prescaler. 01876 * @param TIM1_IC1Prescaler specifies the Input Capture prescaler new value 01877 * This parameter can be one of the following values: 01878 * @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event) 01879 * @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events) 01880 * @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events) 01881 * @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 01882 * @retval None 01883 */ 01884 void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler) 01885 { 01886 /* Check the parameters */ 01887 assert_param(IS_TIM1_IC_PRESCALER(TIM1_IC1Prescaler)); 01888 01889 /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */ 01890 TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_ICxPSC)) | (uint8_t)TIM1_IC1Prescaler); 01891 } 01892 01893 /** 01894 * @brief Sets the TIM1 Input Capture 2 prescaler. 01895 * @param TIM1_IC2Prescaler specifies the Input Capture prescaler new value 01896 * This parameter can be one of the following values: 01897 * @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event) 01898 * @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events) 01899 * @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events) 01900 * @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 01901 * @retval None 01902 */ 01903 void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler) 01904 { 01905 /* Check the parameters */ 01906 assert_param(IS_TIM1_IC_PRESCALER(TIM1_IC2Prescaler)); 01907 01908 /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */ 01909 TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_ICxPSC)) | (uint8_t)TIM1_IC2Prescaler); 01910 } 01911 01912 /** 01913 * @brief Sets the TIM1 Input Capture 3 prescaler. 01914 * @param TIM1_IC3Prescaler specifies the Input Capture prescaler new value 01915 * This parameter can be one of the following values: 01916 * @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event) 01917 * @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events) 01918 * @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events) 01919 * @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 01920 * @retval None 01921 */ 01922 void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler) 01923 { 01924 01925 /* Check the parameters */ 01926 assert_param(IS_TIM1_IC_PRESCALER(TIM1_IC3Prescaler)); 01927 01928 /* Reset the IC1PSC Bits & Set the IC1PSC value */ 01929 TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_ICxPSC)) | (uint8_t)TIM1_IC3Prescaler); 01930 } 01931 01932 /** 01933 * @brief Sets the TIM1 Input Capture 4 prescaler. 01934 * @param TIM1_IC4Prescaler specifies the Input Capture prescaler new value 01935 * This parameter can be one of the following values: 01936 * @arg TIM1_ICPSC_DIV1: Input Capture Prescaler = 1 (one capture every 1 event) 01937 * @arg TIM1_ICPSC_DIV2: Input Capture Prescaler = 2 (one capture every 2 events) 01938 * @arg TIM1_ICPSC_DIV4: Input Capture Prescaler = 4 (one capture every 4 events) 01939 * @arg TIM1_ICPSC_DIV8: Input Capture Prescaler = 8 (one capture every 8 events) 01940 * @retval None 01941 */ 01942 void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler) 01943 { 01944 01945 /* Check the parameters */ 01946 assert_param(IS_TIM1_IC_PRESCALER(TIM1_IC4Prescaler)); 01947 01948 /* Reset the IC1PSC Bits & Set the IC1PSC value */ 01949 TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_ICxPSC)) | (uint8_t)TIM1_IC4Prescaler); 01950 } 01951 01952 /** 01953 * @} 01954 */ 01955 01956 /** @defgroup TIM1_Group4 Interrupts DMA and flags management functions 01957 * @brief Interrupts, DMA and flags management functions 01958 * 01959 @verbatim 01960 =============================================================================== 01961 Interrupts, DMA and flags management functions 01962 =============================================================================== 01963 01964 @endverbatim 01965 * @{ 01966 */ 01967 01968 /** 01969 * @brief Enables or disables the specified TIM1 interrupts. 01970 * @param NewState new state of the TIM1 peripheral. 01971 * This parameter can be: ENABLE or DISABLE. 01972 * @param TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled. 01973 * This parameter can be any combination of the following values: 01974 * @arg TIM1_IT_Update: Update 01975 * @arg TIM1_IT_CC1: Capture Compare Channel1 01976 * @arg TIM1_IT_CC2: Capture Compare Channel2 01977 * @arg TIM1_IT_CC3: Capture Compare Channel3 01978 * @arg TIM1_IT_CC4: Capture Compare Channel4 01979 * @arg TIM1_IT_COM: Commutation 01980 * @arg TIM1_IT_Trigger: Trigger 01981 * @arg TIM1_IT_Break: Break 01982 * @param NewState new state of the TIM1 peripheral. 01983 * @retval None 01984 */ 01985 void TIM1_ITConfig(TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState) 01986 { 01987 /* Check the parameters */ 01988 assert_param(IS_TIM1_IT(TIM1_IT)); 01989 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01990 01991 if (NewState != DISABLE) 01992 { 01993 /* Enable the Interrupt sources */ 01994 TIM1->IER |= (uint8_t)TIM1_IT; 01995 } 01996 else 01997 { 01998 /* Disable the Interrupt sources */ 01999 TIM1->IER &= (uint8_t)(~(uint8_t)TIM1_IT); 02000 } 02001 } 02002 02003 /** 02004 * @brief Configures the TIM1 event to be generated by software. 02005 * @param TIM1_EventSource specifies the event source. 02006 * This parameter can be any combination of the following values: 02007 * @arg TIM1_EventSource_Update: Update 02008 * @arg TIM1_EventSource_CC1: Capture Compare Channel1 02009 * @arg TIM1_EventSource_CC2: Capture Compare Channel2 02010 * @arg TIM1_EventSource_CC3: Capture Compare Channel3 02011 * @arg TIM1_EventSource_CC4: Capture Compare Channel4 02012 * @arg TIM1_EventSource_COM: Commutation 02013 * @arg TIM1_EventSource_Trigger: Trigger 02014 * @arg TIM1_EventSource_Break: Break 02015 * @retval None 02016 */ 02017 void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource) 02018 { 02019 /* Check the parameters */ 02020 assert_param(IS_TIM1_EVENT_SOURCE(TIM1_EventSource)); 02021 02022 /* Set the event sources */ 02023 TIM1->EGR = (uint8_t)TIM1_EventSource; 02024 } 02025 /** 02026 * @brief Checks whether the specified TIM1 flag is set or not. 02027 * @param TIM1_FLAG specifies the flag to check. 02028 * This parameter can be one of the following values: 02029 * @arg TIM1_FLAG_Update: TIM1 update Flag 02030 * @arg TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag 02031 * @arg TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag 02032 * @arg TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag 02033 * @arg TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag 02034 * @arg TIM1_FLAG_COM: TIM1 Commutation Flag 02035 * @arg TIM1_FLAG_Trigger: TIM1 Trigger Flag 02036 * @arg TIM1_FLAG_Break: TIM1 Break Flag 02037 * @arg TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag 02038 * @arg TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag 02039 * @arg TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag 02040 * @arg TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag 02041 * @retval FlagStatus The new state of TIM1_FLAG (SET or RESET). 02042 */ 02043 FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG) 02044 { 02045 FlagStatus bitstatus = RESET; 02046 uint8_t tim1_flag_l = 0, tim1_flag_h = 0; 02047 02048 /* Check the parameters */ 02049 assert_param(IS_TIM1_GET_FLAG(TIM1_FLAG)); 02050 02051 tim1_flag_l = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_FLAG); 02052 tim1_flag_h = (uint8_t)(TIM1->SR2 & (uint8_t)((uint16_t)TIM1_FLAG >> 8)); 02053 02054 if ((uint8_t)((uint8_t)tim1_flag_l | (uint8_t)tim1_flag_h) != 0) 02055 { 02056 bitstatus = SET; 02057 } 02058 else 02059 { 02060 bitstatus = RESET; 02061 } 02062 return (FlagStatus)(bitstatus); 02063 } 02064 02065 /** 02066 * @brief Clears the TIM1�s pending flags. 02067 * @param TIM1_FLAG specifies the flag to clear. 02068 * This parameter can be one of the following values: 02069 * @arg TIM1_FLAG_Update: TIM1 update Flag 02070 * @arg TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag 02071 * @arg TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag 02072 * @arg TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag 02073 * @arg TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag 02074 * @arg TIM1_FLAG_COM: TIM1 Commutation Flag 02075 * @arg TIM1_FLAG_Trigger: TIM1 Trigger Flag 02076 * @arg TIM1_FLAG_Break: TIM1 Break Flag 02077 * @arg TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag 02078 * @arg TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag 02079 * @arg TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag 02080 * @arg TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag 02081 * @retval None. 02082 */ 02083 void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG) 02084 { 02085 /* Check the parameters */ 02086 assert_param(IS_TIM1_CLEAR_FLAG(TIM1_FLAG)); 02087 02088 /* Clear the flags (rc_w0) clear this bit by writing 0. Writing �1� has no effect*/ 02089 TIM1->SR1 = (uint8_t)(~(uint8_t)(TIM1_FLAG)); 02090 TIM1->SR2 = (uint8_t)((uint8_t)(~((uint8_t)((uint16_t)TIM1_FLAG >> 8))) & (uint8_t)0x1E); 02091 } 02092 02093 /** 02094 * @brief Checks whether the TIM1 interrupt has occurred or not. 02095 * @param TIM1_IT specifies the TIM1 interrupt source to check. 02096 * This parameter can be any combination of the following values: 02097 * @arg TIM1_IT_Update: Update 02098 * @arg TIM1_IT_CC1: Capture Compare Channel1 02099 * @arg TIM1_IT_CC2: Capture Compare Channel2 02100 * @arg TIM1_IT_CC3: Capture Compare Channel3 02101 * @arg TIM1_IT_CC4: Capture Compare Channel4 02102 * @arg TIM1_IT_COM: Commutation 02103 * @arg TIM1_IT_Trigger: Trigger 02104 * @arg TIM1_IT_Break: Break 02105 * @retval ITStatus The new state of the TIM1_IT(SET or RESET). 02106 */ 02107 02108 ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT) 02109 { 02110 ITStatus bitstatus = RESET; 02111 02112 uint8_t TIM1_itStatus = 0x0, TIM1_itEnable = 0x0; 02113 02114 /* Check the parameters */ 02115 assert_param(IS_TIM1_GET_IT(TIM1_IT)); 02116 02117 TIM1_itStatus = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_IT); 02118 02119 TIM1_itEnable = (uint8_t)(TIM1->IER & (uint8_t)TIM1_IT); 02120 02121 if ((TIM1_itStatus != (uint8_t)RESET ) && (TIM1_itEnable != (uint8_t)RESET )) 02122 { 02123 bitstatus = SET; 02124 } 02125 else 02126 { 02127 bitstatus = RESET; 02128 } 02129 return (ITStatus)(bitstatus); 02130 } 02131 02132 /** 02133 * @brief Clears the TIM1's interrupt pending bits. 02134 * @param TIM1_IT specifies the pending bit to clear. 02135 * This parameter can be any combination of the following values: 02136 * @arg TIM1_IT_Update: Update 02137 * @arg TIM1_IT_CC1: Capture Compare Channel1 02138 * @arg TIM1_IT_CC2: Capture Compare Channel2 02139 * @arg TIM1_IT_CC3: Capture Compare Channel3 02140 * @arg TIM1_IT_CC4: Capture Compare Channel4 02141 * @arg TIM1_IT_COM: Commutation 02142 * @arg TIM1_IT_Trigger: Trigger 02143 * @arg TIM1_IT_Break: Break 02144 * @retval None. 02145 */ 02146 void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT) 02147 { 02148 /* Check the parameters */ 02149 assert_param(IS_TIM1_IT(TIM1_IT)); 02150 02151 /* Clear the IT pending Bit */ 02152 TIM1->SR1 = (uint8_t)(~(uint8_t)TIM1_IT); 02153 } 02154 02155 /** 02156 * @brief Configures the TIM1�s DMA interface. 02157 * @param TIM1_DMABase: DMA Base address. 02158 * @param TIM1_DMABurstLength: DMA Burst length. 02159 * @retval None. 02160 */ 02161 void TIM1_DMAConfig(TIM1_DMABase_TypeDef TIM1_DMABase, 02162 TIM1_DMABurstLength_TypeDef TIM1_DMABurstLength) 02163 { 02164 /* Check the parameters */ 02165 assert_param(IS_TIM1_DMABase(TIM1_DMABase)); 02166 assert_param(IS_TIM1_DMABurstLength(TIM1_DMABurstLength)); 02167 02168 /* Set the DMA Base and the DMA Burst Length */ 02169 TIM1->DCR1 = (uint8_t)TIM1_DMABase; 02170 TIM1->DCR2 = (uint8_t)TIM1_DMABurstLength; 02171 } 02172 02173 /** 02174 * @brief Enables or disables the TIM�s DMA Requests. 02175 * @param TIM1_DMASources: specifies the DMA Request sources. 02176 * This parameter can be any combination of the following values: 02177 * @arg TIM1_DMA_Update: TIM1 update Interrupt source 02178 * @arg DMA_Trigger: TIM1 Trigger DMA source 02179 * @param NewState new state of the DMA Request sources. 02180 * This parameter can be: ENABLE or DISABLE. 02181 * @retval None. 02182 */ 02183 void TIM1_DMACmd(TIM1_DMASource_TypeDef TIM1_DMASource, FunctionalState NewState) 02184 { 02185 /* Check the parameters */ 02186 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02187 assert_param(IS_TIM1_DMA_SOURCE(TIM1_DMASource)); 02188 02189 if (NewState != DISABLE) 02190 { 02191 /* Enable the DMA sources */ 02192 TIM1->DER |= (uint8_t)TIM1_DMASource; 02193 } 02194 else 02195 { 02196 /* Disable the DMA sources */ 02197 TIM1->DER &= (uint8_t)(~TIM1_DMASource); 02198 } 02199 } 02200 02201 /** 02202 * @brief Selects the TIM1 peripheral Capture Compare DMA source. 02203 * @param NewState: new state of the Capture Compare DMA source. 02204 * This parameter can be: ENABLE or DISABLE. 02205 * @retval None 02206 */ 02207 void TIM1_SelectCCDMA(FunctionalState NewState) 02208 { 02209 /* Check the parameters */ 02210 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02211 02212 if (NewState != DISABLE) 02213 { 02214 /* Set the CCDS Bit */ 02215 TIM1->CR2 |= TIM1_CR2_CCDS; 02216 } 02217 else 02218 { 02219 /* Reset the CCDS Bit */ 02220 TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCDS); 02221 } 02222 } 02223 02224 /** 02225 * @} 02226 */ 02227 02228 /** @defgroup TIM1_Group5 Clocks management functions 02229 * @brief Clocks management functions 02230 * 02231 @verbatim 02232 =============================================================================== 02233 Clocks management functions 02234 =============================================================================== 02235 02236 @endverbatim 02237 * @{ 02238 */ 02239 02240 /** 02241 * @brief Configures the TIM1 internal Clock. 02242 * @param None 02243 * @retval None 02244 */ 02245 void TIM1_InternalClockConfig(void) 02246 { 02247 /* Disable slave mode to clock the prescaler directly with the internal clock */ 02248 TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_SMS); 02249 } 02250 02251 /** 02252 * @brief Configures the TIM1 Trigger as External Clock. 02253 * @param TIM1_TIxExternalCLKSource specifies Trigger source. 02254 * This parameter can be one of the following values: 02255 * @arg TIM1_TIxExternalCLK1Source_TI1: TI1 Edge Detector 02256 * @arg TIM1_TIxExternalCLK1Source_TI2: Filtered TIM1 Input 1 02257 * @arg TIM1_TIxExternalCLK1Source_TI1ED: Filtered TIM1 Input 2 02258 * @param TIM1_ICPolarity specifies the TIx Polarity. 02259 * This parameter can be one of the following values: 02260 * @arg TIM1_ICPolarity_Rising: Input capture polarity rising 02261 * @arg TIM1_ICPolarity_Falling: Input capture polarity falling 02262 * @param ICFilter specifies the filter value. 02263 * This parameter must be a value between 0x00 and 0x0F 02264 * @retval None 02265 */ 02266 void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, 02267 TIM1_ICPolarity_TypeDef TIM1_ICPolarity, 02268 uint8_t ICFilter) 02269 { 02270 /* Check the parameters */ 02271 assert_param(IS_TIM1_TIXCLK_SOURCE(TIM1_TIxExternalCLKSource)); 02272 assert_param(IS_TIM1_IC_POLARITY(TIM1_ICPolarity)); 02273 assert_param(IS_TIM1_IC_FILTER(ICFilter)); 02274 02275 /* Configure the TIM1 Input Clock Source */ 02276 if (TIM1_TIxExternalCLKSource == TIM1_TIxExternalCLK1Source_TI2) 02277 { 02278 TI2_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter); 02279 } 02280 else 02281 { 02282 TI1_Config(TIM1_ICPolarity, TIM1_ICSelection_DirectTI, ICFilter); 02283 } 02284 02285 /* Select the Trigger source */ 02286 TIM1_SelectInputTrigger((TIM1_TRGSelection_TypeDef)TIM1_TIxExternalCLKSource); 02287 02288 /* Select the External clock mode1 */ 02289 TIM1->SMCR |= (uint8_t)(TIM1_SlaveMode_External1); 02290 } 02291 02292 /** 02293 * @brief Configures the TIM1 External clock Mode1. 02294 * @param TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. 02295 * This parameter can be one of the following values: 02296 * @arg TIM1_ExtTRGPSC_OFF 02297 * @arg TIM1_ExtTRGPSC_DIV2 02298 * @arg TIM1_ExtTRGPSC_DIV4 02299 * @arg TIM1_ExtTRGPSC_DIV8. 02300 * @param TIM1_ExtTRGPolarity specifies the external Trigger Polarity. 02301 * This parameter can be one of the following values: 02302 * @arg TIM1_ExtTRGPolarity_Inverted 02303 * @arg TIM1_ExtTRGPolarity_NonInverted 02304 * @param ExtTRGFilter specifies the External Trigger Filter. 02305 * This parameter must be a value between 0x00 and 0x0F 02306 * @retval None 02307 */ 02308 void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, 02309 TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, 02310 uint8_t ExtTRGFilter) 02311 { 02312 /* Check the parameters */ 02313 assert_param(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler)); 02314 assert_param(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity)); 02315 assert_param(IS_TIM1_EXT_TRG_FILTER(ExtTRGFilter)); 02316 02317 /* Configure the ETR Clock source */ 02318 TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter); 02319 02320 /* Select the External clock mode1 & Select the Trigger selection : ETRF */ 02321 TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~(TIM1_SMCR_SMS | TIM1_SMCR_TS))) 02322 | (uint8_t)((uint8_t)TIM1_SlaveMode_External1 | (uint8_t) TIM1_TRGSelection_ETRF)); 02323 } 02324 02325 /** 02326 * @brief Configures the TIM1 External clock Mode2. 02327 * @param TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. 02328 * This parameter can be one of the following values: 02329 * @arg TIM1_ExtTRGPSC_OFF 02330 * @arg TIM1_ExtTRGPSC_DIV2 02331 * @arg TIM1_ExtTRGPSC_DIV4 02332 * @arg TIM1_ExtTRGPSC_DIV8. 02333 * @param TIM1_ExtTRGPolarity specifies the external Trigger Polarity. 02334 * This parameter can be one of the following values: 02335 * @arg TIM1_ExtTRGPolarity_Inverted 02336 * @arg TIM1_ExtTRGPolarity_NonInverted 02337 * @param ExtTRGFilter specifies the External Trigger Filter. 02338 * This parameter must be a value between 0x00 and 0x0F 02339 * @retval None 02340 */ 02341 void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, 02342 TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, 02343 uint8_t ExtTRGFilter) 02344 { 02345 /* Check the parameters */ 02346 assert_param(IS_TIM1_EXT_PRESCALER(TIM1_ExtTRGPrescaler)); 02347 assert_param(IS_TIM1_EXT_POLARITY(TIM1_ExtTRGPolarity)); 02348 02349 /* Configure the ETR Clock source */ 02350 TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter); 02351 02352 /* Enable the External clock mode2 */ 02353 TIM1->ETR |= TIM1_ETR_ECE; 02354 } 02355 02356 /** 02357 * @} 02358 */ 02359 02360 /** @defgroup TIM1_Group6 Synchronization management functions 02361 * @brief Synchronization management functions 02362 * 02363 @verbatim 02364 =============================================================================== 02365 Synchronization management functions 02366 =============================================================================== 02367 02368 =================================================================== 02369 TIM1 Driver: how to use it in synchronization Mode 02370 =================================================================== 02371 Case of two/several Timers 02372 ************************** 02373 1. If TIM1 is used as master to other timers use the following functions: 02374 - TIM1_SelectOutputTrigger() 02375 - TIM1_SelectMasterSlaveMode() 02376 2. If TIM1 is used as slave to other timers use the following functions: 02377 - TIM1_SelectInputTrigger() 02378 - TIM1_SelectSlaveMode() 02379 02380 Case of Timers and external trigger (TRIG pin) 02381 ******************************************** 02382 1. Configure the External trigger using TIM1_ETRConfig() 02383 2. Configure the Slave Timer using the following functions: 02384 - TIM1_SelectInputTrigger() 02385 - TIM1_SelectSlaveMode() 02386 02387 @endverbatim 02388 * @{ 02389 */ 02390 02391 /** 02392 * @brief Selects the TIM1 Input Trigger source. 02393 * @param TIM1_InputTriggerSource specifies Input Trigger source. 02394 * This parameter can be one of the following values: 02395 * @arg TIM1_TRGSelection_TIM4 02396 * @arg TIM1_TRGSelection_TIM3 02397 * @arg TIM1_TRGSelection_TIM2 02398 * @arg TIM1_TRGSelection_TI1F_ED: TI1 Edge Detector 02399 * @arg TIM1_TRGSelection_TI1FP1: Filtered Timer Input 1 02400 * @arg TIM1_TRGSelection_TI2FP2: Filtered Timer Input 2 02401 * @arg TIM1_TRGSelection_ETRF: External Trigger input 02402 * @retval None 02403 */ 02404 void TIM1_SelectInputTrigger(TIM1_TRGSelection_TypeDef TIM1_InputTriggerSource) 02405 { 02406 /* Check the parameters */ 02407 assert_param(IS_TIM1_TRIGGER_SELECTION(TIM1_InputTriggerSource)); 02408 02409 /* Select the Tgigger Source */ 02410 TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_TS)) | (uint8_t)TIM1_InputTriggerSource); 02411 } 02412 02413 /** 02414 * @brief Selects the TIM1 Trigger Output Mode. 02415 * @param TIM1_TRGOSource specifies the Trigger Output source. 02416 * This parameter can be one of the following values 02417 * @arg TIM1_TRGOSource_Reset 02418 * @arg TIM1_TRGOSource_Enable 02419 * @arg TIM1_TRGOSource_Update 02420 * @arg TIM1_TRGOSource_OC1 02421 * @arg TIM1_TRGOSource_OC1REF 02422 * @arg TIM1_TRGOSource_OC2REF 02423 * @arg TIM1_TRGOSource_OC3REF 02424 * @arg TIM1_TRGOSource_OC4REF 02425 * @retval None 02426 */ 02427 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource) 02428 { 02429 /* Check the parameters */ 02430 assert_param(IS_TIM1_TRGO_SOURCE(TIM1_TRGOSource)); 02431 /* Reset the MMS Bits & Select the TRGO source */ 02432 TIM1->CR2 = (uint8_t)((uint8_t)(TIM1->CR2 & (uint8_t)(~TIM1_CR2_MMS)) | (uint8_t) TIM1_TRGOSource); 02433 } 02434 02435 /** 02436 * @brief Selects the TIM1 Slave Mode. 02437 * @param TIM1_SlaveMode specifies the TIM1 Slave Mode. 02438 * This parameter can be one of the following values 02439 * @arg TIM1_SlaveMode_Reset 02440 * @arg TIM1_SlaveMode_Gated 02441 * @arg TIM1_SlaveMode_Trigger 02442 * @arg TIM1_SlaveMode_External1 02443 * @retval None 02444 */ 02445 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode) 02446 { 02447 /* Check the parameters */ 02448 assert_param(IS_TIM1_SLAVE_MODE(TIM1_SlaveMode)); 02449 02450 /* Reset the SMS Bits and Select the Slave Mode */ 02451 TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_SMS)) | (uint8_t)TIM1_SlaveMode); 02452 02453 } 02454 02455 /** 02456 * @brief Sets or Resets the TIM1 Master/Slave Mode. 02457 * @param NewState new state of the synchronization between TIM1 and its slaves 02458 * (through TRGO). This parameter can be ENABLE or DISABLE. 02459 * @retval None 02460 */ 02461 void TIM1_SelectMasterSlaveMode(FunctionalState NewState) 02462 { 02463 /* Check the parameters */ 02464 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02465 02466 /* Set or Reset the MSM Bit */ 02467 if (NewState != DISABLE) 02468 { 02469 TIM1->SMCR |= TIM1_SMCR_MSM; 02470 } 02471 else 02472 { 02473 TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_MSM); 02474 } 02475 } 02476 02477 /** 02478 * @brief Configures the TIM1 External Trigger. 02479 * @param TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler. 02480 * This parameter can be one of the following values: 02481 * @arg TIM1_ExtTRGPSC_OFF 02482 * @arg TIM1_ExtTRGPSC_DIV2 02483 * @arg TIM1_ExtTRGPSC_DIV4 02484 * @arg TIM1_ExtTRGPSC_DIV8. 02485 * @param TIM1_ExtTRGPolarity specifies the external Trigger Polarity. 02486 * This parameter can be one of the following values: 02487 * @arg TIM1_ExtTRGPolarity_Inverted 02488 * @arg TIM1_ExtTRGPolarity_NonInverted 02489 * @param ExtTRGFilter specifies the External Trigger Filter. 02490 * This parameter must be a value between 0x00 and 0x0F 02491 * @retval None 02492 */ 02493 void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, 02494 TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, 02495 uint8_t ExtTRGFilter) 02496 { 02497 assert_param(IS_TIM1_EXT_TRG_FILTER(ExtTRGFilter)); 02498 02499 /* Set the Prescaler, the Filter value and the Polarity */ 02500 TIM1->ETR |= (uint8_t)((uint8_t)((uint8_t) TIM1_ExtTRGPrescaler 02501 | (uint8_t) TIM1_ExtTRGPolarity) 02502 | (uint8_t) ExtTRGFilter); 02503 } 02504 02505 /** 02506 * @} 02507 */ 02508 02509 /** @defgroup TIM1_Group7 Specific interface management functions 02510 * @brief Specific interface management functions 02511 * 02512 @verbatim 02513 =============================================================================== 02514 Specific interface management functions 02515 =============================================================================== 02516 02517 @endverbatim 02518 * @{ 02519 */ 02520 02521 /** 02522 * @brief Configures the TIM1 Encoder Interface. 02523 * @param TIM1_EncoderMode specifies the TIM1 Encoder Mode. 02524 * This parameter can be one of the following values 02525 * @arg TIM1_EncoderMode_TI1: Counter counts on TI1FP1 edge 02526 * depending on TI2FP2 level. 02527 * @arg TIM1_EncoderMode_TI2: Counter counts on TI2FP2 edge 02528 * depending on TI1FP1 level. 02529 * @arg TIM1_EncoderMode_TI12: Counter counts on both TI1FP1 and 02530 * TI2FP2 edges depending on the level of the other input. 02531 * @param TIM1_IC1Polarity specifies the IC1 Polarity. 02532 * This parameter can be one of the following values: 02533 * @arg TIM1_ICPolarity_Rising: Input capture polarity rising 02534 * @arg TIM1_ICPolarity_Falling: Input capture polarity falling 02535 * @param TIM1_IC2Polarity specifies the IC2 Polarity. 02536 * This parameter can be one of the following values: 02537 * @arg TIM1_ICPolarity_Rising: Input capture polarity rising 02538 * @arg TIM1_ICPolarity_Falling: Input capture polarity falling 02539 * @retval None 02540 */ 02541 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode, 02542 TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, 02543 TIM1_ICPolarity_TypeDef TIM1_IC2Polarity) 02544 { 02545 /* Check the parameters */ 02546 assert_param(IS_TIM1_ENCODER_MODE(TIM1_EncoderMode)); 02547 assert_param(IS_TIM1_IC_POLARITY(TIM1_IC1Polarity)); 02548 assert_param(IS_TIM1_IC_POLARITY(TIM1_IC2Polarity)); 02549 02550 /* Set the TI1 and the TI2 Polarities */ 02551 if (TIM1_IC1Polarity != TIM1_ICPolarity_Rising) 02552 { 02553 TIM1->CCER1 |= TIM1_CCER1_CC1P; 02554 } 02555 else 02556 { 02557 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P); 02558 } 02559 02560 if (TIM1_IC2Polarity != TIM1_ICPolarity_Rising) 02561 { 02562 TIM1->CCER1 |= TIM1_CCER1_CC2P; 02563 } 02564 else 02565 { 02566 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P); 02567 } 02568 /* Set the encoder Mode */ 02569 TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(TIM1_SMCR_MSM | TIM1_SMCR_TS)) | (uint8_t) TIM1_EncoderMode); 02570 02571 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ 02572 TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_CCxS)) | (uint8_t) CCMR_TIxDirect_Set); 02573 TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_CCxS)) | (uint8_t) CCMR_TIxDirect_Set); 02574 02575 } 02576 02577 /** 02578 * @brief Enables or Disables the TIM�s Hall sensor interface. 02579 * @param NewState : The new state of the TIM1 Hall sensor interface. 02580 * This parameter can be ENABLE or DISABLE 02581 * @retval None 02582 */ 02583 void TIM1_SelectHallSensor(FunctionalState NewState) 02584 { 02585 /* Check the parameters */ 02586 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02587 02588 /* Set or Reset the TI1S Bit */ 02589 if (NewState != DISABLE) 02590 { 02591 TIM1->CR2 |= TIM1_CR2_TI1S; 02592 } 02593 else 02594 { 02595 TIM1->CR2 &= (uint8_t)(~TIM1_CR2_TI1S); 02596 } 02597 } 02598 02599 /** 02600 * @} 02601 */ 02602 02603 /** 02604 * @brief Configure the TI1 as Input. 02605 * @param TIM1_ICPolarity The Input Polarity. 02606 * This parameter can be one of the following values: 02607 * @arg TIM1_ICPolarity_Rising: Input capture polarity rising 02608 * @arg TIM1_ICPolarity_Falling: Input capture polarity falling 02609 * @param TIM1_ICSelection specifies the input to be used. 02610 * This parameter can be one of the following values: 02611 * @arg TIM1_ICSelection_DirectTI: TIM1 Input 1 is selected to be connected to IC1. 02612 * @arg TIM1_ICSelection_IndirectTI: TIM1 Input 1 is selected to be connected to IC2. 02613 * @param TIM1_ICFilter Specifies the Input Capture Filter. 02614 * This parameter must be a value between 0x00 and 0x0F. 02615 * @retval None 02616 */ 02617 static void TI1_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter) 02618 { 02619 02620 /* Disable the Channel 1: Reset the CCE Bit */ 02621 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E); 02622 02623 /* Select the Input and set the filter */ 02624 TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF))) 02625 | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4)))); 02626 02627 02628 02629 /* Select the Polarity */ 02630 if (TIM1_ICPolarity != TIM1_ICPolarity_Rising) 02631 { 02632 TIM1->CCER1 |= TIM1_CCER1_CC1P; 02633 } 02634 else 02635 { 02636 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P); 02637 } 02638 02639 /* Set the CCE Bit */ 02640 TIM1->CCER1 |= TIM1_CCER1_CC1E; 02641 } 02642 02643 /** 02644 * @brief Configure the TI2 as Input. 02645 * @param TIM1_ICPolarity The Input Polarity. 02646 * This parameter can be one of the following values: 02647 * @arg TIM1_ICPolarity_Rising: Input capture polarity rising 02648 * @arg TIM1_ICPolarity_Falling: Input capture polarity falling 02649 * @param TIM1_ICSelection specifies the input to be used. 02650 * This parameter can be one of the following values: 02651 * @arg TIM1_ICSelection_DirectTI: TIM1 Input 2 is selected to be connected to IC2. 02652 * @arg TIM1_ICSelection_IndirectTI: TIM1 Input 2 is selected to be connected to IC1. 02653 * @param TIM1_ICFilter Specifies the Input Capture Filter. 02654 * This parameter must be a value between 0x00 and 0x0F. 02655 * @retval None 02656 */ 02657 static void TI2_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter) 02658 { 02659 /* Disable the Channel 2: Reset the CCE Bit */ 02660 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E); 02661 02662 /* Select the Input and set the filter */ 02663 TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF))) 02664 | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4)))); 02665 /* Select the Polarity */ 02666 if (TIM1_ICPolarity != TIM1_ICPolarity_Rising) 02667 { 02668 TIM1->CCER1 |= TIM1_CCER1_CC2P; 02669 } 02670 else 02671 { 02672 TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P); 02673 } 02674 /* Set the CCE Bit */ 02675 TIM1->CCER1 |= TIM1_CCER1_CC2E; 02676 } 02677 02678 /** 02679 * @brief Configure the TI3 as Input. 02680 * @param TIM1_ICPolarity The Input Polarity. 02681 * This parameter can be one of the following values: 02682 * @arg TIM1_ICPolarity_Rising: Input capture polarity rising 02683 * @arg TIM1_ICPolarity_Falling: Input capture polarity falling 02684 * @param TIM1_ICSelection specifies the input to be used. 02685 * This parameter can be one of the following values: 02686 * @arg TIM1_ICSelection_DirectTI: TIM1 Input 3 is selected to 02687 * be connected to IC3. 02688 * @param TIM1_ICFilter Specifies the Input Capture Filter. 02689 * This parameter must be a value between 0x00 and 0x0F. 02690 * @retval None 02691 */ 02692 static void TI3_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter) 02693 { 02694 /* Disable the Channel 3: Reset the CCE Bit */ 02695 TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E); 02696 02697 /* Select the Input and set the filter */ 02698 TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF))) 02699 | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4)))); 02700 02701 /* Select the Polarity */ 02702 if (TIM1_ICPolarity != TIM1_ICPolarity_Rising) 02703 { 02704 TIM1->CCER2 |= TIM1_CCER2_CC3P; 02705 } 02706 else 02707 { 02708 TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P); 02709 } 02710 /* Set the CCE Bit */ 02711 TIM1->CCER2 |= TIM1_CCER2_CC3E; 02712 } 02713 02714 /** 02715 * @brief Configure the TI4 as Input. 02716 * @param TIM1_ICPolarity The Input Polarity. 02717 * This parameter can be one of the following values: 02718 * @arg TIM1_ICPolarity_Rising: Input capture polarity rising 02719 * @arg TIM1_ICPolarity_Falling: Input capture polarity falling 02720 * @param TIM1_ICSelection specifies the input to be used. 02721 * This parameter can be one of the following values: 02722 * @arg TIM1_ICSelection_IndirectTI: TIM1 Input 4 is selected to be connected to IC3. 02723 * @param TIM1_ICFilter Specifies the Input Capture Filter. 02724 * This parameter must be a value between 0x00 and 0x0F. 02725 * @retval None 02726 */ 02727 static void TI4_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection, uint8_t TIM1_ICFilter) 02728 { 02729 02730 /* Disable the Channel 4: Reset the CCE Bit */ 02731 TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E); 02732 02733 /* Select the Input and set the filter */ 02734 TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF))) 02735 | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4)))); 02736 02737 /* Select the Polarity */ 02738 if (TIM1_ICPolarity != TIM1_ICPolarity_Rising) 02739 { 02740 TIM1->CCER2 |= TIM1_CCER2_CC4P; 02741 } 02742 else 02743 { 02744 TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4P); 02745 } 02746 02747 /* Set the CCE Bit */ 02748 TIM1->CCER2 |= TIM1_CCER2_CC4E; 02749 } 02750 02751 02752 /** 02753 * @} 02754 */ 02755 02756 /** 02757 * @} 02758 */ 02759 02760 /** 02761 * @} 02762 */ 02763 02764 /** 02765 * @} 02766 */ 02767 02768 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/