STM8L15x Standard Peripherals Drivers
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stm8l15x_pwr.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_pwr.c 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file provides firmware functions to manage the following 00008 * functionalities of the Power Controller (PWR) peripheral: 00009 * - PVD configuration 00010 * - Ultra Low Power mode configuration 00011 * - Interrupts and flags management 00012 * 00013 ****************************************************************************** 00014 * @attention 00015 * 00016 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00017 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00018 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00019 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00020 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00021 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00022 * 00023 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00024 ****************************************************************************** 00025 */ 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm8l15x_pwr.h" 00029 00030 /** @addtogroup STM8L15x_StdPeriph_Driver 00031 * @{ 00032 */ 00033 00034 /** @defgroup PWR 00035 * @brief PWR driver modules 00036 * @{ 00037 */ 00038 00039 /* Private typedef -----------------------------------------------------------*/ 00040 /* Private define ------------------------------------------------------------*/ 00041 /* Private macro -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 /* Private function prototypes -----------------------------------------------*/ 00044 /* Private functions ---------------------------------------------------------*/ 00045 00046 /** @defgroup PWR_Private_Functions 00047 * @{ 00048 */ 00049 00050 /** @defgroup PWR_Group1 PVD configuration functions 00051 * @brief PVD configuration functions 00052 * 00053 @verbatim 00054 =============================================================================== 00055 PVD configuration functions 00056 =============================================================================== 00057 00058 - The PVD is used to monitor the VDD power supply by comparing it to a threshold 00059 selected by the PVD Level (PLS[2:0] bits in the PWR_CSR1). 00060 - The PVD can use an external input analog voltage (PVD_IN) which is compared 00061 internally to VREFINT. The PVD_IN (PE6) has to be configured in Analog mode 00062 when PWR_PVDLevel_PVDIn is selected (PLS[2:0] = 111). 00063 - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 00064 PVD threshold. An interrupt is generated in case enabled for PVD. 00065 - The PVD interrup event has the capability to wake up the CPU from Halt/Active Halt modes. 00066 00067 @endverbatim 00068 * @{ 00069 */ 00070 00071 /** 00072 * @brief Deinitializes the PWR peripheral registers to their default reset values. 00073 * @param None 00074 * @retval None 00075 */ 00076 void PWR_DeInit(void) 00077 { 00078 PWR->CSR1 = PWR_CSR1_PVDIF; 00079 PWR->CSR2 = PWR_CSR2_RESET_VALUE; 00080 } 00081 00082 /** 00083 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 00084 * @param PWR_PVDLevel: specifies the PVD detection level 00085 * This parameter can be one of the following values: 00086 * @arg PWR_PVDLevel_1V85: PVD detection level set to 1.85V 00087 * @arg PWR_PVDLevel_2V05: PVD detection level set to 2.05V 00088 * @arg PWR_PVDLevel_2V26: PVD detection level set to 2.26V 00089 * @arg PWR_PVDLevel_2V45: PVD detection level set to 2.45V 00090 * @arg PWR_PVDLevel_2V65: PVD detection level set to 2.65V 00091 * @arg PWR_PVDLevel_2V85: PVD detection level set to 2.85V 00092 * @arg PWR_PVDLevel_3V05: PVD detection level set to 3.05V 00093 * @arg PWR_PVDLevel_PVDIn: External input analog voltage (Compare internally to VREFINT) 00094 * @retval None 00095 */ 00096 void PWR_PVDLevelConfig(PWR_PVDLevel_TypeDef PWR_PVDLevel) 00097 { 00098 /* Check the parameters */ 00099 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 00100 00101 /* Clear the PVD level */ 00102 PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PLS); 00103 00104 /* Configure the PVD level */ 00105 PWR->CSR1 |= PWR_PVDLevel; 00106 00107 } 00108 00109 /** 00110 * @brief Enables or disables the Power Voltage Detector(PVD). 00111 * @param NewState: new state of the PVD. 00112 * This parameter can be: ENABLE or DISABLE. 00113 * @retval None 00114 */ 00115 void PWR_PVDCmd(FunctionalState NewState) 00116 { 00117 /* Check the parameters */ 00118 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00119 00120 if (NewState != DISABLE) 00121 { 00122 /* Enable the PWR PVD */ 00123 PWR->CSR1 |= PWR_CSR1_PVDE; 00124 } 00125 else 00126 { 00127 /* Disable the PWR PVD */ 00128 PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PVDE); 00129 } 00130 } 00131 00132 /** 00133 * @} 00134 */ 00135 00136 /** @defgroup PWR_Group2 Ultra Low Power mode configuration functions 00137 * @brief Ultra Low Power mode configuration functions 00138 * 00139 @verbatim 00140 =============================================================================== 00141 Ultra Low Power mode configuration functions 00142 =============================================================================== 00143 00144 - The internal voltage reference consumption is not negligible, in particular 00145 in Halt and Active Halt modes. To reduce power consumption, use the PWR_UltraLowPowerCmd() 00146 function (ULP bit (Ultra low power) in the PWR_CSR2 register) to disable the 00147 internal voltage reference. However, in this case, when exiting from the 00148 Halt/Active Halt modes, the functions managed through the internal voltage reference 00149 are not reliable during the internal voltage reference startup time (up to 3 ms). 00150 To reduce the wakeup time, the device can exit from Halt/Active Halt modes without 00151 waiting for the internal voltage reference startup time. This is performed 00152 by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast 00153 wakeup) in the PWR_CSR2 register) before entering Halt/Active Halt mode. 00154 00155 @endverbatim 00156 * @{ 00157 */ 00158 00159 /** 00160 * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode. 00161 * @param NewState: new state of the Fast WakeUp functionality. 00162 * This parameter can be: ENABLE or DISABLE. 00163 * @retval None 00164 */ 00165 void PWR_FastWakeUpCmd(FunctionalState NewState) 00166 { 00167 /* Check the parameters */ 00168 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00169 00170 if (NewState != DISABLE) 00171 { 00172 /* Enable the PWR FWU */ 00173 PWR->CSR2 |= PWR_CSR2_FWU; 00174 } 00175 else 00176 { 00177 /* Disable the PWR FWU */ 00178 PWR->CSR2 &= (uint8_t)(~PWR_CSR2_FWU); 00179 } 00180 } 00181 00182 /** 00183 * @brief Enables or disables the Ultra Low Power mode. 00184 * @param NewState: new state of the Ultra Low Power mode. 00185 * This parameter can be: ENABLE or DISABLE. 00186 * @retval None 00187 */ 00188 void PWR_UltraLowPowerCmd(FunctionalState NewState) 00189 { 00190 /* Check the parameters */ 00191 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00192 00193 if (NewState != DISABLE) 00194 { 00195 /* Enable the PWR ULP */ 00196 PWR->CSR2 |= PWR_CSR2_ULP; 00197 } 00198 else 00199 { 00200 /* Disable the PWR ULP */ 00201 PWR->CSR2 &= (uint8_t)(~PWR_CSR2_ULP); 00202 } 00203 } 00204 00205 /** 00206 * @} 00207 */ 00208 00209 /** @defgroup PWR_Group3 Interrupts and Flags management functions 00210 * @brief Interrupts and Flags management functions 00211 * 00212 @verbatim 00213 =============================================================================== 00214 Interrupts and Flags management functions 00215 =============================================================================== 00216 00217 @endverbatim 00218 * @{ 00219 */ 00220 00221 /** 00222 * @brief Configures the Programmable Voltage Detector (PVD) Interrupt . 00223 * @param NewState : Indicates the new state of the PVD interrupt. 00224 * @retval None 00225 */ 00226 void PWR_PVDITConfig(FunctionalState NewState) 00227 { 00228 /* Check the parameters */ 00229 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00230 00231 if (NewState != DISABLE) 00232 { 00233 /* Enable the PVD interrupt */ 00234 PWR->CSR1 |= PWR_CSR1_PVDIEN; 00235 } 00236 else 00237 { 00238 /* Disable the PVD interrupt */ 00239 PWR->CSR1 &= (uint8_t)(~PWR_CSR1_PVDIEN); 00240 } 00241 } 00242 00243 /** 00244 * @brief Checks whether the specified PWR flag is set or not. 00245 * @param PWR_FLAG: specifies the flag to check. 00246 * This parameter can be one of the following values: 00247 * @arg PWR_FLAG_PVDOF: PVD Output. This flag is valid only if PVD is enabled 00248 * by the PWR_PVDCmd() function. 00249 * @arg PWR_FLAG_VREFINTF: Internal Voltage Reference Ready flag. This 00250 * flag indicates the state of the internal voltage reference, VREFINT. 00251 * @arg PWR_FLAG_PVDIF: PVD Interrupt Flag, it's set by hardware when a PVD 00252 * event occurs 00253 * @retval The new state of PWR_FLAG (SET or RESET). 00254 */ 00255 FlagStatus PWR_GetFlagStatus(PWR_FLAG_TypeDef PWR_FLAG) 00256 { 00257 FlagStatus bitstatus = RESET; 00258 00259 /* Check the parameters */ 00260 assert_param(IS_PWR_FLAG(PWR_FLAG)); 00261 00262 if ((PWR_FLAG & PWR_FLAG_VREFINTF) != 0) 00263 { 00264 if ((PWR->CSR2 & PWR_CR2_VREFINTF) != (uint8_t)RESET ) 00265 { 00266 bitstatus = SET; 00267 } 00268 else 00269 { 00270 bitstatus = RESET; 00271 } 00272 } 00273 else 00274 { 00275 if ((PWR->CSR1 & PWR_FLAG) != (uint8_t)RESET ) 00276 { 00277 bitstatus = SET; 00278 } 00279 else 00280 { 00281 bitstatus = RESET; 00282 } 00283 } 00284 00285 /* Return the flag status */ 00286 return((FlagStatus)bitstatus); 00287 } 00288 00289 /** 00290 * @brief Clears the PWR PVDIF Flag. 00291 * @param None 00292 * @retval None 00293 */ 00294 void PWR_PVDClearFlag(void) 00295 { 00296 /* Set the PVDIF to clear it */ 00297 PWR->CSR1 |= PWR_CSR1_PVDIF; 00298 } 00299 00300 /** 00301 * @brief Checks whether the PVD interrupt has occurred or not. 00302 * @param None 00303 * @retval The new state of the PVD Interrupt (SET or RESET). 00304 */ 00305 ITStatus PWR_PVDGetITStatus(void) 00306 { 00307 ITStatus bitstatus = RESET; 00308 00309 uint8_t PVD_itStatus = 0x0, PVD_itEnable = 0x0; 00310 00311 PVD_itStatus = (uint8_t)(PWR->CSR1 & (uint8_t)PWR_CSR1_PVDIF); 00312 PVD_itEnable = (uint8_t)(PWR->CSR1 & (uint8_t)PWR_CSR1_PVDIEN); 00313 00314 if ((PVD_itStatus != (uint8_t)RESET ) && (PVD_itEnable != (uint8_t)RESET)) 00315 { 00316 bitstatus = (ITStatus)SET; 00317 } 00318 else 00319 { 00320 bitstatus = (ITStatus)RESET; 00321 } 00322 return ((ITStatus)bitstatus); 00323 } 00324 00325 /** 00326 * @brief Clears the PWR interrupt pending bit. 00327 * @param None 00328 * @retval None 00329 */ 00330 void PWR_PVDClearITPendingBit(void) 00331 { 00332 /* Set the PVDIF to clear it */ 00333 PWR->CSR1 |= PWR_CSR1_PVDIF; 00334 } 00335 00336 /** 00337 * @} 00338 */ 00339 00340 /** 00341 * @} 00342 */ 00343 00344 /** 00345 * @} 00346 */ 00347 00348 /** 00349 * @} 00350 */ 00351 00352 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/