00001 /**
00002   ********************************************************************************
00003   * @file    stm8l15x_iwdg.c
00004   * @author  MCD Application Team
00005   * @version V1.5.0
00006   * @date    13-May-2011
00007   * @brief   This file provides firmware functions to manage the following 
00008   *          functionalities of the Independent watchdog (IWDG) peripheral:           
00009   *           - Prescaler and Counter configuration
00010   *           - IWDG activation
00011   *
00012   *  @verbatim  
00013   *  
00014   *          ===================================================================
00015   *                                     IWDG features
00016   *          ===================================================================
00017   *    
00018   *          The IWDG can be started by either software or hardware (configurable
00019   *          through option byte).
00020   *            
00021   *          The IWDG is clocked by its own dedicated low-speed clock (LSI) and
00022   *          thus stays active even if the main clock fails.
00023   *          Once the IWDG is started, the LSI is forced ON and cannot be disabled
00024   *          (LSI cannot be disabled too), and the counter starts counting down from 
00025   *          the reset value of 0xFF. When it reaches the end of count value (0x00)
00026   *          a system reset is generated.
00027   *          The IWDG counter should be reloaded at regular intervals to prevent
00028   *          an MCU reset.
00029   *                           
00030   *          The IWDG is implemented in the VDD voltage domain that is still functional
00031   *          in Halt and Active Halt mode depending on the configuration of the IWDG_HALT
00032   *          option byte. (IWDG reset can wake-up from Halt).          
00033   *            
00034   *          IWDGF flag in RST_SR register can be used to inform when a IWDG
00035   *          reset occurs.
00036   *            
00037   *          Min-max timeout value @38KHz (LSI): 0.10 ms / ~1.724s
00038   *          The IWDG timeout may vary due to LSI frequency dispersion. STM8L15x
00039   *          devices provide the capability to measure the LSI frequency (LSI clock
00040   *          connected internally to TIM2 CH1 input capture). The measured value
00041   *          can be used to have an IWDG timeout with an acceptable accuracy. 
00042   *          For more information, please refer to the STM8L15x Reference manual
00043   *          
00044   *                            
00045   *          ===================================================================
00046   *                                 How to use this driver
00047   *          ===================================================================
00048   *          1. Enable write access to IWDG_PR and IWDG_RLR registers using
00049   *             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
00050   *               
00051   *          2. Configure the IWDG prescaler using IWDG_SetPrescaler() function
00052   *            
00053   *          3. Configure the IWDG counter value using IWDG_SetReload() function.
00054   *             This value will be loaded in the IWDG counter each time the counter
00055   *             is reloaded, then the IWDG will start counting down from this value.
00056   *            
00057   *          4. Start the IWDG using IWDG_Enable() function, when the IWDG is used
00058   *             in software mode (no need to enable the LSI, it will be enabled
00059   *             by hardware)
00060   *             
00061   *          5. Then the application program must reload the IWDG counter at regular
00062   *             intervals during normal operation to prevent an MCU reset, using
00063   *             IWDG_ReloadCounter() function.      
00064   *          
00065   *  @endverbatim
00066   *    
00067   ******************************************************************************
00068   * @attention
00069   *
00070   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00071   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00072   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00073   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00074   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00075   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00076   *
00077   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00078   ******************************************************************************
00079   */
00080 
00081 /* Includes ------------------------------------------------------------------*/
00082 #include "stm8l15x_iwdg.h"
00083 
00084 /** @addtogroup STM8L15x_StdPeriph_Driver
00085   * @{
00086   */
00087   
00088 /** @defgroup IWDG 
00089   * @brief IWDG driver modules
00090   * @{
00091   */ 
00092 /* Private typedef -----------------------------------------------------------*/
00093 /* Private define ------------------------------------------------------------*/
00094 /* Private macro -------------------------------------------------------------*/
00095 /* Private function prototypes -----------------------------------------------*/
00096 /* Private functions ---------------------------------------------------------*/
00097 
00098 /** @defgroup IWDG_Private_Functions
00099   * @{
00100   */
00101 
00102 /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
00103  *  @brief   Prescaler and Counter configuration functions
00104  *
00105 @verbatim   
00106  ===============================================================================
00107                   Prescaler and Counter configuration functions
00108  ===============================================================================  
00109 
00110 @endverbatim
00111   * @{
00112   */
00113   
00114 /**
00115   * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
00116   * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
00117   *          This parameter can be one of the following values:
00118   *            @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
00119   *            @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
00120   * @retval None
00121   */
00122 void IWDG_WriteAccessCmd(IWDG_WriteAccess_TypeDef IWDG_WriteAccess)
00123 {
00124   /* Check the parameters */
00125   assert_param(IS_IWDG_WRITE_ACCESS_MODE(IWDG_WriteAccess));
00126   IWDG->KR = IWDG_WriteAccess; /* Write Access */
00127 }
00128 
00129 /**
00130   * @brief  Sets IWDG Prescaler value.
00131   * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
00132   *          This parameter can be one of the following values:
00133   *            @arg IWDG_Prescaler_4: IWDG prescaler set to 4
00134   *            @arg IWDG_Prescaler_8: IWDG prescaler set to 8
00135   *            @arg IWDG_Prescaler_16: IWDG prescaler set to 16
00136   *            @arg IWDG_Prescaler_32: IWDG prescaler set to 32
00137   *            @arg IWDG_Prescaler_64: IWDG prescaler set to 64
00138   *            @arg IWDG_Prescaler_128: IWDG prescaler set to 128
00139   *            @arg IWDG_Prescaler_256: IWDG prescaler set to 256
00140   * @retval None
00141   */
00142 void IWDG_SetPrescaler(IWDG_Prescaler_TypeDef IWDG_Prescaler)
00143 {
00144   /* Check the parameters */
00145   assert_param(IS_IWDG_PRESCALER_VALUE(IWDG_Prescaler));
00146   IWDG->PR = IWDG_Prescaler;
00147 }
00148 
00149 /**
00150   * @brief  Sets IWDG Reload value.
00151   * @note   Write access should be enabled
00152   * @param  IWDG_Reload : Reload register value.
00153   *         This parameter must be a number between 0 and 0xFF.
00154   * @retval None
00155   */
00156 void IWDG_SetReload(uint8_t IWDG_Reload)
00157 {
00158   IWDG->RLR = IWDG_Reload;
00159 }
00160 
00161 /**
00162   * @brief  Reloads IWDG counter with value defined in the reload register
00163   *         (write access to IWDG_PR and IWDG_RLR registers disabled).
00164   * @param  None
00165   * @retval None
00166   */
00167 void IWDG_ReloadCounter(void)
00168 {
00169   IWDG->KR = IWDG_KEY_REFRESH;
00170 }
00171 
00172 /**
00173   * @}
00174   */
00175 
00176 /** @defgroup IWDG_Group2 IWDG activation function
00177  *  @brief   IWDG activation function 
00178  *
00179 @verbatim   
00180  ===============================================================================
00181                           IWDG activation function
00182  ===============================================================================  
00183 
00184 @endverbatim
00185   * @{
00186   */
00187 
00188 /**
00189   * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
00190   * @param  None
00191   * @retval None
00192   */
00193 void IWDG_Enable(void)
00194 {
00195   IWDG->KR = IWDG_KEY_ENABLE;
00196 }
00197 
00198 /**
00199   * @}
00200   */
00201 
00202 /**
00203   * @}
00204   */
00205   
00206 /**
00207   * @}
00208   */
00209 
00210 /**
00211   * @}
00212   */
00213 
00214 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/