STM8L15x Standard Peripherals Drivers
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stm8l15x_itc.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_itc.c 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file provides firmware functions to manage the following 00008 * functionality of the Interrupt controller (ITC) peripheral: 00009 * - Configuration and management 00010 ****************************************************************************** 00011 * @attention 00012 * 00013 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00014 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00015 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00016 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00017 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00018 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00019 * 00020 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00021 ****************************************************************************** 00022 */ 00023 00024 /* Includes ------------------------------------------------------------------*/ 00025 #include "stm8l15x_itc.h" 00026 00027 /** @addtogroup STM8L15x_StdPeriph_Driver 00028 * @{ 00029 */ 00030 00031 /** @defgroup ITC 00032 * @brief ITC driver modules 00033 * @{ 00034 */ 00035 /* Private typedef -----------------------------------------------------------*/ 00036 /* Private define ------------------------------------------------------------*/ 00037 /* Private macro -------------------------------------------------------------*/ 00038 /* Private function prototypes -----------------------------------------------*/ 00039 /* Private functions ---------------------------------------------------------*/ 00040 00041 /** @defgroup ITC_Private_Functions 00042 * @{ 00043 */ 00044 00045 /** 00046 * @brief Utility function used to read CC register. 00047 * @param None 00048 * @retval CPU CC register value 00049 */ 00050 uint8_t ITC_GetCPUCC(void) 00051 { 00052 #ifdef _COSMIC_ 00053 _asm("push cc"); 00054 _asm("pop a"); 00055 return; /* Ignore compiler warning, the returned value is in A register */ 00056 #elif defined _RAISONANCE_ /* _RAISONANCE_ */ 00057 return _getCC_(); 00058 #else /* _IAR_ */ 00059 asm("push cc"); 00060 asm("pop a"); /* Ignore compiler warning, the returned value is in A register */ 00061 #endif /* _COSMIC_*/ 00062 } 00063 00064 /** @defgroup ITC_Group1 ITC configuration and management functions 00065 * @brief ITC configuration and management functions 00066 * 00067 @verbatim 00068 =============================================================================== 00069 ITC configuration and management functions 00070 =============================================================================== 00071 00072 @endverbatim 00073 * @{ 00074 */ 00075 00076 /** 00077 * @brief Deinitializes the ITC registers to their default reset value. 00078 * @param None 00079 * @retval None 00080 */ 00081 void ITC_DeInit(void) 00082 { 00083 ITC->ISPR1 = ITC_SPRX_RESET_VALUE; 00084 ITC->ISPR2 = ITC_SPRX_RESET_VALUE; 00085 ITC->ISPR3 = ITC_SPRX_RESET_VALUE; 00086 ITC->ISPR4 = ITC_SPRX_RESET_VALUE; 00087 ITC->ISPR5 = ITC_SPRX_RESET_VALUE; 00088 ITC->ISPR6 = ITC_SPRX_RESET_VALUE; 00089 ITC->ISPR7 = ITC_SPRX_RESET_VALUE; 00090 ITC->ISPR8 = ITC_SPRX_RESET_VALUE; 00091 } 00092 00093 /** 00094 * @brief Gets the interrupt software priority bits (I1, I0) value from CPU CC register. 00095 * @param None 00096 * @retval The interrupt software priority bits value. 00097 */ 00098 uint8_t ITC_GetSoftIntStatus(void) 00099 { 00100 return ((uint8_t)(ITC_GetCPUCC() & CPU_SOFT_INT_DISABLED)); 00101 } 00102 00103 /** 00104 * @brief Gets the software priority of the specified interrupt source. 00105 * @param IRQn : Specifies the peripheral interrupt source. 00106 * @retval Specifies the software priority of the interrupt source. 00107 */ 00108 ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(IRQn_TypeDef IRQn) 00109 { 00110 uint8_t Value = 0; 00111 uint8_t Mask = 0; 00112 00113 /* Check function parameters */ 00114 assert_param(IS_ITC_IRQ(IRQn)); 00115 00116 /* Define the mask corresponding to the bits position in the SPR register */ 00117 Mask = (uint8_t)(0x03U << ((IRQn % 4U) * 2U)); 00118 00119 switch (IRQn) 00120 { 00121 case FLASH_IRQn: 00122 case DMA1_CHANNEL0_1_IRQn: 00123 case DMA1_CHANNEL2_3_IRQn: 00124 Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */ 00125 break; 00126 00127 case EXTIE_F_PVD_IRQn: 00128 #ifdef STM8L15X_MD 00129 case RTC_IRQn: 00130 case EXTIB_IRQn: 00131 case EXTID_IRQn: 00132 #elif defined (STM8L15X_LD) 00133 case RTC_CSSLSE_IRQn: 00134 case EXTIB_IRQn: 00135 case EXTID_IRQn: 00136 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00137 case RTC_CSSLSE_IRQn: 00138 case EXTIB_G_IRQn: 00139 case EXTID_H_IRQn: 00140 #endif /* STM8L15X_MD */ 00141 Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */ 00142 break; 00143 00144 case EXTI0_IRQn: 00145 case EXTI1_IRQn: 00146 case EXTI2_IRQn: 00147 case EXTI3_IRQn: 00148 Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */ 00149 break; 00150 00151 case EXTI4_IRQn: 00152 case EXTI5_IRQn: 00153 case EXTI6_IRQn: 00154 case EXTI7_IRQn: 00155 Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */ 00156 break; 00157 00158 #ifdef STM8L15X_LD 00159 case SWITCH_CSS_IRQn: 00160 #else 00161 case SWITCH_CSS_BREAK_DAC_IRQn: 00162 #endif /* STM8L15X_LD */ 00163 case ADC1_COMP_IRQn: 00164 #ifdef STM8L15X_MD 00165 case LCD_IRQn: 00166 case TIM2_UPD_OVF_TRG_BRK_IRQn: 00167 #elif defined (STM8L15X_LD) 00168 case TIM2_UPD_OVF_TRG_BRK_IRQn: 00169 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00170 case LCD_AES_IRQn: 00171 case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn: 00172 #endif /* STM8L15X_MD */ 00173 Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */ 00174 break; 00175 00176 #ifndef STM8L15X_LD 00177 case TIM1_UPD_OVF_TRG_IRQn: 00178 #endif /* STM8L15X_LD */ 00179 #if defined (STM8L15X_MD) || defined (STM8L15X_LD) 00180 case TIM2_CC_IRQn: 00181 case TIM3_UPD_OVF_TRG_BRK_IRQn : 00182 case TIM3_CC_IRQn: 00183 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00184 case TIM2_CC_USART2_RX_IRQn: 00185 case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn : 00186 case TIM3_CC_USART3_RX_IRQn: 00187 #endif /* STM8L15X_MD */ 00188 Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */ 00189 break; 00190 00191 #ifndef STM8L15X_LD 00192 case TIM1_CC_IRQn: 00193 #endif /* STM8L15X_LD */ 00194 case TIM4_UPD_OVF_TRG_IRQn: 00195 case SPI1_IRQn: 00196 #if defined (STM8L15X_MD) || defined (STM8L15X_LD) 00197 case USART1_TX_IRQn: 00198 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00199 case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn: 00200 #endif /* STM8L15X_MD || STM8L15X_LD */ 00201 Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */ 00202 break; 00203 00204 #if defined (STM8L15X_MD) || defined (STM8L15X_LD) 00205 case USART1_RX_IRQn: 00206 case I2C1_IRQn: 00207 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00208 case USART1_RX_TIM5_CC_IRQn: 00209 case I2C1_SPI2_IRQn: 00210 #endif /* STM8L15X_MD || STM8L15X_LD*/ 00211 Value = (uint8_t)(ITC->ISPR8 & Mask); /* Read software priority */ 00212 break; 00213 00214 default: 00215 break; 00216 } 00217 00218 Value >>= (uint8_t)((IRQn % 4u) * 2u); 00219 00220 return((ITC_PriorityLevel_TypeDef)Value); 00221 00222 } 00223 00224 /** 00225 * @brief Sets the software priority of the specified interrupt source. 00226 * @note The modification of the software priority is only possible when 00227 * the interrupts are disabled. 00228 * @note The normal behavior is to disable the interrupt before calling 00229 * this function, and re-enable it after. 00230 * @note The priority level 0 cannot be set (see product specification 00231 * for more details). 00232 * @param IRQn : Specifies the peripheral interrupt source. 00233 * @param ITC_PriorityLevel : Specifies the software priority value to set 00234 * This parameter can be one of the following values: 00235 * @arg ITC_PriorityLevel_0: Software priority level 0 (cannot be written) 00236 * @arg ITC_PriorityLevel_1: Software priority level 1 00237 * @arg ITC_PriorityLevel_2: Software priority level 2 00238 * @arg ITC_PriorityLevel_3: Software priority level 3 00239 * @retval None 00240 */ 00241 void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel) 00242 { 00243 uint8_t Mask = 0; 00244 uint8_t NewPriority = 0; 00245 00246 /* Check function parameters */ 00247 assert_param(IS_ITC_IRQ(IRQn)); 00248 assert_param(IS_ITC_PRIORITY(ITC_PriorityLevel)); 00249 00250 /* Check if interrupts are disabled */ 00251 assert_param(IS_ITC_INTERRUPTS_DISABLED); 00252 00253 /* Define the mask corresponding to the bits position in the SPR register */ 00254 /* The mask is reversed in order to clear the 2 bits after more easily */ 00255 Mask = (uint8_t)(~(uint8_t)(0x03U << ((IRQn % 4U) * 2U))); 00256 /* Define the new priority to write */ 00257 NewPriority = (uint8_t)((uint8_t)(ITC_PriorityLevel) << ((IRQn % 4U) * 2U)); 00258 00259 switch (IRQn) 00260 { 00261 case FLASH_IRQn: 00262 case DMA1_CHANNEL0_1_IRQn: 00263 case DMA1_CHANNEL2_3_IRQn: 00264 ITC->ISPR1 &= Mask; 00265 ITC->ISPR1 |= NewPriority; 00266 break; 00267 00268 case EXTIE_F_PVD_IRQn: 00269 #ifdef STM8L15X_MD 00270 case RTC_IRQn: 00271 case EXTIB_IRQn: 00272 case EXTID_IRQn: 00273 #elif defined (STM8L15X_LD) 00274 case RTC_CSSLSE_IRQn: 00275 case EXTIB_IRQn: 00276 case EXTID_IRQn: 00277 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00278 case RTC_CSSLSE_IRQn: 00279 case EXTIB_G_IRQn: 00280 case EXTID_H_IRQn: 00281 #endif /* STM8L15X_MD */ 00282 ITC->ISPR2 &= Mask; 00283 ITC->ISPR2 |= NewPriority; 00284 break; 00285 00286 case EXTI0_IRQn: 00287 case EXTI1_IRQn: 00288 case EXTI2_IRQn: 00289 case EXTI3_IRQn: 00290 ITC->ISPR3 &= Mask; 00291 ITC->ISPR3 |= NewPriority; 00292 break; 00293 00294 case EXTI4_IRQn: 00295 case EXTI5_IRQn: 00296 case EXTI6_IRQn: 00297 case EXTI7_IRQn: 00298 ITC->ISPR4 &= Mask; 00299 ITC->ISPR4 |= NewPriority; 00300 break; 00301 #ifndef STM8L15X_LD 00302 case SWITCH_CSS_BREAK_DAC_IRQn: 00303 #else 00304 case SWITCH_CSS_IRQn: 00305 #endif /* STM8L15X_LD */ 00306 case ADC1_COMP_IRQn: 00307 #ifdef STM8L15X_MD 00308 case LCD_IRQn: 00309 case TIM2_UPD_OVF_TRG_BRK_IRQn: 00310 #elif defined (STM8L15X_LD) 00311 case TIM2_UPD_OVF_TRG_BRK_IRQn: 00312 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00313 case LCD_AES_IRQn: 00314 case TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn: 00315 #endif /* STM8L15X_MD */ 00316 ITC->ISPR5 &= Mask; 00317 ITC->ISPR5 |= NewPriority; 00318 break; 00319 #ifndef STM8L15X_LD 00320 case TIM1_UPD_OVF_TRG_IRQn: 00321 #endif /* STM8L15X_LD */ 00322 #if defined (STM8L15X_MD) || defined (STM8L15X_LD) 00323 case TIM2_CC_IRQn: 00324 case TIM3_UPD_OVF_TRG_BRK_IRQn : 00325 case TIM3_CC_IRQn: 00326 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00327 case TIM2_CC_USART2_RX_IRQn: 00328 case TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn : 00329 case TIM3_CC_USART3_RX_IRQn: 00330 #endif /* STM8L15X_MD */ 00331 ITC->ISPR6 &= Mask; 00332 ITC->ISPR6 |= NewPriority; 00333 break; 00334 00335 #ifndef STM8L15X_LD 00336 case TIM1_CC_IRQn: 00337 #endif /* STM8L15X_LD */ 00338 case TIM4_UPD_OVF_TRG_IRQn: 00339 case SPI1_IRQn: 00340 #if defined (STM8L15X_MD) || defined (STM8L15X_LD) 00341 case USART1_TX_IRQn: 00342 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00343 case USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn: 00344 #endif /* STM8L15X_MD */ 00345 ITC->ISPR7 &= Mask; 00346 ITC->ISPR7 |= NewPriority; 00347 break; 00348 00349 #if defined (STM8L15X_MD) || defined (STM8L15X_LD) 00350 case USART1_RX_IRQn: 00351 case I2C1_IRQn: 00352 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00353 case USART1_RX_TIM5_CC_IRQn: 00354 case I2C1_SPI2_IRQn: 00355 #endif /* STM8L15X_MD */ 00356 ITC->ISPR8 &= Mask; 00357 ITC->ISPR8 |= NewPriority; 00358 break; 00359 00360 default: 00361 break; 00362 } 00363 } 00364 00365 /** 00366 * @} 00367 */ 00368 00369 /** 00370 * @} 00371 */ 00372 00373 /** 00374 * @} 00375 */ 00376 00377 /** 00378 * @} 00379 */ 00380 00381 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/