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STM8L15x Standard Peripherals Drivers
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stm8l15x_dac.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_dac.c 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file provides firmware functions to manage the following 00008 * functionalities of the Digital-to-Analog Converter (DAC) peripheral: 00009 * - DAC channels configuration: trigger, output buffer, data format 00010 * - DMA management 00011 * - Interrupts and flags management 00012 * 00013 * @verbatim 00014 * 00015 * =================================================================== 00016 * DAC Peripheral features 00017 * =================================================================== 00018 * The device integrates two 12-bit Digital Analog Converters that can 00019 * be used independently or simultaneously (dual mode): 00020 * 1- DAC channel1 with DAC_OUT1 (PF0) as output 00021 * 1- DAC channel2 with DAC_OUT2 (PF1) as output 00022 * 00023 * Digital to Analog conversion can be non-triggered using DAC_Trigger_None 00024 * and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using 00025 * DAC_SetChannel1Data()/DAC_SetChannel2Data. 00026 * 00027 * Digital to Analog conversion can be triggered by: 00028 * 1- External event: PE4 using DAC_Trigger_Ext. 00029 * This pin (PE4) must be configured in input mode. 00030 * 00031 * 2- Timers TRGO: TIM4, TIM5 00032 * (DAC_Trigger_T4_TRGO, DAC_Trigger_T5_TRGO) 00033 * The timer TRGO event should be selected using TIMx_SelectOutputTrigger() 00034 * 00035 * 3- Software using DAC_Trigger_Software 00036 * 00037 * Each DAC channel integrates an output buffer that can be used to 00038 * reduce the output impedance, and to drive external loads directly 00039 * without having to add an external operational amplifier. 00040 * 00041 * Refer to the device datasheet for more details about output impedance 00042 * value with and without output buffer. 00043 * 00044 * Both DAC channels can be used to generate 00045 * 1- Noise wave using DAC_Wave_Noise 00046 * 2- Triangle wave using DAC_Wave_Triangle 00047 * 00048 * 00049 * The DAC data format can be: 00050 * 1- 8-bit right alignment using DAC_Align_8b_R 00051 * 2- 12-bit left alignment using DAC_Align_12b_L 00052 * 3- 12-bit right alignment using DAC_Align_12b_R 00053 * 00054 * The analog output voltage on each DAC channel pin is determined 00055 * by the following equation: DAC_OUTx = VREF+ * DOR / 4095 00056 * with DOR is the Data Output Register 00057 * VEF+ is the input voltage reference (refer to the device datasheet) 00058 * e.g. To set DAC_OUT1 to 0.7V, use 00059 * DAC_SetChannel1Data(DAC_Align_12b_R, 868); 00060 * Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V 00061 * 00062 * A DMA1 request can be generated when an external trigger (but not 00063 * a software trigger) occurs if DMA1 requests are enabled using 00064 * DAC_DMACmd() 00065 * DMA1 requests are mapped as following: 00066 * 1- DAC channel1 is mapped on DMA1 channel3 which must be already 00067 * configured 00068 * 2- DAC channel2 is mapped on DMA1 channel1 which must be already 00069 * configured 00070 * 00071 * =================================================================== 00072 * How to use this driver 00073 * =================================================================== 00074 * - DAC clock must be enabled to get write access to DAC registers using 00075 * CLK_PeripheralClockConfig(CLK_Peripheral_DAC, ENABLE) 00076 * - Configure DAC_OUTx (DAC_OUT1: PF0, DAC_OUT2: PF1) in analog mode. 00077 * - Configure the DAC channel using DAC_Init() 00078 * - Enable the DAC channel using DAC_Cmd() 00079 * 00080 * @endverbatim 00081 * 00082 ****************************************************************************** 00083 * @attention 00084 * 00085 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00086 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00087 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00088 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00089 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00090 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00091 * 00092 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00093 ****************************************************************************** 00094 */ 00095 00096 /* Includes ------------------------------------------------------------------*/ 00097 #include "stm8l15x_dac.h" 00098 00099 /** @addtogroup STM8L15x_StdPeriph_Driver 00100 * @{ 00101 */ 00102 00103 /** @defgroup DAC 00104 * @brief DAC driver modules 00105 * @{ 00106 */ 00107 00108 /* Private typedef -----------------------------------------------------------*/ 00109 /* Private define ------------------------------------------------------------*/ 00110 /* Private macro -------------------------------------------------------------*/ 00111 /* Private variables ---------------------------------------------------------*/ 00112 /* Private function prototypes -----------------------------------------------*/ 00113 /* Private functions ---------------------------------------------------------*/ 00114 00115 /** @defgroup DAC_Private_Functions 00116 * @{ 00117 */ 00118 00119 /** @defgroup DAC_Group1 DAC channels configuration 00120 * @brief DAC channels configuration: trigger, output buffer, data format 00121 * 00122 @verbatim 00123 =============================================================================== 00124 DAC channels configuration: trigger, output buffer, data format 00125 =============================================================================== 00126 00127 @endverbatim 00128 * @{ 00129 */ 00130 00131 /** 00132 * @brief Deinitializes the DAC peripheral registers to their default reset values. 00133 * @param None 00134 * @retval None 00135 */ 00136 void DAC_DeInit(void) 00137 { 00138 /* Set Channel1 the Configuration registers to their reset values */ 00139 DAC->CH1CR1 = DAC_CR1_RESET_VALUE; 00140 DAC->CH1CR2 = DAC_CR2_RESET_VALUE; 00141 00142 /* Set Channel2 the Configuration registers to their reset values */ 00143 DAC->CH2CR1 = DAC_CR1_RESET_VALUE; 00144 DAC->CH2CR2 = DAC_CR2_RESET_VALUE; 00145 00146 /* Set the Software Trigger configuration registers to their reset values */ 00147 DAC->SWTRIGR = DAC_SWTRIGR_RESET_VALUE; 00148 00149 /* Set the Status registers to their reset values */ 00150 DAC->SR = (uint8_t)~DAC_SR_RESET_VALUE; 00151 00152 /* Set the Channel1 Data holding registers to their reset values */ 00153 DAC->CH1RDHRH = DAC_RDHRH_RESET_VALUE; 00154 DAC->CH1RDHRL = DAC_RDHRL_RESET_VALUE; 00155 DAC->CH1LDHRH = DAC_LDHRH_RESET_VALUE; 00156 DAC->CH1LDHRL = DAC_LDHRL_RESET_VALUE; 00157 DAC->CH1DHR8 = DAC_DHR8_RESET_VALUE; 00158 00159 /* Set the Channel2 Data holding registers to their reset values */ 00160 DAC->CH2RDHRH = DAC_RDHRH_RESET_VALUE; 00161 DAC->CH2RDHRL = DAC_RDHRL_RESET_VALUE; 00162 DAC->CH2LDHRH = DAC_LDHRH_RESET_VALUE; 00163 DAC->CH2LDHRL = DAC_LDHRL_RESET_VALUE; 00164 DAC->CH2DHR8 = DAC_DHR8_RESET_VALUE; 00165 00166 /* Set the Dual mode 12bit Right Data holding registers to their reset values */ 00167 DAC->DCH1RDHRH = DAC_RDHRH_RESET_VALUE; 00168 DAC->DCH1RDHRL = DAC_RDHRL_RESET_VALUE; 00169 DAC->DCH2RDHRH = DAC_RDHRH_RESET_VALUE; 00170 DAC->DCH2RDHRL = DAC_RDHRL_RESET_VALUE; 00171 00172 /* Set the Dual mode 12bit Left Data holding registers to their reset values */ 00173 DAC->DCH1LDHRH = DAC_LDHRH_RESET_VALUE; 00174 DAC->DCH1LDHRL = DAC_LDHRL_RESET_VALUE; 00175 DAC->DCH2LDHRH = DAC_LDHRH_RESET_VALUE; 00176 DAC->DCH2LDHRL = DAC_LDHRL_RESET_VALUE; 00177 00178 /* Set the Dual mode 8bit Data holding registers to their reset values */ 00179 DAC->DCH1DHR8 = DAC_DHR8_RESET_VALUE; 00180 DAC->DCH2DHR8 = DAC_DHR8_RESET_VALUE; 00181 } 00182 00183 /** 00184 * @brief Initializes the DAC according to the specified parameters. 00185 * @param DAC_Channel: the selected DAC channel. 00186 * This parameter can be one of the following values: 00187 * @arg DAC_Channel_1: DAC Channel1 selected 00188 * @arg DAC_Channel_2: DAC Channel2 selected 00189 * @param DAC_Trigger : the selected DAC trigger. 00190 * This parameter can be one of the following values: 00191 * @arg DAC_Trigger_None: DAC trigger None 00192 * @arg DAC_Trigger_T4_TRGO: DAC trigger TIM4 TRGO 00193 * @arg DAC_Trigger_T5_TRGO: DAC trigger TIM5 TRGO 00194 * @arg DAC_Trigger_Ext: DAC trigger External Trigger (PE4) 00195 * @arg DAC_Trigger_Software: DAC trigger software 00196 * @param DAC_OutputBuffer : the status of DAC load Buffer 00197 * This parameter can be one of the following values: 00198 * @arg DAC_OutputBuffer_Enable: DAC output buffer Enabled 00199 * @arg DAC_OutputBuffer_Disable: DAC output buffer Disabled 00200 * @retval None 00201 */ 00202 void DAC_Init(DAC_Channel_TypeDef DAC_Channel, 00203 DAC_Trigger_TypeDef DAC_Trigger, 00204 DAC_OutputBuffer_TypeDef DAC_OutputBuffer) 00205 { 00206 uint8_t tmpreg = 0; 00207 uint16_t tmpreg2 = 0; 00208 00209 /* Check the DAC parameters */ 00210 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00211 assert_param(IS_DAC_TRIGGER(DAC_Trigger)); 00212 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_OutputBuffer)); 00213 00214 /* Get the DAC CHxCR1 value */ 00215 tmpreg2 = (uint16_t)((uint8_t)((uint8_t)DAC_Channel << 1)); 00216 tmpreg = *(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2)); 00217 00218 /* Clear BOFFx, TENx, TSELx bits */ 00219 tmpreg &= (uint8_t)~(DAC_CR1_BOFF | DAC_CR1_TEN | DAC_CR1_TSEL ); 00220 00221 /* Set BOFFx bit according to DAC_OutputBuffer value */ 00222 tmpreg |= (uint8_t)(DAC_OutputBuffer); 00223 00224 00225 /* Configure for the selected DAC channel trigger*/ 00226 if (DAC_Trigger != DAC_Trigger_None) 00227 { 00228 /* Set TSELx and TEN bits according to DAC_Trigger value */ 00229 tmpreg |= (uint8_t)(DAC_CR1_TEN | DAC_Trigger) ; 00230 } 00231 00232 /* Write to DAC CHxCR1 */ 00233 *(uint8_t*)((uint16_t)(DAC_BASE + CR1_Offset + tmpreg2)) = (uint8_t)tmpreg; 00234 } 00235 00236 /** 00237 * @brief Enables or disables the specified DAC channel. 00238 * @param DAC_Channel: the selected DAC channel. 00239 * This parameter can be one of the following values: 00240 * @arg DAC_Channel_1: DAC Channel1 selected 00241 * @arg DAC_Channel_2: DAC Channel2 selected 00242 * @param NewState: new state of the DAC channel. 00243 * This parameter can be: ENABLE or DISABLE. 00244 * @note When the DAC channel is enabled the trigger source can no more 00245 * be modified. 00246 * @retval None 00247 */ 00248 void DAC_Cmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState) 00249 { 00250 uint16_t cr1addr = 0; 00251 /* Check the parameters */ 00252 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00253 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00254 00255 /* Find CHxCR1 register Address */ 00256 cr1addr = DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1); 00257 00258 if (NewState != DISABLE) 00259 { 00260 /* Enable the selected DAC channel */ 00261 (*(uint8_t*)(cr1addr)) |= DAC_CR1_EN; 00262 } 00263 else 00264 { 00265 /* Disable the selected DAC channel */ 00266 (*(uint8_t*)(cr1addr)) &= (uint8_t) ~(DAC_CR1_EN); 00267 } 00268 } 00269 00270 /** 00271 * @brief Enables or disables the selected DAC channel software trigger. 00272 * @param DAC_Channel: the selected DAC channel. 00273 * This parameter can be one of the following values: 00274 * @arg DAC_Channel_1: DAC Channel1 selected 00275 * @arg DAC_Channel_2: DAC Channel2 selected 00276 * @param NewState: new state of the selected DAC channel software trigger. 00277 * This parameter can be: ENABLE or DISABLE. 00278 * @retval None. 00279 */ 00280 void DAC_SoftwareTriggerCmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState) 00281 { 00282 /* Check the parameters */ 00283 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00284 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00285 00286 if (NewState != DISABLE) 00287 { 00288 /* Enable software trigger for the selected DAC channel */ 00289 DAC->SWTRIGR |= (uint8_t)(DAC_SWTRIGR_SWTRIG1 << DAC_Channel); 00290 } 00291 else 00292 { 00293 /* Disable software trigger for the selected DAC channel */ 00294 DAC->SWTRIGR &= (uint8_t)~((uint8_t)(DAC_SWTRIGR_SWTRIG1 << DAC_Channel)); 00295 } 00296 } 00297 00298 /** 00299 * @brief Enables or disables simultaneously the two DAC channels software 00300 * triggers. 00301 * @param NewState: new state of the DAC channels software triggers. 00302 * This parameter can be: ENABLE or DISABLE. 00303 * @retval None. 00304 */ 00305 void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) 00306 { 00307 /* Check the parameters */ 00308 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00309 00310 if (NewState != DISABLE) 00311 { 00312 /* Enable software trigger for both DAC channels */ 00313 DAC->SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2) ; 00314 } 00315 else 00316 { 00317 /* Disable software trigger for both DAC channels */ 00318 DAC->SWTRIGR &= (uint8_t)~(DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2); 00319 } 00320 } 00321 00322 /** 00323 * @brief Enables or disables the selected DAC channel wave generation. 00324 * @param DAC_Channel: the selected DAC channel. 00325 * This parameter can be one of the following values: 00326 * @arg DAC_Channel_1: DAC Channel1 selected 00327 * @arg DAC_Channel_2: DAC Channel2 selected 00328 * @param DAC_Wave: Specifies the wave type to enable or disable. 00329 * This parameter can be one of the following values: 00330 * @arg DAC_Wave_Noise: noise wave generation 00331 * @arg DAC_Wave_Triangle: triangle wave generation 00332 * @param NewState: new state of the selected DAC channel wave generation. 00333 * This parameter can be: ENABLE or DISABLE. 00334 * @retval None 00335 */ 00336 void DAC_WaveGenerationCmd(DAC_Channel_TypeDef DAC_Channel, 00337 DAC_Wave_TypeDef DAC_Wave, 00338 FunctionalState NewState) 00339 { 00340 uint8_t tmpreg = 0; 00341 00342 /* Check the DAC parameters */ 00343 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00344 assert_param(IS_DAC_WAVE(DAC_Wave)); 00345 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00346 00347 /* Get the DAC CHxCR1 value & Clear WAVEN bits */ 00348 tmpreg = (uint8_t)((*(uint8_t*)(uint16_t)(DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1))) & (uint8_t)~(DAC_CR1_WAVEN)); 00349 00350 if (NewState != DISABLE) 00351 { 00352 tmpreg |= (uint8_t)(DAC_Wave); 00353 } 00354 00355 /* Write to DAC CHxCR1 */ 00356 (*(uint8_t*) (uint16_t)(DAC_BASE + CR1_Offset + (uint8_t)((uint8_t)DAC_Channel << 1))) = tmpreg; 00357 00358 } 00359 00360 /** 00361 * @brief Select DAC Noise Wave Generation LFSR according to the specified parameters. 00362 * @param DAC_Channel: the selected DAC channel. 00363 * This parameter can be one of the following values: 00364 * @arg DAC_Channel_1: DAC Channel1 selected 00365 * @arg DAC_Channel_2: DAC Channel2 selected 00366 * @param DAC_LFSRUnmask : the selected unmasked bit. 00367 * This parameter can be one of the following values: 00368 * @arg DAC_LFSRUnmask_Bit0: Noise LFSR Unmask 1 LSB 00369 * @arg DAC_LFSRUnmask_Bits1_0: Noise LFSR Unmask 2 LSB 00370 * @arg DAC_LFSRUnmask_Bit2_0: Noise LFSR Unmask 3 LSB 00371 * @arg DAC_LFSRUnmask_Bit3_0: Noise LFSR Unmask 4 LSB 00372 * @arg DAC_LFSRUnmask_Bit4_0: Noise LFSR Unmask 5 LSB 00373 * @arg DAC_LFSRUnmask_Bit5_0: Noise LFSR Unmask 6 LSB 00374 * @arg DAC_LFSRUnmask_Bit6_0: Noise LFSR Unmask 7 LSB 00375 * @arg DAC_LFSRUnmask_Bit7_0: Noise LFSR Unmask 8 LSB 00376 * @arg DAC_LFSRUnmask_Bit8_0: Noise LFSR Unmask 9 LSB 00377 * @arg DAC_LFSRUnmask_Bit9_0: Noise LFSR Unmask 10 LSB 00378 * @arg DAC_LFSRUnmask_Bit10_0: Noise LFSR Unmask 11 LSB 00379 * @arg DAC_LFSRUnmask_Bit11_0: Noise LFSR Unmask 12 LSB 00380 * @retval None 00381 */ 00382 void DAC_SetNoiseWaveLFSR(DAC_Channel_TypeDef DAC_Channel, DAC_LFSRUnmask_TypeDef DAC_LFSRUnmask) 00383 { 00384 uint8_t tmpreg = 0; 00385 uint16_t cr2addr = 0; 00386 00387 /* Check the DAC parameters */ 00388 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00389 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_LFSRUnmask)); 00390 00391 /* Get the DAC CHxCR2 value & Clear MAMPx bits */ 00392 cr2addr = (uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1)); 00393 tmpreg = (uint8_t)((*(uint8_t*)(cr2addr)) & (uint8_t)~(DAC_CR2_MAMPx)); 00394 00395 /* Write to DAC CHxCR2 */ 00396 (*(uint8_t*)(cr2addr)) = (uint8_t)( tmpreg | DAC_LFSRUnmask); 00397 } 00398 00399 /** 00400 * @brief Select DAC Triangle Wave Generation Amplitude according to the specified parameters. 00401 * @param DAC_Channel: the selected DAC channel. 00402 * This parameter can be one of the following values: 00403 * @arg DAC_Channel_1: DAC Channel1 selected 00404 * @arg DAC_Channel_2: DAC Channel2 selected 00405 * @param DAC_TriangleAmplitude : the selected Amplitude 00406 * This parameter can be one of the following values: 00407 * @arg DAC_TriangleAmplitude_1: Triangle Amplitude = Vref.(1/4096) 00408 * @arg DAC_TriangleAmplitude_3: Triangle Amplitude = Vref.(3/4096) 00409 * @arg DAC_TriangleAmplitude_7: Triangle Amplitude = Vref.(7/4096) 00410 * @arg DAC_TriangleAmplitude_15: Triangle Amplitude = Vref.(15/4096) 00411 * @arg DAC_TriangleAmplitude_31: Triangle Amplitude = Vref.(31/4096) 00412 * @arg DAC_TriangleAmplitude_63: Triangle Amplitude = Vref.(63/4096) 00413 * @arg DAC_TriangleAmplitude_127: Triangle Amplitude = Vref.(127/4096) 00414 * @arg DAC_TriangleAmplitude_255: Triangle Amplitude = Vref.(255/4096) 00415 * @arg DAC_TriangleAmplitude_511: Triangle Amplitude = Vref.(511/4096) 00416 * @arg DAC_TriangleAmplitude_1023: Triangle Amplitude = Vref.(1023/4096) 00417 * @arg DAC_TriangleAmplitude_2047: Triangle Amplitude = Vref.(2047/4096) 00418 * @arg DAC_TriangleAmplitude_4095: Triangle Amplitude = Vref.(4095/4096) 00419 * @retval None 00420 */ 00421 void DAC_SetTriangleWaveAmplitude(DAC_Channel_TypeDef DAC_Channel, DAC_TriangleAmplitude_TypeDef DAC_TriangleAmplitude) 00422 { 00423 uint8_t tmpreg = 0; 00424 uint16_t cr2addr = 0; 00425 00426 /* Check the DAC parameters */ 00427 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00428 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_TriangleAmplitude)); 00429 00430 00431 /* Get the DAC CHxCR2 value & Clear MAMPx bits */ 00432 cr2addr = (uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1)); 00433 tmpreg = (uint8_t)((*(uint8_t*)(cr2addr)) & (uint8_t)~(DAC_CR2_MAMPx)); 00434 00435 /* Write to DAC CHxCR2 */ 00436 (*(uint8_t*)(cr2addr)) = (uint8_t)( tmpreg | DAC_TriangleAmplitude); 00437 } 00438 00439 /** 00440 * @brief Set the specified data holding register value for DAC channel1. 00441 * @param DAC_Align: Specifies the data alignment for DAC channel1. 00442 * This parameter can be one of the following values: 00443 * @arg DAC_Align_8b_R: 8bit right data alignment selected 00444 * @arg DAC_Align_12b_L: 12bit left data alignment selected 00445 * @arg DAC_Align_12b_R: 12bit right data alignment selected 00446 * @param Data : Data to be loaded in the selected data holding register. 00447 * @retval None. 00448 */ 00449 void DAC_SetChannel1Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data) 00450 { 00451 /* Check the parameters */ 00452 assert_param(IS_DAC_ALIGN(DAC_Align)); 00453 00454 if (DAC_Align != DAC_Align_8b_R) 00455 { 00456 /* Set the DAC channel1 selected data holding register */ 00457 *(uint8_t*)((uint16_t)(DAC_BASE + CH1RDHRH_Offset + DAC_Align )) = (uint8_t)(((uint16_t)DAC_Data) >> 8); 00458 *(uint8_t*)((uint16_t)(DAC_BASE + CH1RDHRH_Offset + 1 + DAC_Align )) = (uint8_t)DAC_Data; 00459 } 00460 else 00461 { 00462 /* Check the parameter */ 00463 assert_param(IS_DAC_DATA_08R(DAC_Data)); 00464 00465 /* Set the DAC channel1 selected data holding register */ 00466 DAC->CH1DHR8 = (uint8_t)(DAC_Data); 00467 } 00468 } 00469 00470 /** 00471 * @brief Set the specified data holding register value for DAC channel2. 00472 * @param DAC_Align: Specifies the data alignment for DAC channel2. 00473 * This parameter can be one of the following values: 00474 * @arg DAC_Align_8b_R: 8bit right data alignment selected 00475 * @arg DAC_Align_12b_L: 12bit left data alignment selected 00476 * @arg DAC_Align_12b_R: 12bit right data alignment selected 00477 * @param Data : Data to be loaded in the selected data holding register. 00478 * @retval None. 00479 */ 00480 void DAC_SetChannel2Data(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data) 00481 { 00482 /* Check the parameters */ 00483 assert_param(IS_DAC_ALIGN(DAC_Align)); 00484 00485 if (DAC_Align != DAC_Align_8b_R) 00486 { 00487 /* Set the DAC channel2 selected data holding register */ 00488 *(uint8_t*)((uint16_t)(DAC_BASE + CH2RDHRH_Offset + DAC_Align )) = (uint8_t)(((uint16_t)DAC_Data) >> 8); 00489 *(uint8_t*)((uint16_t)(DAC_BASE + CH2RDHRH_Offset + 1 + DAC_Align )) = (uint8_t)DAC_Data; 00490 } 00491 else 00492 { 00493 /* Check the parameter */ 00494 assert_param(IS_DAC_DATA_08R(DAC_Data)); 00495 00496 /* Set the DAC channel2 selected data holding register */ 00497 DAC->CH2DHR8 = (uint8_t)(DAC_Data); 00498 } 00499 } 00500 00501 /** 00502 * @brief Set the specified data holding register value for dual channel DAC. 00503 * @param DAC_Align: Specifies the data alignment for dual channel DAC. 00504 * This parameter can be one of the following values: 00505 * @arg DAC_Align_8b_R: 8bit right data alignment selected 00506 * @arg DAC_Align_12b_L: 12bit left data alignment selected 00507 * @arg DAC_Align_12b_R: 12bit right data alignment selected 00508 * @param Data2: Data for DAC Channel2 to be loaded in the selected data 00509 * holding register. 00510 * @param Data1: Data for DAC Channel1 to be loaded in the selected data 00511 * holding register. 00512 * @note In dual mode, a unique register access is required to write in both 00513 * DAC channels at the same time. 00514 * @retval None. 00515 */ 00516 void DAC_SetDualChannelData(DAC_Align_TypeDef DAC_Align, uint16_t DAC_Data2, uint16_t DAC_Data1) 00517 { 00518 uint16_t dchxrdhrhaddr = 0; 00519 00520 /* Check the parameters */ 00521 assert_param(IS_DAC_ALIGN(DAC_Align)); 00522 00523 if (DAC_Align != DAC_Align_8b_R) 00524 { 00525 /* Identify the DCHxRDHRH address*/ 00526 dchxrdhrhaddr = (uint16_t)(DAC_BASE + DCH1RDHRH_Offset + DAC_Align); 00527 00528 /* Set the DAC channels Dual data holding registers */ 00529 *(uint8_t*)(uint16_t)dchxrdhrhaddr = (uint8_t)(((uint16_t)DAC_Data1) >> 8); 00530 *(uint8_t*)(uint16_t)(dchxrdhrhaddr + 1) = (uint8_t)DAC_Data1; 00531 *(uint8_t*)(uint16_t)(dchxrdhrhaddr + 2) = (uint8_t)(((uint16_t)DAC_Data2) >> 8); 00532 *(uint8_t*)(uint16_t)(dchxrdhrhaddr + 3) = (uint8_t)DAC_Data2; 00533 } 00534 else 00535 { 00536 /* Check the parameter */ 00537 assert_param(IS_DAC_DATA_08R(DAC_Data1 | DAC_Data2)); 00538 00539 /* Set the DAC channels Dual data holding registers */ 00540 DAC->DCH1DHR8 = (uint8_t)(DAC_Data1); 00541 DAC->DCH2DHR8 = (uint8_t)(DAC_Data2); 00542 } 00543 } 00544 00545 /** 00546 * @brief Returns the last data output value of the selected DAC channel. 00547 * @param DAC_Channel: the selected DAC channel. 00548 * This parameter can be one of the following values: 00549 * @arg DAC_Channel_1: DAC Channel1 selected 00550 * @arg DAC_Channel_2: DAC Channel2 selected 00551 * @retval The selected DAC channel data output value. 00552 */ 00553 uint16_t DAC_GetDataOutputValue(DAC_Channel_TypeDef DAC_Channel) 00554 { 00555 uint16_t outputdata = 0; 00556 uint16_t tmp = 0; 00557 00558 /* Check the parameters */ 00559 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00560 00561 if ( DAC_Channel == DAC_Channel_1) 00562 { 00563 /* Returns the DAC channel data output register value */ 00564 tmp = (uint16_t)((uint16_t)DAC->CH1DORH << 8); 00565 outputdata = (uint16_t)(tmp | (DAC->CH1DORL)); 00566 } 00567 else 00568 { 00569 /* Returns the DAC channel data output register value */ 00570 tmp = (uint16_t)((uint16_t)DAC->CH2DORH << 8); 00571 outputdata = (uint16_t)(tmp | (DAC->CH2DORL)); 00572 } 00573 00574 /* return the selected DAC channel data output value.*/ 00575 return (uint16_t)outputdata; 00576 } 00577 00578 /** 00579 * @} 00580 */ 00581 00582 /** @defgroup DAC_Group2 DMA management functions 00583 * @brief DMA management functions 00584 * 00585 @verbatim 00586 =============================================================================== 00587 DMA management function 00588 =============================================================================== 00589 00590 @endverbatim 00591 * @{ 00592 */ 00593 00594 /** 00595 * @brief Enables or disables the specified DAC channel DMA request. 00596 * When enabled DMA1 is generated when an external trigger occurs 00597 * @param DAC_Channel: the selected DAC channel. 00598 * This parameter can be one of the following values: 00599 * @arg DAC_Channel_1: DAC Channel1 selected 00600 * @arg DAC_Channel_2: DAC Channel2 selected 00601 * @param NewState: new state of the selected DAC channel DMA request. 00602 * This parameter can be: ENABLE or DISABLE. 00603 * The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel1) which 00604 * must be already configured. 00605 * @retval None 00606 */ 00607 void DAC_DMACmd(DAC_Channel_TypeDef DAC_Channel, FunctionalState NewState) 00608 { 00609 uint16_t cr2addr = 0; 00610 00611 /* Check the parameters */ 00612 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00613 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00614 00615 /* Find CHxCR2 register Address */ 00616 cr2addr = DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1); 00617 00618 if (NewState != DISABLE) 00619 { 00620 /* Enable the selected DAC channel DMA request */ 00621 (*(uint8_t*)(cr2addr)) |= DAC_CR2_DMAEN; 00622 } 00623 else 00624 { 00625 /* Disable the selected DAC channel DMA request */ 00626 (*(uint8_t*)(cr2addr)) &= (uint8_t)~(DAC_CR2_DMAEN); 00627 } 00628 } 00629 00630 /** 00631 * @} 00632 */ 00633 00634 /** @defgroup DAC_Group3 Interrupts and flags management functions 00635 * @brief Interrupts and flags management functions 00636 * 00637 @verbatim 00638 =============================================================================== 00639 Interrupts and flags management functions 00640 =============================================================================== 00641 00642 @endverbatim 00643 * @{ 00644 */ 00645 00646 /** 00647 * @brief Enables or disables the specified DAC interrupts. 00648 * @param DAC_Channel: the selected DAC channel. 00649 * This parameter can be one of the following values: 00650 * @arg DAC_Channel_1: DAC Channel1 selected 00651 * @arg DAC_Channel_2: DAC Channel2 selected 00652 * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 00653 * This parameter can be the following values: 00654 * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask 00655 * @note The DMA underrun occurs when a second external trigger arrives before 00656 * the acknowledgement for the first external trigger is received (first request). 00657 * @param NewState: new state of the specified DAC interrupts. 00658 * This parameter can be: ENABLE or DISABLE. 00659 * @retval None 00660 */ 00661 void DAC_ITConfig(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT, FunctionalState NewState) 00662 { 00663 uint16_t cr2addr = 0; 00664 00665 /* Check the parameters */ 00666 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00667 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00668 assert_param(IS_DAC_IT(DAC_IT)); 00669 00670 /* Find CHxCR2 register Address */ 00671 cr2addr = DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 1); 00672 00673 if (NewState != DISABLE) 00674 { 00675 /* Enable the selected DAC interrupts */ 00676 (*(uint8_t*)(cr2addr)) |= (uint8_t)(DAC_IT); 00677 } 00678 else 00679 { 00680 /* Disable the selected DAC interrupts */ 00681 (*(uint8_t*)(cr2addr)) &= (uint8_t)(~(DAC_IT)); 00682 } 00683 } 00684 00685 /** 00686 * @brief Checks whether the specified DAC flag is set or not. 00687 * @param DAC_Channel: thee selected DAC channel. 00688 * This parameter can be one of the following values: 00689 * @arg DAC_Channel_1: DAC Channel1 selected 00690 * @arg DAC_Channel_2: DAC Channel2 selected 00691 * @param DAC_FLAG: specifies the flag to check. 00692 * This parameter can be only of the following value: 00693 * @arg DAC_FLAG_DMAUDR: DMA underrun flag 00694 * @note The DMA underrun occurs when a second external trigger arrives before 00695 * the acknowledgement for the first external trigger is received (first request). 00696 * @retval The new state of DAC_FLAG (SET or RESET). 00697 */ 00698 FlagStatus DAC_GetFlagStatus(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG) 00699 { 00700 FlagStatus flagstatus = RESET; 00701 uint8_t flag = 0; 00702 00703 /* Check the parameters */ 00704 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00705 assert_param(IS_DAC_FLAG(DAC_FLAG)); 00706 00707 flag = (uint8_t)(DAC_FLAG << DAC_Channel); 00708 00709 /* Check the status of the specified DAC flag */ 00710 if ((DAC->SR & flag ) != (uint8_t)RESET) 00711 { 00712 /* DAC FLAG is set */ 00713 flagstatus = SET; 00714 } 00715 else 00716 { 00717 /* DAC FLAG is reset */ 00718 flagstatus = RESET; 00719 } 00720 00721 /* Return the DAC FLAG status */ 00722 return flagstatus; 00723 } 00724 00725 /** 00726 * @brief Clears the DAC channel's pending flags. 00727 * @param DAC_Channel: the selected DAC channel. 00728 * This parameter can be one of the following values: 00729 * @arg DAC_Channel_1: DAC Channel1 selected 00730 * @arg DAC_Channel_2: DAC Channel2 selected 00731 * @param DAC_FLAG: specifies the flag to clear. 00732 * This parameter can be of the following value: 00733 * @arg DAC_FLAG_DMAUDR: DMA underrun flag 00734 * @retval None 00735 */ 00736 void DAC_ClearFlag(DAC_Channel_TypeDef DAC_Channel, DAC_FLAG_TypeDef DAC_FLAG) 00737 { 00738 uint8_t flag = 0; 00739 00740 /* Check the parameters */ 00741 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00742 assert_param(IS_DAC_FLAG(DAC_FLAG)); 00743 00744 /* identify the selected flag*/ 00745 flag = (uint8_t)(DAC_FLAG << DAC_Channel); 00746 00747 /* Clear the selected DAC flag */ 00748 DAC->SR = (uint8_t)(~flag); 00749 } 00750 00751 /** 00752 * @brief Checks whether the specified DAC interrupt has occurred or not. 00753 * @param DAC_Channel: the selected DAC channel. 00754 * This parameter can be one of the following values: 00755 * @arg DAC_Channel_1: DAC Channel1 selected 00756 * @arg DAC_Channel_2: DAC Channel2 selected 00757 * @param DAC_IT: specifies the DAC interrupt source to check. 00758 * This parameter can be the following values: 00759 * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask 00760 * @note The DMA underrun occurs when a second external trigger arrives before 00761 * the acknowledgement for the first external trigger is received (first request). 00762 * @retval The new state of DAC_IT (SET or RESET). 00763 */ 00764 ITStatus DAC_GetITStatus(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT) 00765 { 00766 ITStatus itstatus = RESET; 00767 uint8_t enablestatus = 0; 00768 uint8_t flagstatus = 0; 00769 uint8_t tempreg = 0; 00770 00771 /* Check the parameters */ 00772 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00773 assert_param(IS_DAC_IT(DAC_IT)); 00774 00775 /* identify the status of the IT and its correspondent flag*/ 00776 tempreg = *(uint8_t*)(uint16_t)(DAC_BASE + CR2_Offset + (uint8_t)((uint8_t)DAC_Channel << 2)); 00777 enablestatus = (uint8_t)( tempreg & (uint8_t)((uint8_t)DAC_IT << DAC_Channel)); 00778 flagstatus = (uint8_t)(DAC->SR & (uint8_t)(DAC_IT >> ((uint8_t)0x05 - DAC_Channel))); 00779 00780 /* Check the status of the specified DAC interrupt */ 00781 if (((flagstatus) != (uint8_t)RESET) && enablestatus) 00782 { 00783 /* DAC IT is set */ 00784 itstatus = SET; 00785 } 00786 else 00787 { 00788 /* DAC IT is reset */ 00789 itstatus = RESET; 00790 } 00791 00792 /* Return the DAC IT status */ 00793 return itstatus; 00794 } 00795 00796 /** 00797 * @brief Clears the DAC channel's interrupt pending bits. 00798 * @param DAC_Channel: the selected DAC channel. 00799 * This parameter can be one of the following values: 00800 * @arg DAC_Channel_1: DAC Channel1 selected 00801 * @arg DAC_Channel_2: DAC Channel2 selected 00802 * @param DAC_IT: specifies the DAC interrupt pending bit to clear. 00803 * This parameter can be the following values: 00804 * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask 00805 * @retval None 00806 */ 00807 void DAC_ClearITPendingBit(DAC_Channel_TypeDef DAC_Channel, DAC_IT_TypeDef DAC_IT) 00808 { 00809 /* Check the parameters */ 00810 assert_param(IS_DAC_CHANNEL(DAC_Channel)); 00811 assert_param(IS_DAC_IT(DAC_IT)); 00812 00813 /* Clear the selected DAC interrupt pending bits */ 00814 DAC->SR = (uint8_t)~(uint8_t)((uint8_t)DAC_IT >> (0x05 - DAC_Channel)); 00815 } 00816 00817 /** 00818 * @} 00819 */ 00820 00821 /** 00822 * @} 00823 */ 00824 00825 /** 00826 * @} 00827 */ 00828 00829 /** 00830 * @} 00831 */ 00832 00833 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/