00001 /**
00002   ******************************************************************************
00003   * @file    stm8l15x_aes.c
00004   * @author  MCD Application Team
00005   * @version V1.5.0
00006   * @date    13-May-2011
00007   * @brief   This file provides firmware functions to manage the following 
00008   *          functionalities of the Advanced Encryption Standard (AES) peripheral:           
00009   *           - Configuration
00010   *           - Read/Write operations
00011   *           - DMA transfers management  
00012   *           - Interrupts and flags management
00013   *
00014   *  @verbatim  
00015   *          ===================================================================
00016   *                                 How to use this driver
00017   *          ===================================================================  
00018   *          1- Enable AES clock to get write access to AES registers
00019   *             using CLK_PeripheralClockConfig(CLK_Peripheral_AES, ENABLE);
00020   *
00021   *          2- Configure the AES operation mode using AES_OperationModeConfig()
00022   *
00023   *          3- If required, enable interrupt source using AES_ITConfig()
00024   *
00025   *          4- If required, when using the DMA mode 
00026   *               - Configure the DMA using DMA_Init()
00027   *               - Enable DMA requests using AES_DMAConfig()
00028   *
00029   *          5- Enable the AES peripheral using AES_Cmd()
00030   *
00031   *          6- Write data/key using AES_WriteSubData() / AES_WriteSubKey()
00032   *            
00033   *  @endverbatim   
00034   ******************************************************************************
00035   * @attention
00036   *
00037   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
00038   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
00039   * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
00040   * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
00041   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
00042   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
00043   *
00044   * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
00045   ******************************************************************************  
00046   */
00047 
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm8l15x_aes.h"
00050 
00051 /** @addtogroup STM8L15x_StdPeriph_Driver
00052   * @{
00053   */
00054   
00055 /** @defgroup AES 
00056   * @brief AES driver modules
00057   * @{
00058   */ 
00059 /* Private typedef -----------------------------------------------------------*/
00060 /* Private define ------------------------------------------------------------*/
00061 /* Private macro -------------------------------------------------------------*/
00062 /* Private variables ---------------------------------------------------------*/
00063 /* Private function prototypes -----------------------------------------------*/
00064 /* Private functions ---------------------------------------------------------*/
00065 
00066 /** @defgroup AES_Private_Functions
00067   * @{
00068   */ 
00069 
00070 /** @defgroup AES_Group1 Configuration
00071  *  @brief   Configuration
00072  *
00073 @verbatim   
00074  ===============================================================================
00075                            Configuration
00076  ===============================================================================  
00077 
00078 @endverbatim
00079   * @{
00080   */  
00081   
00082 /**
00083   * @brief   Deinitializes the AES peripheral.
00084   * @param   None.
00085   * @retval  None
00086   */
00087 void AES_DeInit(void)
00088 {
00089   /* Set AES_CR to reset value 0x00, AES_SR is reset by setting ERRC and CCFC bits in CR */
00090   AES->CR = AES_CR_ERRC | AES_CR_CCFC;
00091   AES->DINR = AES_DINR_RESET_VALUE;       /* Set AES_DINR to reset value 0x00 */
00092   AES->DOUTR = AES_DOUTR_RESET_VALUE;     /* Set AES_DOUTR to reset value 0x00 */
00093 }
00094 
00095 /**
00096   * @brief   Configures the AES operation mode.
00097   * @param   AES_Operation : the selected AES operation mode.
00098   *          This parameter can be one of the following values:
00099   *            @arg AES_Operation_Encryp: AES in Encryption mode
00100   *            @arg AES_Operation_KeyDeriv: AES in Key Derivation mode
00101   *            @arg AES_Operation_Decryp: AES in Decryption mode
00102   *            @arg AES_Operation_KeyDerivAndDecryp: AES in Key Derivation and Decryption mode
00103   * @note   The operation mode must be configured when AES peripheral is disabled.
00104   * @retval  None
00105   */
00106 void AES_OperationModeConfig(AES_Operation_TypeDef AES_Operation)
00107 {
00108   /* Check the parameter */
00109   assert_param(IS_AES_MODE(AES_Operation));
00110 
00111   /* Reset the operation mode bits in CR register */
00112   AES->CR &= (uint8_t) (~AES_CR_MODE);
00113 
00114   /* Set the new operaton mode bits in CR register */
00115   AES->CR |= (uint8_t) (AES_Operation);
00116 }
00117 
00118 /**
00119   * @brief  Enable the AES peripheral.
00120   * @param  NewState : The new state of the AES peripheral.
00121     *         This parameter can be: ENABLE or DISABLE.
00122   * @note   AES peripheral can be enabled once operation mode is configured using
00123   *         AES_OperationModeConfig()  
00124   * @retval None
00125   */
00126 void AES_Cmd(FunctionalState NewState)
00127 {
00128   /* Check the parameter */
00129   assert_param(IS_FUNCTIONAL_STATE(NewState));
00130 
00131   if (NewState != DISABLE)
00132   {
00133     AES->CR |= (uint8_t) AES_CR_EN;   /**< AES Enable */
00134   }
00135   else
00136   {
00137     AES->CR &= (uint8_t)(~AES_CR_EN);  /**< AES Disable */
00138   }
00139 }
00140 
00141 /**
00142   * @}
00143   */
00144 
00145 /** @defgroup AES_Group2 AES Read and Write
00146  *  @brief   AES Read and Write
00147  *
00148 @verbatim   
00149  ===============================================================================
00150                         AES Read and Write operations
00151  ===============================================================================  
00152 
00153 @endverbatim
00154   * @{
00155   */
00156 
00157 /**
00158   * @brief  Write data in DINR register to be processed by AES peripheral.
00159   * @param  Data: The data to be processed.
00160   * @note   When an unexpected write to DINR register is detected, WRERR flag is
00161   *         set.
00162   * @retval None
00163   */
00164 void AES_WriteSubData(uint8_t Data)
00165 {
00166   /* Write Data */
00167   AES->DINR = Data;
00168 }
00169 
00170 /**
00171   * @brief  Write key in DINR register.
00172   * @param  Key: The key to be used for encryption/decryption.
00173   * @note   When an unexpected write to DINR register is detected, WRERR flag is
00174   *         set.
00175   * @retval None
00176   */
00177 void AES_WriteSubKey(uint8_t Key)
00178 {
00179   /* Write key */
00180   AES->DINR = Key;
00181 }
00182 
00183 /**
00184   * @brief  Returns the data in DOUTR register processed by AES peripheral.
00185   * @note   When an unexpected read of DOUTR register is detected, RDERR flag is
00186   *         set
00187   * @retval The processed data.
00188   */
00189 uint8_t AES_ReadSubData(void)
00190 {
00191   return AES->DOUTR;
00192 }
00193 
00194 /**
00195   * @brief  Returns the DOUTR register content.
00196   * @retval The derivation key.
00197   * @note   When an unexpected read of DOUTR register is detected, RDERR flag is
00198   *         set.  
00199   */
00200 uint8_t AES_ReadSubKey(void)
00201 {
00202   return AES->DOUTR;
00203 }
00204 
00205 /**
00206   * @}
00207   */
00208 
00209 /** @defgroup AES_Group3 DMA transfers management functions
00210  *  @brief   DMA transfers management function
00211  *
00212 @verbatim   
00213  ===============================================================================
00214                       DMA transfers management functions
00215  ===============================================================================  
00216 
00217 @endverbatim
00218   * @{
00219   */
00220   
00221 /**
00222   * @brief  Configures the AES DMA interface.
00223   * @param  AES_DMATransfer: Specifies the AES DMA transfer.
00224   *          This parameter can be one of the following values:
00225   *            @arg AES_DMATransfer_InOut: DMA requests enabled for input/Output transfer phase
00226   * @param  NewState Indicates the new state of the AES DMA interface.
00227     *         This parameter can be: ENABLE or DISABLE.
00228   * @retval None
00229   * @note   CCF bit has no meaning when DMA requests are enabled (DMAEN = 1).
00230   */
00231 void AES_DMAConfig(AES_DMATransfer_TypeDef AES_DMATransfer, FunctionalState NewState)
00232 {
00233   /* Check the parameter */
00234   assert_param(IS_AES_DMATRANSFER(AES_DMATransfer));
00235 
00236   if (NewState != DISABLE)
00237   {
00238     /* Enable the DMA transfer */
00239     AES->CR |= (uint8_t) AES_DMATransfer;
00240   }
00241   else
00242   {
00243     /* Disable the DMA transfer */
00244     AES->CR &= (uint8_t)(~AES_DMATransfer);
00245   }
00246 }
00247 
00248 
00249 /**
00250   * @}
00251   */
00252 
00253 /** @defgroup AES_Group4 Interrupts and flags management functions
00254  *  @brief   Interrupts and flags management functions
00255  *
00256 @verbatim   
00257 
00258  ===============================================================================
00259                    Interrupts and flags management functions
00260  ===============================================================================
00261 @endverbatim
00262   * @{
00263   */
00264 
00265 /**
00266   * @brief  Enables or disables the specified AES interrupt.
00267   * @param  AES_IT: Specifies the AES interrupt source to enable/disable.
00268   *          This parameter can be one of the following values:
00269   *            @arg AES_IT_CCIE: Computation Complete interrupt enable
00270   *            @arg AES_IT_ERRIE: Error interrupt enable
00271   * @param  NewState : The new state of the AES peripheral.
00272     *         This parameter can be: ENABLE or DISABLE.
00273   * @retval None
00274   */
00275 void AES_ITConfig(AES_IT_TypeDef AES_IT, FunctionalState NewState)
00276 {
00277   /* Check the parameters */
00278   assert_param(IS_FUNCTIONAL_STATE(NewState));
00279   assert_param(IS_AES_IT(AES_IT));
00280 
00281   if (NewState != DISABLE)
00282   {
00283     AES->CR |= (uint8_t) AES_IT;    /**< AES_IT Enable */
00284   }
00285   else
00286   {
00287     AES->CR &= (uint8_t)(~AES_IT);  /**< AES_IT Disable */
00288   }
00289 }
00290 
00291 /**
00292   * @brief  Checks whether the specified AES flag is set or not.
00293   * @param  AES_FLAG specifies the flag to check.
00294   *          This parameter can be one of the following values:
00295   *            @arg AES_FLAG_CCF: Computation Complete Flag
00296   *            @arg AES_FLAG_RDERR: Read Error Flag
00297   *            @arg AES_FLAG_WRERR: Write Error Flag 
00298   * @retval FlagStatus (SET or RESET)
00299   * @note   CCF bit has a meaning only when DMA requests are disabled (DMAEN bit = 0).
00300   */
00301 FlagStatus AES_GetFlagStatus(AES_FLAG_TypeDef AES_FLAG)
00302 {
00303   FlagStatus status = RESET;
00304 
00305   /* Check parameters */
00306   assert_param(IS_AES_FLAG(AES_FLAG));
00307 
00308   if (AES_FLAG == AES_FLAG_CCF)
00309   {
00310     if ((AES->SR & (uint8_t)AES_FLAG_CCF) != (uint8_t)0x00)
00311     {
00312       /* Computation Complete Flag CCF is set */
00313       status = (FlagStatus) SET;
00314     }
00315     else
00316     {
00317       /* Computation Complete Flag CCF is reset */
00318       status = (FlagStatus) RESET;
00319     }
00320   }
00321   else if (AES_FLAG == AES_FLAG_RDERR)
00322   {
00323     if ((AES->SR & (uint8_t)AES_FLAG_RDERR) != (uint8_t)0x00)
00324     {
00325       /* Read Error Flag RDERR is set */
00326       status = (FlagStatus) SET;
00327     }
00328     else
00329     {
00330       /* Read Error Flag RDERR is reset */
00331       status = (FlagStatus) RESET;
00332     }
00333   }
00334   else
00335   {
00336     if ((AES->SR & (uint8_t)AES_FLAG_WRERR) != (uint8_t)0x00)
00337     {
00338       /* Write Error Flag WRERR is set */
00339       status = (FlagStatus) SET;
00340     }
00341     else
00342     {
00343       /* Write Error Flag WRERR is reset */
00344       status = (FlagStatus) RESET;
00345     }
00346   }
00347   /* Return the AES_FLAG status */
00348   return ((FlagStatus) status);
00349 }
00350 
00351 /**
00352   * @brief  Clears the AES flags.
00353   * @param  AES_FLAG: specifies the flag to clear.
00354   *          This parameter can be one of the following values:
00355   *            @arg AES_FLAG_CCF: Computation Complete Flag
00356   *            @arg AES_FLAG_RDERR: Read Error Flag
00357   *            @arg AES_FLAG_WRERR: Write Error Flag 
00358   * @retval None
00359   */
00360 void AES_ClearFlag(AES_FLAG_TypeDef AES_FLAG)
00361 {
00362   /* Check the parameters */
00363   assert_param(IS_AES_FLAG(AES_FLAG));
00364 
00365   /* Check if AES_FLAG is AES_FLAG_CCF */
00366   if (AES_FLAG == AES_FLAG_CCF)
00367   {
00368     /* Clear CCF flag by setting CCFC bit */
00369     AES->CR |= (uint8_t) AES_CR_CCFC;
00370   }
00371   else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */
00372   {
00373     /* Clear RDERR and WRERR flags by setting ERRC bit */
00374     AES->CR |= (uint8_t) AES_CR_ERRC;
00375   }
00376 }
00377 
00378 /**
00379   * @brief  Checks whether the specified AES interrupt has occurred or not.
00380   * @param  AES_IT: Specifies the AES interrupt pending bit to check.
00381   *          This parameter can be one of the following values:
00382   *            @arg AES_IT_CCIE: Computation Complete interrupt enable
00383   *            @arg AES_IT_ERRIE: Error interrupt enable
00384   * @retval ITStatus The new state of AES_IT (SET or RESET).
00385   */
00386 ITStatus AES_GetITStatus(AES_IT_TypeDef AES_IT)
00387 {
00388   ITStatus itstatus = RESET;
00389   BitStatus cciebitstatus, ccfbitstatus = RESET;
00390 
00391   /* Check parameters */
00392   assert_param(IS_AES_IT(AES_IT));
00393 
00394   cciebitstatus = (BitStatus) (AES->CR & AES_CR_CCIE);
00395   ccfbitstatus =  (BitStatus) (AES->SR & AES_SR_CCF);
00396 
00397   /* Check if AES_IT is AES_IT_CCIE */
00398   if (AES_IT == AES_IT_CCIE)
00399   {
00400     /* Check the status of the specified AES interrupt */
00401     if (((cciebitstatus) != RESET) && ((ccfbitstatus) != RESET))
00402     {
00403       /* Interrupt occurred */
00404       itstatus = (ITStatus) SET;
00405     }
00406     else
00407     {
00408       /* Interrupt not occurred */
00409       itstatus = (ITStatus) RESET;
00410     }
00411   }
00412   else /* AES_IT is AES_IT_ERRIE */
00413   {
00414     /* Check the status of the specified AES interrupt */
00415     if ((AES->CR & AES_CR_ERRIE) != RESET)
00416     {
00417       /* Check if WRERR or RDERR flags are set */
00418       if ((AES->SR & (uint8_t)(AES_SR_WRERR | AES_SR_RDERR)) != RESET)
00419       {
00420         /* Interrupt occurred */
00421         itstatus = (ITStatus) SET;
00422       }
00423       else
00424       {
00425         /* Interrupt not occurred */
00426         itstatus = (ITStatus) RESET;
00427       }
00428     }
00429     else
00430     {
00431       /* Interrupt not occurred */
00432       itstatus = (ITStatus) RESET;
00433     }
00434   }
00435 
00436   /* Return the AES_IT status */
00437   return ((ITStatus)itstatus);
00438 }
00439 
00440 /**
00441   * @brief  Clears the AES's interrupt pending bits.
00442   * @param  AES_IT: specifies the interrupt pending bit to clear.
00443   *          This parameter can be one of the following values:
00444   *            @arg AES_IT_CCIE: Computation Complete interrupt enable
00445   *            @arg AES_IT_ERRIE: Error interrupt enable
00446   * @retval None
00447   */
00448 void AES_ClearITPendingBit(AES_IT_TypeDef AES_IT)
00449 {
00450   /* Check the parameters */
00451   assert_param(IS_AES_IT(AES_IT));
00452 
00453   /* Check if AES_IT is AES_IT_CCIE */
00454   if (AES_IT == AES_IT_CCIE)
00455   {
00456     /* Clear CCF flag by setting CCFC bit */
00457     AES->CR |= (uint8_t) AES_CR_CCFC;
00458   }
00459   else /* AES_IT is AES_IT_ERRIE */
00460   {
00461     /* Clear RDERR and WRERR flags by setting ERRC bit */
00462     AES->CR |= (uint8_t) AES_CR_ERRC;
00463   }
00464 }
00465 
00466 /**
00467   * @}
00468   */ 
00469 
00470 /**
00471   * @}
00472   */
00473 
00474 /**
00475   * @}
00476   */ 
00477 
00478 /**
00479   * @}
00480   */ 
00481 
00482 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/