Extended 16-Bit Core Instruction Set

Extended 16-Bit Core Instruction Set

Microchip's new high-performance 8-bit microcontroller family uses a 16-bit wide instruction set. This instruction set consists of 76 instructions, each a single 16-bit wide word (2 bytes). Most instructions operate on a file register, f, and the working register, WREG (accumulator). The result can be directed either to the file register or the WREG register or to both in the case of some instructions. A few instructions operate solely on a file register (BSF for example).

Table: Extended 16-Bit Core Byte-Oriented Register Operations 

Hex	Mnemonic		Description	Function
27f*	ADDWF	f,d,a	ADD WREG to f	WREG+f → dest
23f*	ADDWFC	f,d,a	ADD WREG and Carry bit to f	WREG+f+C → dest
17f*	ANDWF	f,d,a	AND WREG with f	WREG .AND. f → dest
6Bf*	CLRF	f,a	Clear f	0 → f
1Ff*	COMF	f,d,a	Complement f	.NOT. f → dest
63f*	CPFSEQ	f,a	Compare f with WREG, skip if f=WREG	f-WREG, if f=WREG, PC+4 → PC else PC+2 → PC
65f*	CPFSGT	f,a	Compare f with WREG, skip if f > WREG	f-WREG, if f > WREG, PC+4 → PC else PC+2 → PC
61f*	CPFSLT	f,a	Compare f with WREG, skip if f < WREG	f-WREG, if f < WREG, PC+4 → PC else PC+2 → PC
07f*	DECF	f,d,a	Decrement f	f-1 → dest
2Ff*	DECFSZ	f,d,a	Decrement f, skip if 0	f-1 → dest, if dest=0, PC+4 → PC else PC+2 → PC
4Ff*	DCFSNZ	f,d,a	Decrement f, skip if not 0	f-1 → dest, if dest ¼ 0, PC+4 → PC else PC+2 → PC
2Bf*	INCF	f,d,a	Increment f	f+1 → dest
3Ff*	INCFSZ	f,d,a	Increment f, skip if 0	f+1 → dest, if dest=0, PC+4 → PC else PC+2 → PC
4Bf*	INFSNZ	f,d,a	Increment f, skip if not 0	f+1 → dest, if dest ¼ 0, PC+4 → PC else PC+2 → PC
13f*	IORWF	f,d,a	Inclusive OR WREG with f	WREG .OR. f → dest
53f*	MOVF	f,d,a	Move f	f → dest
Cf' Ff"	MOVFF	f',f"	Move f' to fd" (second word)	f' → f"
6Ff*	MOVWF	f,a	Move WREG to f	WREG → f
03f*	MULWF	f,a	Multiply WREG with f	WREG * f → PRODH:PRODL
6Df*	NEGF	f,a	Negate f	-f → f
37f*	RLCF	f,d,a	Rotate left f through Carry
47f*	RLNCF	f,d,a	Rotate left f (no carry)
33f*	RRCF	f,d,a	Rotate right f through Carry
43f*	RRNCF	f,d,a	Rotate right f (no carry)
69f*	SETF	f,a	Set f	0xFF → f
57f*	SUBFWB	f,d,a	Subtract f from WREG with Borrow	WREG-f-C → dest
5Ff*	SUBWF	f,d,a	Subtract WREG from f	f-WREG → dest
5Bf*	SUBWFB	f,d,a	Subtract WREG from f with Borrow	f-WREG-C → dest
3Bf*	SWAPF	f,d,a	Swap nibbles of f	f<3:0> → dest<7:4>, f<7:4> → dest<3:0>
67f*	TSTFSZ	f,a	Test f, skip if 0	PC+4 → PC, if f=0, else PC+2 → PC
1Bf*	XORWF	f,d,a	Exclusive OR WREG with f	WREG .XOR. f → dest
* Assuming default bit values for d and a.

Table: Extended 16-Bit Core Bit-Oriented Register Operations 

Hex	Mnemonic		Description	Function
91f*	BCF	f,b,a	Bit Clear f	0 → f<b>
81f*	BSF	f,b,a	Bit Set f	1 → f<b>
B1f*	BTFSC	f,b,a	Bit test f, skip if clear	if f<b>=0, PC+4→PC, else PC+2→PC
A1f*	BTFSS	f,b,a	Bit test f, skip if set	if f<b>=1, PC+4→PC, else PC+2→PC
71f*	BTG	f,b,a	Bit Toggle f	f<b> → f<b>
* Assuming b = 0 and default bit value for a.

Table: Extended 16-Bit Core Control Operations 

Hex	Mnemonic		Description	Function
E2n	BC	n	Branch if Carry	if C=1, PC+2+2*n→ PC, else PC+2→PC
E6n	BN	n	Branch if Negative	if N=1, PC+2+2*n→PC,else PC+2→PC
E3n	BNC	n	Branch if Not Carry	if C=0, PC+2+2*n→PC, else PC+2→PC
E7n	BNN	n	Branch if Not Negative	if N=0, PC+2+2*n→PC, else PC+2→PC
E5n	BNOV	n	Branch if Not Overflow	if OV=0, PC+2+2*n→PC, else PC+2→PC
E1n	BNZ	n	Branch if Not Zero	if Z=0, PC+2+2*n→PC, else PC+2→PC
E4n	BOV	n	Branch if Overflow	if OV=1, PC+2+2*n→PC, else PC+2→PC
D'0'n	BRA	n	Branch Unconditionally	PC+2+2*n→ PC
E0n	BZ	n	Branch if Zero	if Z=1, PC+2+2*n→PC, else PC+2→PC
ECkk* Fkkk	CALL	n,s	Call Subroutine 1st word 2nd word	PC+4 → TOS, n → PC<20:1>, if s=1, WREG → WREGs, STATUS → STATUSs, BSR → BSRs
0004	CLRWDT		Clear Watchdog Timer	0 → WDT, 0 → WDT postscaler, 1 → TO,1 → PD
0007	DAW		Decimal Adjust WREG	if WREG<3:0> >9 or DC=1, WREG<3:0>+6→WREG<3:0>, else WREG<3:0> → WREG<3:0>; if WREG<7:4> >9 or C=1, WREG<7:4>+6→WREG<7:4>, else WREG<7:4> → WREG<7:4>;
EFkk Fkkk	GOTO	n	Go to address 1st word 2nd word	n → PC<20:1>
0000	NOP		No Operation	No Operation
Fxxx	NOP		No Operation	No Operation (2-word instructions)
0006	POP		Pop top of return stack (TOS)	TOS-1 → TOS
0005	PUSH		Push top of return stack (TOS)	PC +2→ TOS
D'1'n	RCALL	n	Relative Call	PC+2 → TOS, PC+2+2*n→PC
00FF	RESET		Software device reset	Same as MCLR reset
0010*	RETFIE	s	Return from interrupt (and enable interrupts)	TOS → PC, 1 → GIE/GIEH or PEIE/GIEL, if s=1, WREGs → WREG, STATUSs → STATUS, BSRs → BSR, PCLATU/PCLATH unchngd.
0012*	RETURN	s	Return from subroutine	TOS → PC, if s=1, WREGs → WREG, STATUSs → STATUS, BSRs → BSR, PCLATU/PCLATH are unchanged
0003	SLEEP		Enter SLEEP Mode	0 → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD
* Assuming default bit value for s.

Table: Extended 16-Bit Core Literal Operations 

Hex	Mnemonic		Description	Function
0Fkk	ADDLW	kk	Add literal to WREG	WREG+kk → WREG
0Bkk	ANDLW	kk	AND literal with WREG	WREG .AND. kk → WREG
09kk	IORLW	kk	Inclusive OR literal with WREG	WREG .OR. kk → WREG
EErk F0kk	LFSR	r,kk	Move literal (12 bit) 2nd word to FSRr 1st word	kk → FSRr
010k	MOVLB	k	Move literal to BSR<3:0>	kk → BSR
0Ekk	MOVLW	kk	Move literal to WREG	kk → WREG
0Dkk	MULLW	kk	Multiply literal with WREG	WREG * kk→ PRODH:PRODL
0Ckk	RETLW	kk	Return with literal in WREG	kk → WREG
08kk	SUBLW	kk	Subtract WREG from literal	kk-WREG → WREG
0Akk	XORLW	kk	Exclusive OR literal with WREG	WREG .XOR. kk → WREG

Table: Extended 16-Bit Core Memory Operations 

Hex	Mnemonic	Description	Function
0008	TBLRD*	Table Read	Prog Mem (TBLPTR) → TABLAT
0009	TBLRD*+	Table Read with post-increment	Prog Mem (TBLPTR) → TABLAT TBLPTR +1 → TBLPTR
000A	TBLRD*-	Table Read with post-decrement	Prog Mem (TBLPTR) → TABLAT TBLPTR -1 → TBLPTR
000B	TBLRD+*	Table Read with pre-increment	TBLPTR +1 → TBLPTR Prog Mem (TBLPTR) → TABLAT
000C	TBLWT*	Table Write	TABLAT → Prog Mem(TBLPTR)
000D	TBLWT*+	Table Write with post-increment	TABLAT → Prog Mem(TBLPTR) TBLPTR +1 → TBLPTR
000E	TBLWT*-	Table Write with post-decrement	TABLAT → Prog Mem(TBLPTR) TBLPTR -1 → TBLPTR
000F	TBLWT+*	Table Write with pre-increment	TBLPTR +1 → TBLPTR TABLAT → Prog Mem(TBLPTR)