12-Bit Core Instruction Set
Microchip's base-line 8-bit microcontroller family uses a 12-bit wide instruction set. All instructions execute in a single instruction cycle unless otherwise noted. Any unused opcode is executed as a NOP.
The instruction set is grouped into the following catagories: Byte-oriented file register operations, bit-oriented file register operations, and core literal and control operations. Instructions are listed by catagory in the tables below. Instruction opcode is show in Hex by certain making assumptions, either listed in the key or as a footnote. For more information on the opcode bit values for each instruction, as well as the number of cycles per instruction, status bits affected and complete instruction details, see the relevent device data sheet.
Table: 12-Bit Core Byte-Oriented File Register Operations
|
Hex
|
Mnemonic
|
Description
|
Function
|
|
1Ef*
|
ADDWF
|
f,d
|
Add W and f
|
WREG + f → dest
|
|
16f*
|
ANDWF
|
f,d
|
AND W and f
|
WREG .AND. f → dest
|
|
06f
|
CLRF
|
f
|
Clear f
|
0 → f
|
|
040
|
CLRW
|
|
Clear W
|
0 → WREG
|
|
26f*
|
COMF
|
f,d
|
Complement f
|
.NOT. f → dest
|
|
0Ef*
|
DECF
|
f,d
|
Decrement f
|
f - 1 → dest
|
|
2Ef*
|
DECFSZ
|
f,d
|
Decrement f, skip if zero
|
f - 1 → dest, skip if zero
|
|
2Af*
|
INCF
|
f,d
|
Increment f
|
f + 1 → dest
|
|
3Ef*
|
INCFSZ
|
f,d
|
Increment f, skip if zero
|
f + 1 → dest, skip if zero
|
|
12f*
|
IORWF
|
f,d
|
Inclusive OR W and f
|
WREG .OR. f → dest
|
|
22f*
|
MOVF
|
f,d
|
Move f
|
f → dest
|
|
02f
|
MOVWF
|
f
|
Move W to f
|
WREG → f
|
|
000
|
NOP
|
|
No operation
|
|
|
36f*
|
RLF
|
f,d
|
Rotate left f
|
|
|
32f*
|
RRF
|
f,d
|
Rotate right f
|
|
|
0Af*
|
SUBWF
|
f,d
|
Subtract W from f
|
f - WREG → dest
|
|
3Af*
|
SWAPF
|
f,d
|
Swap halves f
|
f(0:3) ↔ f(4:7) → dest
|
|
1Af*
|
XORWF
|
f,d
|
Exclusive OR W and f
|
WREG .XOR. f → dest
|
|
* Assuming default bit value for d.
|
Table: 12-Bit Core Bit-Oriented File Register Operations
|
Hex
|
Mnemonic
|
Description
|
Function
|
|
4bf
|
BCF
|
f,b
|
Bit clear f
|
0 → f(b)
|
|
5bf
|
BSF
|
f,b
|
Bit set f
|
1 → f(b)
|
|
6bf
|
BTFSC
|
f,b
|
Bit test, skip if clear
|
skip if f(b) = 0
|
|
7bf
|
BTFSS
|
f,b
|
Bit test, skip if set
|
skip if f(b) = 1
|
Table: 12-Bit Core Literal and Control Operations
|
Hex
|
Mnemonic
|
Description
|
Function
|
|
Ekk
|
ANDLW
|
kk
|
AND literal and W
|
kk .AND. WREG → WREG
|
|
9kk
|
CALL
|
kk
|
Call subroutine
|
PC + 1 → TOS, kk → PC
|
|
004
|
CLRWDT
|
|
Clear watchdog timer
|
0 → WDT (and Prescaler if assigned)
|
|
Akk
|
GOTO
|
kk
|
Goto address (k is nine bits)
|
kk → PC(9 bits)
|
|
Dkk
|
IORLW
|
kk
|
Incl. OR literal and W
|
kk .OR. WREG → WREG
|
|
Ckk
|
MOVLW
|
kk
|
Move Literal to W
|
kk → WREG
|
|
002
|
OPTION
|
|
Load OPTION Register
|
WREG → OPTION Register
|
|
8kk
|
RETLW
|
kk
|
Return with literal in W
|
kk → WREG, TOS → PC
|
|
003
|
SLEEP
|
|
Go into Standby Mode
|
0 → WDT, stop oscillator
|
|
00r
|
TRIS
|
r
|
Tristate port r
|
WREG → I/O control reg r
|
|
Fkk
|
XORLW
|
kk
|
Exclusive OR literal and W
|
kk .XOR. WREG → WREG
|
