16-Bit Core Instruction Set

16-Bit Core Instruction Set

Microchip's high-performance 8-bit microcontroller family uses a 16-bit wide instruction set. This instruction set consists of 55 instructions, each a single 16-bit wide word. Most instructions operate on a file register, f, and the working register, WREG (accumulator). The result can be directed either to the file register or the WREG register or to both in the case of some instructions. Some devices in this family also include hardware multiply instructions. A few instructions operate solely on a file register (BSF for example).

The instruction set is grouped into the following catagories: Byte-oriented file register operations, bit-oriented file register operations, and core literal and control operations. Instructions are listed by catagory in the tables below. Instruction opcode is show in Hex by certain making assumptions, either listed in the key or as a footnote. For more information on the opcode bit values for each instruction, as well as the number of cycles per instruction, status bits affected and complete instruction details, see the relevent device data sheet.

Table: 16-Bit Byte-Oriented File Register Operations 

Hex	Mnemonic		Description	Function
0Ff*	ADDWF	f,d	Add WREG to F	(WREG + f) → dest
11f*	ADDWFC	f,d	Add WREG and Carry to f	(WREG + f + C) → dest
0Bf*	ANDWF	f,d	AND WREG with f	(WREG .AND. f) → dest
29f*	CLRF	f,s	Clear dest	0x00 → dest
13f*	COMF	f,d	Complement f	.NOT. f → dest
31f	CPFSEQ	f	Compare f, WREG, skip if f = WREG	f-WREG, skip if f = WREG
32f	CPFSGT	f	Compare f, WREG, skip if f > WREG	f-WREG, skip if f > WREG
30f	CPFSLT	f	Compare f, WREG, skip if f< WREG	f-WREG, skip if f < WREG
2Ff*	DAW	f,s	Dec. adjust WREG, store in dest	WREG adjusted → dest
07f*	DECF	f,d	Decrement f	(f - 1) → dest
17f*	DECFSZ	f,d	Decrement f, skip if 0	(f - 1) → dest, skip if 0
27f*	DCFSNZ	f,d	Decrement f, skip if not 0	(f - 1) → dest, skip if not 0
15f*	INCF	f,d	Increment f	(f + 1) → dest
1Ff*	INCFSZ	f,d	Increment f, skip if zero	(f + 1) → dest, skip if 0
25f*	INFSNZ	f,d	Increment f, skip if not zero	(f + 1) → dest, skip if not 0
09f*	IORWF	f,d	Inclusive or WREG with f	(WREG .OR. f) → dest
6pf	MOVFP	f,p	Move f to p	f → p
4pf	MOVPF	p,f	Move p to f	p → f
01f	MOVWF	f	Move WREG to F	WREG → f
34f	MULWF	f	Multiply WREG and f	(WREG x f) → PRODH:PRODL
2Df*	NEGW	f,s	Negate WREG, store in dest	-WREG → dest
0000	NOP		No operation	No operation
1Bf*	RLCF	f,d	Rotate left through carry
23f*	RLNCF	f,d	Rotate left (no carry)
19f*	RRCF	f,d	Rotate right through carry
21f*	RRNCF	f,d	Rotate right (no carry)
2Af*	SETF	f,s	Set dest	0xFF → dest
05f*	SUBWF	f,d	Subtract WREG from f	(f - WREG) → d
03f*	SUBWFB	f,d	Subtract from f with borrow	(f - WREG - c) → d
1Df*	SWAPF	f,d	Swap f	f(0:3) → d(4:7), f(4:7) → d(0:3)
A8f	TABLRD	t,i,f	Read data from table latch into file f, then update table latch with 16-bit contents of memory location addressed by table pointer	TBLATH → f if t=1, TBLATL → f if t=0; ProgMem(TBLPTR) → TBLAT; TBLPTR + 1 → TBLPTR if i=1
ACf	TABLWT	t,i,f	Write data from file f to table latch and then write 16-bit table latch to program memory location addressed by table pointer	f → TBLATH if t = 1, f → TBLATL if t = 0; TBLAT → ProgMem(TBLPTR); TBLPTR + 1 → TBLPTR if i=1
A0f	TLRD	t,f	Read data from table latch into file f (table latch unchanged)	TBLATH → f if t = 1 TBLATL → f if t = 0
A4f	TLWT	t,f	Write data from file f into table latch	f → TBLATH if t = 1 f → TBLATL if t = 0
33f	TSTFSZ	f	Test f, skip if zero	skip if f = 0
0Df*	XORWF	f,d	Exclusive OR WREG with f	(WREG .XOR. f) → dest
* Assuming default bit values for d and s.

Table: 16-Bit Core Bit-Oriented File Register Operations 

Hex	Mnemonic		Description	Function
8'1'bf	BCF	f,b	Bit clear f	0 → f(b)
8'0'bf	BSF	f,b	Bit set f	1 → f(b)
9'1'bf	BTFSC	f,b	Bit test, skip if clear	skip if f(b) = 0
9'0'bf	BTFSS	f,b	Bit test, skip if set	skip if f(b) = 1
3'1'bf	BTG	f,b	Bit toggle f	.NOT. f(b) → f(b)

Table: 16-Bit Core Literal and Control Operations 

Hex	Mnemonic		Description	Function
B1kk	ADDLW	kk	Add literal to WREG	(WREG + kk) → WREG
B5kk	ANDLW	kk	AND Literal and WREG	(WREG .AND. kk) → WREG
Ekkk	CALL	kkk	Subroutine call (within 8k page)	PC+1 → TOS,k → PC(12:0), k(12:8) → PCLATH(4:0), PC(15:13) → PCLATH(7:5)
0004	CLRWT		Clear watchdog timer	0 → WDT,0→ WDT prescaler, 1 → PD, 1 → TO
Ckkk	GOTO	kkk	Unconditional branch (within 8k)	k → PC(12:0) k(12:8) → PCLATH(4:0), PC(15:13) → PCLATH(7:5)
B3kk	IORLW	kk	Inclusive OR literal with W	(WREG .OR. kk) → WREG
B7kk	LCALL	kk	Long Call (within 64k)	(PC+1) → TOS; kk → PCL, (PCLATH)→ PCH
B8xk	MOVLB	k	Move literal to low nibble in BSR	k → BSR (3:0)
BAkx	MOVLR	k	Move literal to high nibble in BSR	k → BSR (7:4)
B0kk	MOVLW	kk	Move literal to WREG	kk → WREG
BCkk	MULLW	kk	Multiply literal and WREG	(kk x WREG) → PRODH:PRODL
0005	RETFIE		Return from interrupt, enable interrupt	(PCLATH) → PCH:k → PCL 0 → GLINTD
B6kk	RETLW	kk	Return with literal in WREG	kk → W, TOS → PC, (PCLATH unchanged)
0002	RETURN		Return from subroutine	TOS → PC (PCLATH unchanged)
0003	SLEEP		Enter Sleep Mode	Stop oscillator,power down, 0 → WDT, 0 → WDT Prescaler 1 → PD, 1 → TO
B2kk	SUBLW	kk	Subtract WREG from literal	(kk - WREG) → WREG
B4kk	XORLW	kk	Exclusive OR literal with WREG	(WREG .XOR. kk) → WREG