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STM8L15x Standard Peripherals Drivers
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stm8l15x_tim5.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_tim5.h 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file contains all the functions prototypes for the TIM5 firmware 00008 * library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00013 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00014 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00015 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00016 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00017 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00018 * 00019 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00020 ****************************************************************************** 00021 */ 00022 00023 /* Define to prevent recursive inclusion -------------------------------------*/ 00024 #ifndef __STM8L15x_TIM5_H 00025 #define __STM8L15x_TIM5_H 00026 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm8l15x.h" 00030 00031 /** @addtogroup STM8L15x_StdPeriph_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup TIM5 00036 * @{ 00037 */ 00038 /* Exported types ------------------------------------------------------------*/ 00039 00040 /** @defgroup TIM5_Exported_Types 00041 * @{ 00042 */ 00043 00044 /** @defgroup TIM5_Forced_Action 00045 * @{ 00046 */ 00047 typedef enum 00048 { 00049 TIM5_ForcedAction_Active = ((uint8_t)0x50), /*!< Output Reference is forced low */ 00050 TIM5_ForcedAction_Inactive = ((uint8_t)0x40) /*!< Output Reference is forced high */ 00051 } 00052 TIM5_ForcedAction_TypeDef; 00053 00054 #define IS_TIM5_FORCED_ACTION(ACTION) (((ACTION) == TIM5_ForcedAction_Active) || \ 00055 ((ACTION) == TIM5_ForcedAction_Inactive)) 00056 /** 00057 * @} 00058 */ 00059 00060 /** @defgroup TIM5_Prescaler 00061 * @{ 00062 */ 00063 typedef enum 00064 { 00065 TIM5_Prescaler_1 = ((uint8_t)0x00), /*!< Time base Prescaler = 1 (No effect)*/ 00066 TIM5_Prescaler_2 = ((uint8_t)0x01), /*!< Time base Prescaler = 2 */ 00067 TIM5_Prescaler_4 = ((uint8_t)0x02), /*!< Time base Prescaler = 4 */ 00068 TIM5_Prescaler_8 = ((uint8_t)0x03), /*!< Time base Prescaler = 8 */ 00069 TIM5_Prescaler_16 = ((uint8_t)0x04), /*!< Time base Prescaler = 16 */ 00070 TIM5_Prescaler_32 = ((uint8_t)0x05), /*!< Time base Prescaler = 32 */ 00071 TIM5_Prescaler_64 = ((uint8_t)0x06), /*!< Time base Prescaler = 64 */ 00072 TIM5_Prescaler_128 = ((uint8_t)0x07) /*!< Time base Prescaler = 128 */ 00073 }TIM5_Prescaler_TypeDef; 00074 00075 #define IS_TIM5_PRESCALER(PRESCALER) (((PRESCALER) == TIM5_Prescaler_1) || \ 00076 ((PRESCALER) == TIM5_Prescaler_2) || \ 00077 ((PRESCALER) == TIM5_Prescaler_4) || \ 00078 ((PRESCALER) == TIM5_Prescaler_8) || \ 00079 ((PRESCALER) == TIM5_Prescaler_16) || \ 00080 ((PRESCALER) == TIM5_Prescaler_32) || \ 00081 ((PRESCALER) == TIM5_Prescaler_64) || \ 00082 ((PRESCALER) == TIM5_Prescaler_128)) 00083 /** 00084 * @} 00085 */ 00086 00087 /** @defgroup TIM5_OCMode 00088 * @{ 00089 */ 00090 typedef enum 00091 { 00092 TIM5_OCMode_Timing = ((uint8_t)0x00), /*!< Timing (Frozen) Mode*/ 00093 TIM5_OCMode_Active = ((uint8_t)0x10), /*!< Active Mode*/ 00094 TIM5_OCMode_Inactive = ((uint8_t)0x20), /*!< Inactive Mode*/ 00095 TIM5_OCMode_Toggle = ((uint8_t)0x30), /*!< Toggle Mode*/ 00096 TIM5_OCMode_PWM1 = ((uint8_t)0x60), /*!< PWM Mode 1*/ 00097 TIM5_OCMode_PWM2 = ((uint8_t)0x70) /*!< PWM Mode 2*/ 00098 }TIM5_OCMode_TypeDef; 00099 00100 #define IS_TIM5_OC_MODE(MODE) (((MODE) == TIM5_OCMode_Timing) || \ 00101 ((MODE) == TIM5_OCMode_Active) || \ 00102 ((MODE) == TIM5_OCMode_Inactive) || \ 00103 ((MODE) == TIM5_OCMode_Toggle) || \ 00104 ((MODE) == TIM5_OCMode_PWM1) || \ 00105 ((MODE) == TIM5_OCMode_PWM2)) 00106 00107 #define IS_TIM5_OCM(MODE) (((MODE) == TIM5_OCMode_Timing) || \ 00108 ((MODE) == TIM5_OCMode_Active) || \ 00109 ((MODE) == TIM5_OCMode_Inactive) || \ 00110 ((MODE) == TIM5_OCMode_Toggle) || \ 00111 ((MODE) == TIM5_OCMode_PWM1) || \ 00112 ((MODE) == TIM5_OCMode_PWM2) || \ 00113 ((MODE) == (uint8_t)TIM5_ForcedAction_Active) || \ 00114 ((MODE) == (uint8_t)TIM5_ForcedAction_Inactive)) 00115 /** 00116 * @} 00117 */ 00118 00119 /** @defgroup TIM5_OnePulseMode 00120 * @{ 00121 */ 00122 typedef enum 00123 { 00124 TIM5_OPMode_Single = ((uint8_t)0x01), /*!< Single one Pulse mode (OPM Active) */ 00125 TIM5_OPMode_Repetitive = ((uint8_t)0x00) /*!< Repetitive Pulse mode (OPM inactive) */ 00126 }TIM5_OPMode_TypeDef; 00127 00128 #define IS_TIM5_OPM_MODE(MODE) (((MODE) == TIM5_OPMode_Single) || \ 00129 ((MODE) == TIM5_OPMode_Repetitive)) 00130 /** 00131 * @} 00132 */ 00133 00134 /** @defgroup TIM5_Channel 00135 * @{ 00136 */ 00137 typedef enum 00138 { 00139 TIM5_Channel_1 = ((uint8_t)0x00), /*!< Channel 1*/ 00140 TIM5_Channel_2 = ((uint8_t)0x01) /*!< Channel 2*/ 00141 }TIM5_Channel_TypeDef; 00142 00143 #define IS_TIM5_CHANNEL(CHANNEL) (((CHANNEL) == TIM5_Channel_1) || \ 00144 ((CHANNEL) == TIM5_Channel_2) ) 00145 /** 00146 * @} 00147 */ 00148 00149 /** @defgroup TIM5_CounterMode 00150 * @{ 00151 */ 00152 typedef enum 00153 { 00154 TIM5_CounterMode_Up = ((uint8_t)0x00), /*!< Counter Up Mode */ 00155 TIM5_CounterMode_Down = ((uint8_t)0x10), /*!< Counter Down Mode */ 00156 TIM5_CounterMode_CenterAligned1 = ((uint8_t)0x20), /*!< Counter Central aligned Mode 1 */ 00157 TIM5_CounterMode_CenterAligned2 = ((uint8_t)0x40), /*!< Counter Central aligned Mode 2 */ 00158 TIM5_CounterMode_CenterAligned3 = ((uint8_t)0x60) /*!< Counter Central aligned Mode 3 */ 00159 }TIM5_CounterMode_TypeDef; 00160 00161 #define IS_TIM5_COUNTER_MODE(MODE) (((MODE) == TIM5_CounterMode_Up) || \ 00162 ((MODE) == TIM5_CounterMode_Down) || \ 00163 ((MODE) == TIM5_CounterMode_CenterAligned1) || \ 00164 ((MODE) == TIM5_CounterMode_CenterAligned2) || \ 00165 ((MODE) == TIM5_CounterMode_CenterAligned3)) 00166 /** 00167 * @} 00168 */ 00169 00170 /** @defgroup TIM5_Output_Compare_Polarity 00171 * @{ 00172 */ 00173 typedef enum 00174 { 00175 TIM5_OCPolarity_High = ((uint8_t)0x00), /*!< Output compare polarity = High */ 00176 TIM5_OCPolarity_Low = ((uint8_t)0x01) /*!< Output compare polarity = Low */ 00177 }TIM5_OCPolarity_TypeDef; 00178 00179 #define IS_TIM5_OC_POLARITY(POLARITY) (((POLARITY) == TIM5_OCPolarity_High) || \ 00180 ((POLARITY) == TIM5_OCPolarity_Low)) 00181 /** 00182 * @} 00183 */ 00184 00185 /** @defgroup TIM5_Output_State 00186 * @{ 00187 */ 00188 typedef enum 00189 { 00190 TIM5_OutputState_Disable = ((uint8_t)0x00), /*!< Output compare State disabled (channel output disabled) */ 00191 TIM5_OutputState_Enable = ((uint8_t)0x01) /*!< Output compare State enabled (channel output enabled) */ 00192 }TIM5_OutputState_TypeDef; 00193 00194 #define IS_TIM5_OUTPUT_STATE(STATE) (((STATE) == TIM5_OutputState_Disable) || \ 00195 ((STATE) == TIM5_OutputState_Enable)) 00196 00197 /** 00198 * @} 00199 */ 00200 00201 /** @defgroup TIM5_Break_State 00202 * @{ 00203 */ 00204 typedef enum 00205 { 00206 TIM5_BreakState_Disable = ((uint8_t)0x00), /*!< Break State disabled (break option disabled) */ 00207 TIM5_BreakState_Enable = ((uint8_t)0x10) /*!< Break State enabled (break option enabled) */ 00208 }TIM5_BreakState_TypeDef; 00209 00210 #define IS_TIM5_BREAK_STATE(STATE) (((STATE) == TIM5_BreakState_Enable) || \ 00211 ((STATE) == TIM5_BreakState_Disable)) 00212 /** 00213 * @} 00214 */ 00215 00216 /** @defgroup TIM5_Break_Polarity 00217 * @{ 00218 */ 00219 typedef enum 00220 { 00221 TIM5_BreakPolarity_High = ((uint8_t)0x20), /*!< if Break, channel polarity = High */ 00222 TIM5_BreakPolarity_Low = ((uint8_t)0x00) /*!< if Break, channel polarity = Low */ 00223 }TIM5_BreakPolarity_TypeDef; 00224 00225 #define IS_TIM5_BREAK_POLARITY(POLARITY) \ 00226 (((POLARITY) == TIM5_BreakPolarity_Low) || \ 00227 ((POLARITY) == TIM5_BreakPolarity_High)) 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup TIM5_Automatic_Output 00233 * @{ 00234 */ 00235 typedef enum 00236 { 00237 TIM5_AutomaticOutput_Enable = ((uint8_t)0x40), /*!< Automatic Output option enabled */ 00238 TIM5_AutomaticOutput_Disable = ((uint8_t)0x00) /*!< Automatic Output option disabled */ 00239 }TIM5_AutomaticOutput_TypeDef; 00240 00241 #define IS_TIM5_AUTOMATIC_OUTPUT_STATE(STATE) \ 00242 (((STATE) == TIM5_AutomaticOutput_Enable) || \ 00243 ((STATE) == TIM5_AutomaticOutput_Disable)) 00244 /** 00245 * @} 00246 */ 00247 00248 /** @defgroup TIM5_Lock_Level 00249 * @{ 00250 */ 00251 typedef enum 00252 { 00253 TIM5_LockLevel_Off = ((uint8_t)0x00), /*!< Lock option disabled */ 00254 TIM5_LockLevel_1 = ((uint8_t)0x01), /*!< Select Lock Level 1 */ 00255 TIM5_LockLevel_2 = ((uint8_t)0x02), /*!< Select Lock Level 2 */ 00256 TIM5_LockLevel_3 = ((uint8_t)0x03) /*!< Select Lock Level 3 */ 00257 }TIM5_LockLevel_TypeDef; 00258 00259 #define IS_TIM5_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM5_LockLevel_Off) || \ 00260 ((LEVEL) == TIM5_LockLevel_1) || \ 00261 ((LEVEL) == TIM5_LockLevel_2) || \ 00262 ((LEVEL) == TIM5_LockLevel_3)) 00263 /** 00264 * @} 00265 */ 00266 00267 /** @defgroup TIM5_OSSI_State 00268 * @{ 00269 */ 00270 typedef enum 00271 { 00272 TIM5_OSSIState_Enable = ((uint8_t)0x04), /*!< Off-State Selection for Idle mode enabled */ 00273 TIM5_OSSIState_Disable = ((uint8_t)0x00) /*!< Off-State Selection for Idle mode disabled */ 00274 }TIM5_OSSIState_TypeDef; 00275 00276 #define IS_TIM5_OSSI_STATE(STATE) \ 00277 (((STATE) == TIM5_OSSIState_Enable) || \ 00278 ((STATE) == TIM5_OSSIState_Disable)) 00279 /** 00280 * @} 00281 */ 00282 00283 /** @defgroup TIM5_Output_Compare_Idle_state 00284 * @{ 00285 */ 00286 typedef enum 00287 { 00288 TIM5_OCIdleState_Reset = ((uint8_t)0x00), /*!< Output Compare Idle state = Reset */ 00289 TIM5_OCIdleState_Set = ((uint8_t)0x01) /*!< Output Compare Idle state = Set */ 00290 }TIM5_OCIdleState_TypeDef; 00291 00292 #define IS_TIM5_OCIDLE_STATE(STATE) \ 00293 (((STATE) == TIM5_OCIdleState_Set) || \ 00294 ((STATE) == TIM5_OCIdleState_Reset)) 00295 /** 00296 * @} 00297 */ 00298 00299 /** @defgroup TIM5_Input_Capture_Polarity 00300 * @{ 00301 */ 00302 typedef enum 00303 { 00304 TIM5_ICPolarity_Rising = ((uint8_t)0x00), /*!< Input Capture on Rising Edge*/ 00305 TIM5_ICPolarity_Falling = ((uint8_t)0x01) /*!< Input Capture on Falling Edge*/ 00306 }TIM5_ICPolarity_TypeDef; 00307 00308 #define IS_TIM5_IC_POLARITY(POLARITY) \ 00309 (((POLARITY) == TIM5_ICPolarity_Rising) || \ 00310 ((POLARITY) == TIM5_ICPolarity_Falling)) 00311 /** 00312 * @} 00313 */ 00314 00315 /** @defgroup TIM5_Input_Capture_Selection 00316 * @{ 00317 */ 00318 typedef enum 00319 { 00320 TIM5_ICSelection_DirectTI = ((uint8_t)0x01), /*!< Input Capture mapped on the direct input*/ 00321 TIM5_ICSelection_IndirectTI = ((uint8_t)0x02), /*!< Input Capture mapped on the indirect input*/ 00322 TIM5_ICSelection_TRGI = ((uint8_t)0x03) /*!< Input Capture mapped on the Trigger Input*/ 00323 }TIM5_ICSelection_TypeDef; 00324 00325 #define IS_TIM5_IC_SELECTION(SELECTION) \ 00326 (((SELECTION) == TIM5_ICSelection_DirectTI) || \ 00327 ((SELECTION) == TIM5_ICSelection_IndirectTI) || \ 00328 ((SELECTION) == TIM5_ICSelection_TRGI)) 00329 /** 00330 * @} 00331 */ 00332 00333 /** @defgroup TIM5_Input_Capture_Prescaler 00334 * @{ 00335 */ 00336 typedef enum 00337 { 00338 TIM5_ICPSC_DIV1 = ((uint8_t)0x00), /*!< Input Capture Prescaler = 1 (one capture every 1 event) */ 00339 TIM5_ICPSC_DIV2 = ((uint8_t)0x04), /*!< Input Capture Prescaler = 2 (one capture every 2 events) */ 00340 TIM5_ICPSC_DIV4 = ((uint8_t)0x08), /*!< Input Capture Prescaler = 4 (one capture every 4 events) */ 00341 TIM5_ICPSC_DIV8 = ((uint8_t)0x0C) /*!< Input Capture Prescaler = 8 (one capture every 8 events) */ 00342 }TIM5_ICPSC_TypeDef; 00343 00344 #define IS_TIM5_IC_PRESCALER(PRESCALER) \ 00345 (((PRESCALER) == TIM5_ICPSC_DIV1) || \ 00346 ((PRESCALER) == TIM5_ICPSC_DIV2) || \ 00347 ((PRESCALER) == TIM5_ICPSC_DIV4) || \ 00348 ((PRESCALER) == TIM5_ICPSC_DIV8)) 00349 /** 00350 * @} 00351 */ 00352 00353 /** @defgroup TIM5_Interrupts 00354 * @{ 00355 */ 00356 typedef enum 00357 { 00358 TIM5_IT_Update = ((uint8_t)0x01), /*!< Update Interrupt*/ 00359 TIM5_IT_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Interrupt*/ 00360 TIM5_IT_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Interrupt*/ 00361 TIM5_IT_Trigger = ((uint8_t)0x40), /*!< Trigger Interrupt*/ 00362 TIM5_IT_Break = ((uint8_t)0x80) /*!< Break Interrupt*/ 00363 }TIM5_IT_TypeDef; 00364 00365 #define IS_TIM5_IT(IT) \ 00366 ((IT) != 0x00) 00367 00368 #define IS_TIM5_GET_IT(IT) \ 00369 (((IT) == TIM5_IT_Update) || \ 00370 ((IT) == TIM5_IT_CC1) || \ 00371 ((IT) == TIM5_IT_CC2) || \ 00372 ((IT) == TIM5_IT_Trigger) || \ 00373 ((IT) == TIM5_IT_Break)) 00374 /** 00375 * @} 00376 */ 00377 00378 /** @defgroup TIM5_External_Trigger_Prescaler 00379 * @{ 00380 */ 00381 typedef enum 00382 { 00383 TIM5_ExtTRGPSC_OFF = ((uint8_t)0x00), /*!< No External Trigger prescaler */ 00384 TIM5_ExtTRGPSC_DIV2 = ((uint8_t)0x10), /*!< External Trigger prescaler = 2 (ETRP frequency divided by 2) */ 00385 TIM5_ExtTRGPSC_DIV4 = ((uint8_t)0x20), /*!< External Trigger prescaler = 4 (ETRP frequency divided by 4) */ 00386 TIM5_ExtTRGPSC_DIV8 = ((uint8_t)0x30) /*!< External Trigger prescaler = 8 (ETRP frequency divided by 8) */ 00387 }TIM5_ExtTRGPSC_TypeDef; 00388 00389 #define IS_TIM5_EXT_PRESCALER(PRESCALER) \ 00390 (((PRESCALER) == TIM5_ExtTRGPSC_OFF) || \ 00391 ((PRESCALER) == TIM5_ExtTRGPSC_DIV2) || \ 00392 ((PRESCALER) == TIM5_ExtTRGPSC_DIV4) || \ 00393 ((PRESCALER) == TIM5_ExtTRGPSC_DIV8)) 00394 /** 00395 * @} 00396 */ 00397 00398 /** @defgroup TIM5_Internal_Trigger_Selection 00399 * @{ 00400 */ 00401 typedef enum 00402 { 00403 TIM5_TRGSelection_TIM4 = ((uint8_t)0x00), /*!< TRIG Input source = TIM TRIG Output */ 00404 TIM5_TRGSelection_TIM1 = ((uint8_t)0x10), /*!< TRIG Input source = TIM TRIG Output */ 00405 TIM5_TRGSelection_TIM3 = ((uint8_t)0x20), /*!< TRIG Input source = TIM TRIG Output */ 00406 TIM5_TRGSelection_TIM2 = ((uint8_t)0x30), /*!< TRIG Input source = TIM TRIG Output */ 00407 TIM5_TRGSelection_TI1F_ED = ((uint8_t)0x40), /*!< TRIG Input source = TI1F_ED (TI1 Edge Detector) */ 00408 TIM5_TRGSelection_TI1FP1 = ((uint8_t)0x50), /*!< TRIG Input source = TI1FP1 (Filtred Timer Input 1) */ 00409 TIM5_TRGSelection_TI2FP2 = ((uint8_t)0x60), /*!< TRIG Input source = TI2FP2 (Filtred Timer Input 2) */ 00410 TIM5_TRGSelection_ETRF = ((uint8_t)0x70) /*!< TRIG Input source = ETRF (External Trigger Input ) */ 00411 }TIM5_TRGSelection_TypeDef; 00412 00413 #define IS_TIM5_TRIGGER_SELECTION(SELECTION) \ 00414 (((SELECTION) == TIM5_TRGSelection_TIM4) || \ 00415 ((SELECTION) == TIM5_TRGSelection_TIM1) || \ 00416 ((SELECTION) == TIM5_TRGSelection_TIM3) || \ 00417 ((SELECTION) == TIM5_TRGSelection_TIM2) || \ 00418 ((SELECTION) == TIM5_TRGSelection_TI1F_ED) || \ 00419 ((SELECTION) == TIM5_TRGSelection_TI1FP1) || \ 00420 ((SELECTION) == TIM5_TRGSelection_TI2FP2) || \ 00421 ((SELECTION) == TIM5_TRGSelection_ETRF)) 00422 00423 00424 #define IS_TIM5_TIX_TRIGGER_SELECTION(SELECTION) \ 00425 (((SELECTION) == TIM5_TRGSelection_TI1F_ED) || \ 00426 ((SELECTION) == TIM5_TRGSelection_TI1FP1) || \ 00427 ((SELECTION) == TIM5_TRGSelection_TI2FP2)) 00428 /** 00429 * @} 00430 */ 00431 00432 /** @defgroup TIM5_TI_External_Clock_Source 00433 * @{ 00434 */ 00435 typedef enum 00436 { 00437 TIM5_TIxExternalCLK1Source_TI1ED = ((uint8_t)0x40), /*!< External Clock mode 1 source = TI1ED */ 00438 TIM5_TIxExternalCLK1Source_TI1 = ((uint8_t)0x50), /*!< External Clock mode 1 source = TI1 */ 00439 TIM5_TIxExternalCLK1Source_TI2 = ((uint8_t)0x60) /*!< External Clock mode 1 source = TI2 */ 00440 }TIM5_TIxExternalCLK1Source_TypeDef; 00441 00442 #define IS_TIM5_TIXCLK_SOURCE(SOURCE) \ 00443 (((SOURCE) == TIM5_TIxExternalCLK1Source_TI1ED) || \ 00444 ((SOURCE) == TIM5_TIxExternalCLK1Source_TI2) || \ 00445 ((SOURCE) == TIM5_TIxExternalCLK1Source_TI1)) 00446 00447 /** 00448 * @} 00449 */ 00450 00451 /** @defgroup TIM5_External_Trigger_Polarity 00452 * @{ 00453 */ 00454 typedef enum 00455 { 00456 TIM5_ExtTRGPolarity_Inverted = ((uint8_t)0x80), /*!< External Trigger Polarity = inverted */ 00457 TIM5_ExtTRGPolarity_NonInverted = ((uint8_t)0x00) /*!< External Trigger Polarity = non inverted */ 00458 }TIM5_ExtTRGPolarity_TypeDef; 00459 00460 #define IS_TIM5_EXT_POLARITY(POLARITY) \ 00461 (((POLARITY) == TIM5_ExtTRGPolarity_Inverted) || \ 00462 ((POLARITY) == TIM5_ExtTRGPolarity_NonInverted)) 00463 /** 00464 * @} 00465 */ 00466 00467 /** @defgroup TIM5_Prescaler_Reload_Mode 00468 * @{ 00469 */ 00470 typedef enum 00471 { 00472 TIM5_PSCReloadMode_Update = ((uint8_t)0x00), /*!< Prescaler value is reloaded at every update*/ 00473 TIM5_PSCReloadMode_Immediate = ((uint8_t)0x01) /*!< Prescaler value is reloaded immediatly*/ 00474 }TIM5_PSCReloadMode_TypeDef; 00475 00476 #define IS_TIM5_PRESCALER_RELOAD(RELOAD) \ 00477 (((RELOAD) == TIM5_PSCReloadMode_Update) || \ 00478 ((RELOAD) == TIM5_PSCReloadMode_Immediate)) 00479 /** 00480 * @} 00481 */ 00482 00483 /** @defgroup TIM5_Encoder_Mode 00484 * @{ 00485 */ 00486 typedef enum 00487 { 00488 TIM5_EncoderMode_TI1 = ((uint8_t)0x01), /*!< Encoder mode 1*/ 00489 TIM5_EncoderMode_TI2 = ((uint8_t)0x02), /*!< Encoder mode 2*/ 00490 TIM5_EncoderMode_TI12 = ((uint8_t)0x03) /*!< Encoder mode 3*/ 00491 }TIM5_EncoderMode_TypeDef; 00492 00493 #define IS_TIM5_ENCODER_MODE(MODE) \ 00494 (((MODE) == TIM5_EncoderMode_TI1) || \ 00495 ((MODE) == TIM5_EncoderMode_TI2) || \ 00496 ((MODE) == TIM5_EncoderMode_TI12)) 00497 /** 00498 * @} 00499 */ 00500 00501 /** @defgroup TIM5_Event_Source 00502 * @{ 00503 */ 00504 typedef enum 00505 { 00506 TIM5_EventSource_Update = ((uint8_t)0x01), /*!< Update Event*/ 00507 TIM5_EventSource_CC1 = ((uint8_t)0x02), /*!< Capture Compare Channel1 Event*/ 00508 TIM5_EventSource_CC2 = ((uint8_t)0x04), /*!< Capture Compare Channel2 Event*/ 00509 TIM5_EventSource_Trigger = ((uint8_t)0x40), /*!< Trigger Event*/ 00510 TIM5_EventSource_Break = ((uint8_t)0x80) /*!< Break Event*/ 00511 }TIM5_EventSource_TypeDef; 00512 00513 #define IS_TIM5_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint8_t)0x18) == 0x00) && \ 00514 ((SOURCE) != 0x00)) 00515 /** 00516 * @} 00517 */ 00518 00519 /** @defgroup TIM5_Update_Source 00520 * @{ 00521 */ 00522 typedef enum 00523 { 00524 TIM5_UpdateSource_Global = ((uint8_t)0x00), /*!< Global Update request source */ 00525 TIM5_UpdateSource_Regular = ((uint8_t)0x01) /*!< Regular Update request source */ 00526 }TIM5_UpdateSource_TypeDef; 00527 00528 #define IS_TIM5_UPDATE_SOURCE(SOURCE) \ 00529 (((SOURCE) == TIM5_UpdateSource_Global) || \ 00530 ((SOURCE) == TIM5_UpdateSource_Regular)) 00531 00532 /** 00533 * @} 00534 */ 00535 00536 /** @defgroup TIM5_Trigger_Output_Source 00537 * @{ 00538 */ 00539 typedef enum 00540 { 00541 TIM5_TRGOSource_Reset = ((uint8_t)0x00), /*!< Trigger Output source = Reset*/ 00542 TIM5_TRGOSource_Enable = ((uint8_t)0x10), /*!< Trigger Output source = TIM5 is enabled*/ 00543 TIM5_TRGOSource_Update = ((uint8_t)0x20), /*!< Trigger Output source = Update event*/ 00544 TIM5_TRGOSource_OC1 = ((uint8_t)0x30), /*!< Trigger Output source = output compare channel1 */ 00545 TIM5_TRGOSource_OC1REF = ((uint8_t)0x40), /*!< Trigger Output source = output compare channel 1 reference */ 00546 TIM5_TRGOSource_OC2REF = ((uint8_t)0x50) /*!< Trigger Output source = output compare channel 2 reference */ 00547 }TIM5_TRGOSource_TypeDef; 00548 00549 #define IS_TIM5_TRGO_SOURCE(SOURCE) \ 00550 (((SOURCE) == TIM5_TRGOSource_Reset) || \ 00551 ((SOURCE) == TIM5_TRGOSource_Enable) || \ 00552 ((SOURCE) == TIM5_TRGOSource_Update) || \ 00553 ((SOURCE) == TIM5_TRGOSource_OC1) || \ 00554 ((SOURCE) == TIM5_TRGOSource_OC1REF) || \ 00555 ((SOURCE) == TIM5_TRGOSource_OC2REF)) 00556 /** 00557 * @} 00558 */ 00559 00560 /** @defgroup TIM5_Slave_Mode 00561 * @{ 00562 */ 00563 typedef enum 00564 { 00565 TIM5_SlaveMode_Reset = ((uint8_t)0x04), /*!< Slave Mode Selection = Reset*/ 00566 TIM5_SlaveMode_Gated = ((uint8_t)0x05), /*!< Slave Mode Selection = Gated*/ 00567 TIM5_SlaveMode_Trigger = ((uint8_t)0x06), /*!< Slave Mode Selection = Trigger*/ 00568 TIM5_SlaveMode_External1 = ((uint8_t)0x07) /*!< Slave Mode Selection = External 1*/ 00569 }TIM5_SlaveMode_TypeDef; 00570 00571 #define IS_TIM5_SLAVE_MODE(MODE) \ 00572 (((MODE) == TIM5_SlaveMode_Reset) || \ 00573 ((MODE) == TIM5_SlaveMode_Gated) || \ 00574 ((MODE) == TIM5_SlaveMode_Trigger) || \ 00575 ((MODE) == TIM5_SlaveMode_External1)) 00576 /** 00577 * @} 00578 */ 00579 00580 /** @defgroup TIM5_Flags 00581 * @{ 00582 */ 00583 typedef enum 00584 { 00585 TIM5_FLAG_Update = ((uint16_t)0x0001), /*!< Update Flag */ 00586 TIM5_FLAG_CC1 = ((uint16_t)0x0002), /*!< Capture compare 1 Flag */ 00587 TIM5_FLAG_CC2 = ((uint16_t)0x0004), /*!< Capture compare 2 Flag */ 00588 TIM5_FLAG_Trigger = ((uint16_t)0x0040), /*!< Trigger Flag */ 00589 TIM5_FLAG_Break = ((uint16_t)0x0080), /*!< Break Flag */ 00590 TIM5_FLAG_CC1OF = ((uint16_t)0x0200), /*!< Capture compare 1 over capture Flag */ 00591 TIM5_FLAG_CC2OF = ((uint16_t)0x0400) /*!< Capture compare 2 over capture Flag */ 00592 }TIM5_FLAG_TypeDef; 00593 00594 #define IS_TIM5_GET_FLAG(FLAG) \ 00595 (((FLAG) == TIM5_FLAG_Update) || \ 00596 ((FLAG) == TIM5_FLAG_CC1) || \ 00597 ((FLAG) == TIM5_FLAG_CC2) || \ 00598 ((FLAG) == TIM5_FLAG_Trigger) || \ 00599 ((FLAG) == TIM5_FLAG_Break) || \ 00600 ((FLAG) == TIM5_FLAG_CC1OF) || \ 00601 ((FLAG) == TIM5_FLAG_CC2OF)) 00602 00603 #define IS_TIM5_CLEAR_FLAG(FLAG) \ 00604 ((((FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000)) 00605 /** 00606 * @} 00607 */ 00608 00609 /** @defgroup TIM5_DMA_Source_Requests 00610 * @{ 00611 */ 00612 typedef enum 00613 { 00614 TIM5_DMASource_Update = ((uint8_t)0x01), /*!< TIM5 DMA Update Request*/ 00615 TIM5_DMASource_CC1 = ((uint8_t)0x02), /*!< TIM5 DMA CC1 Request*/ 00616 TIM5_DMASource_CC2 = ((uint8_t)0x04) /*!< TIM5 DMA CC2 Request*/ 00617 }TIM5_DMASource_TypeDef; 00618 00619 #define IS_TIM5_DMA_SOURCE(SOURCE) \ 00620 (((SOURCE) == TIM5_DMASource_Update) || \ 00621 ((SOURCE) == TIM5_DMASource_CC1) || \ 00622 ((SOURCE) == TIM5_DMASource_CC2)) 00623 /** 00624 * @} 00625 */ 00626 00627 /** 00628 * @} 00629 */ 00630 00631 /* Exported constants --------------------------------------------------------*/ 00632 /* Exported macros -----------------------------------------------------------*/ 00633 00634 /** @defgroup TIM5_Exported_Macros 00635 * @{ 00636 */ 00637 00638 /** 00639 * @brief Macro TIM5 Input Capture Filter Value 00640 */ 00641 #define IS_TIM5_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F) 00642 00643 /** 00644 * @brief Macro TIM5 External Trigger Filter 00645 */ 00646 #define IS_TIM5_EXT_FILTER(EXTFILTER) \ 00647 ((EXTFILTER) <= 0x0F) 00648 00649 /** 00650 * @} 00651 */ 00652 00653 /* Exported functions ------------------------------------------------------- */ 00654 00655 /* TimeBase management ********************************************************/ 00656 void TIM5_DeInit(void); 00657 void TIM5_TimeBaseInit(TIM5_Prescaler_TypeDef TIM5_Prescaler, 00658 TIM5_CounterMode_TypeDef TIM5_CounterMode, uint16_t TIM5_Period); 00659 void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler, 00660 TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode); 00661 void TIM5_CounterModeConfig(TIM5_CounterMode_TypeDef TIM5_CounterMode); 00662 void TIM5_SetCounter(uint16_t Counter); 00663 void TIM5_SetAutoreload(uint16_t Autoreload); 00664 uint16_t TIM5_GetCounter(void); 00665 TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void); 00666 void TIM5_UpdateDisableConfig(FunctionalState NewState); 00667 void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource); 00668 void TIM5_ARRPreloadConfig(FunctionalState NewState); 00669 void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode); 00670 void TIM5_Cmd(FunctionalState NewState); 00671 00672 /* Output Compare management **************************************************/ 00673 void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode, 00674 TIM5_OutputState_TypeDef TIM5_OutputState, 00675 uint16_t TIM5_Pulse, 00676 TIM5_OCPolarity_TypeDef TIM5_OCPolarity, 00677 TIM5_OCIdleState_TypeDef TIM5_OCIdleState); 00678 void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode, 00679 TIM5_OutputState_TypeDef TIM5_OutputState, 00680 uint16_t TIM5_Pulse, 00681 TIM5_OCPolarity_TypeDef TIM5_OCPolarity, 00682 TIM5_OCIdleState_TypeDef TIM5_OCIdleState); 00683 void TIM5_BKRConfig(TIM5_OSSIState_TypeDef TIM5_OSSIState, 00684 TIM5_LockLevel_TypeDef TIM5_LockLevel, 00685 TIM5_BreakState_TypeDef TIM5_BreakState, 00686 TIM5_BreakPolarity_TypeDef TIM5_BreakPolarity, 00687 TIM5_AutomaticOutput_TypeDef TIM5_AutomaticOutput); 00688 void TIM5_CtrlPWMOutputs(FunctionalState NewState); 00689 void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode); 00690 void TIM5_SetCompare1(uint16_t Compare); 00691 void TIM5_SetCompare2(uint16_t Compare); 00692 void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction); 00693 void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction); 00694 void TIM5_OC1PreloadConfig(FunctionalState NewState); 00695 void TIM5_OC2PreloadConfig(FunctionalState NewState); 00696 void TIM5_OC1FastConfig(FunctionalState NewState); 00697 void TIM5_OC2FastConfig(FunctionalState NewState); 00698 void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity); 00699 void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity); 00700 void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState); 00701 00702 /* Input Capture management ***************************************************/ 00703 void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel, 00704 TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 00705 TIM5_ICSelection_TypeDef TIM5_ICSelection, 00706 TIM5_ICPSC_TypeDef TIM5_ICPrescaler, 00707 uint8_t TIM5_ICFilter); 00708 void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel, 00709 TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 00710 TIM5_ICSelection_TypeDef TIM5_ICSelection, 00711 TIM5_ICPSC_TypeDef TIM5_ICPrescaler, 00712 uint8_t TIM5_ICFilter); 00713 uint16_t TIM5_GetCapture1(void); 00714 uint16_t TIM5_GetCapture2(void); 00715 void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler); 00716 void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler); 00717 00718 /* Interrupts, DMA and flags management ***************************************/ 00719 void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState); 00720 void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource); 00721 FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG); 00722 void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG); 00723 ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT); 00724 void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT); 00725 void TIM5_DMACmd(TIM5_DMASource_TypeDef TIM5_DMASource, FunctionalState NewState); 00726 void TIM5_SelectCCDMA(FunctionalState NewState); 00727 00728 /* Clocks management **********************************************************/ 00729 void TIM5_InternalClockConfig(void); 00730 void TIM5_TIxExternalClockConfig(TIM5_TIxExternalCLK1Source_TypeDef TIM5_TIxExternalCLKSource, 00731 TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 00732 uint8_t ICFilter); 00733 void TIM5_ETRClockMode1Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler, 00734 TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity, 00735 uint8_t ExtTRGFilter); 00736 void TIM5_ETRClockMode2Config(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler, 00737 TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity, 00738 uint8_t ExtTRGFilter); 00739 00740 /* Synchronization management *************************************************/ 00741 void TIM5_SelectInputTrigger(TIM5_TRGSelection_TypeDef TIM5_InputTriggerSource); 00742 void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource); 00743 void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode); 00744 void TIM5_SelectMasterSlaveMode(FunctionalState NewState); 00745 void TIM5_ETRConfig(TIM5_ExtTRGPSC_TypeDef TIM5_ExtTRGPrescaler, 00746 TIM5_ExtTRGPolarity_TypeDef TIM5_ExtTRGPolarity, 00747 uint8_t ExtTRGFilter); 00748 00749 /* Specific interface management **********************************************/ 00750 void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode, 00751 TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, 00752 TIM5_ICPolarity_TypeDef TIM5_IC2Polarity); 00753 void TIM5_SelectHallSensor(FunctionalState NewState); 00754 00755 #endif /* __STM8L15x_TIM5_H */ 00756 00757 /** 00758 * @} 00759 */ 00760 00761 /** 00762 * @} 00763 */ 00764 00765 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/