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STM8L15x Standard Peripherals Drivers
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stm8l15x_tim1.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_tim1.h 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file contains all the functions prototypes for the TIM1 firmware 00008 * library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00013 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00014 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00015 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00016 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00017 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00018 * 00019 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00020 ****************************************************************************** 00021 */ 00022 00023 /* Define to prevent recursive inclusion -------------------------------------*/ 00024 #ifndef __STM8L15x_TIM1_H 00025 #define __STM8L15x_TIM1_H 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm8l15x.h" 00029 00030 /** @addtogroup STM8L15x_StdPeriph_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup TIM1 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup TIM1_Exported_Types 00040 * @{ 00041 */ 00042 00043 /** @defgroup TIM1_Output_Compare_Mode 00044 * @{ 00045 */ 00046 typedef enum 00047 { 00048 TIM1_OCMode_Timing = ((uint8_t)0x00), 00049 TIM1_OCMode_Active = ((uint8_t)0x10), 00050 TIM1_OCMode_Inactive = ((uint8_t)0x20), 00051 TIM1_OCMode_Toggle = ((uint8_t)0x30), 00052 TIM1_OCMode_PWM1 = ((uint8_t)0x60), 00053 TIM1_OCMode_PWM2 = ((uint8_t)0x70) 00054 }TIM1_OCMode_TypeDef; 00055 00056 /** 00057 * @} 00058 */ 00059 00060 /** @defgroup TIM1_One_Pulse_Mode 00061 * @{ 00062 */ 00063 typedef enum 00064 { 00065 TIM1_OPMode_Single = ((uint8_t)0x01), 00066 TIM1_OPMode_Repetitive = ((uint8_t)0x00) 00067 }TIM1_OPMode_TypeDef; 00068 00069 /** 00070 * @} 00071 */ 00072 00073 /** @defgroup TIM1_Channels 00074 * @{ 00075 */ 00076 typedef enum 00077 { 00078 TIM1_Channel_1 = ((uint8_t)0x00), 00079 TIM1_Channel_2 = ((uint8_t)0x01), 00080 TIM1_Channel_3 = ((uint8_t)0x02), 00081 TIM1_Channel_4 = ((uint8_t)0x03) 00082 }TIM1_Channel_TypeDef; 00083 00084 /** 00085 * @} 00086 */ 00087 00088 /** @defgroup TIM1_Counter_Mode 00089 * @{ 00090 */ 00091 typedef enum 00092 { 00093 TIM1_CounterMode_Up = ((uint8_t)0x00), 00094 TIM1_CounterMode_Down = ((uint8_t)0x10), 00095 TIM1_CounterMode_CenterAligned1 = ((uint8_t)0x20), 00096 TIM1_CounterMode_CenterAligned2 = ((uint8_t)0x40), 00097 TIM1_CounterMode_CenterAligned3 = ((uint8_t)0x60) 00098 }TIM1_CounterMode_TypeDef; 00099 00100 /** 00101 * @} 00102 */ 00103 00104 /** @defgroup TIM1_Output_Compare_Polarity 00105 * @{ 00106 */ 00107 typedef enum 00108 { 00109 TIM1_OCPolarity_High = ((uint8_t)0x00), 00110 TIM1_OCPolarity_Low = ((uint8_t)0x22) 00111 }TIM1_OCPolarity_TypeDef; 00112 00113 /** 00114 * @} 00115 */ 00116 00117 /** @defgroup TIM1_Output_Compare_N_Polarity 00118 * @{ 00119 */ 00120 typedef enum 00121 { 00122 TIM1_OCNPolarity_High = ((uint8_t)0x00), 00123 TIM1_OCNPolarity_Low = ((uint8_t)0x88) 00124 }TIM1_OCNPolarity_TypeDef; 00125 00126 /** 00127 * @} 00128 */ 00129 00130 /** @defgroup TIM1_Output_State 00131 * @{ 00132 */ 00133 typedef enum 00134 { 00135 TIM1_OutputState_Disable = ((uint8_t)0x00), 00136 TIM1_OutputState_Enable = ((uint8_t)0x11) 00137 }TIM1_OutputState_TypeDef; 00138 00139 /** 00140 * @} 00141 */ 00142 00143 /** @defgroup TIM1_Output_N_State 00144 * @{ 00145 */ 00146 typedef enum 00147 { 00148 TIM1_OutputNState_Disable = ((uint8_t)0x00), 00149 TIM1_OutputNState_Enable = ((uint8_t)0x44) 00150 } TIM1_OutputNState_TypeDef; 00151 00152 /** 00153 * @} 00154 */ 00155 00156 /** @defgroup TIM1_Break_State 00157 * @{ 00158 */ 00159 typedef enum 00160 { 00161 TIM1_BreakState_Enable = ((uint8_t)0x10), 00162 TIM1_BreakState_Disable = ((uint8_t)0x00) 00163 }TIM1_BreakState_TypeDef; 00164 00165 /** 00166 * @} 00167 */ 00168 00169 /** @defgroup TIM1_Break_Polarity 00170 * @{ 00171 */ 00172 typedef enum 00173 { 00174 TIM1_BreakPolarity_Low = ((uint8_t)0x00), 00175 TIM1_BreakPolarity_High = ((uint8_t)0x20) 00176 }TIM1_BreakPolarity_TypeDef; 00177 00178 /** 00179 * @} 00180 */ 00181 00182 /** @defgroup TIM1_Automatic_Output 00183 * @{ 00184 */ 00185 typedef enum 00186 { 00187 TIM1_AutomaticOutput_Enable = ((uint8_t)0x40), 00188 TIM1_AutomaticOutput_Disable = ((uint8_t)0x00) 00189 }TIM1_AutomaticOutput_TypeDef; 00190 00191 /** 00192 * @} 00193 */ 00194 00195 /** @defgroup TIM1_Lock_Level 00196 * @{ 00197 */ 00198 typedef enum 00199 { 00200 TIM1_LockLevel_Off = ((uint8_t)0x00), 00201 TIM1_LockLevel_1 = ((uint8_t)0x01), 00202 TIM1_LockLevel_2 = ((uint8_t)0x02), 00203 TIM1_LockLevel_3 = ((uint8_t)0x03) 00204 }TIM1_LockLevel_TypeDef; 00205 00206 /** 00207 * @} 00208 */ 00209 00210 /** @defgroup TIM1_OSSI_State 00211 * @{ 00212 */ 00213 typedef enum 00214 { 00215 TIM1_OSSIState_Enable = ((uint8_t)0x04), 00216 TIM1_OSSIState_Disable = ((uint8_t)0x00) 00217 }TIM1_OSSIState_TypeDef; 00218 00219 /** 00220 * @} 00221 */ 00222 00223 /** @defgroup TIM1_Output_Compare_Idle_state 00224 * @{ 00225 */ 00226 typedef enum 00227 { 00228 TIM1_OCIdleState_Set = ((uint8_t)0x55), 00229 TIM1_OCIdleState_Reset = ((uint8_t)0x00) 00230 }TIM1_OCIdleState_TypeDef; 00231 00232 /** 00233 * @} 00234 */ 00235 00236 /** @defgroup TIM1_Output_Compare_N_Idle_state 00237 * @{ 00238 */ 00239 typedef enum 00240 { 00241 TIM1_OCNIdleState_Set = ((uint8_t)0x2A), 00242 TIM1_OCNIdleState_Reset = ((uint8_t)0x00) 00243 }TIM1_OCNIdleState_TypeDef; 00244 00245 /** 00246 * @} 00247 */ 00248 00249 /** @defgroup TIM1_Input_Capture_Polarity 00250 * @{ 00251 */ 00252 typedef enum 00253 { 00254 TIM1_ICPolarity_Rising = ((uint8_t)0x00), 00255 TIM1_ICPolarity_Falling = ((uint8_t)0x01) 00256 }TIM1_ICPolarity_TypeDef; 00257 00258 /** 00259 * @} 00260 */ 00261 00262 /** @defgroup TIM1_Input_Capture_Selection 00263 * @{ 00264 */ 00265 typedef enum 00266 { 00267 TIM1_ICSelection_DirectTI = ((uint8_t)0x01), 00268 TIM1_ICSelection_IndirectTI = ((uint8_t)0x02), 00269 TIM1_ICSelection_TRGI = ((uint8_t)0x03) 00270 }TIM1_ICSelection_TypeDef; 00271 00272 /** 00273 * @} 00274 */ 00275 00276 /** @defgroup TIM1_Input_Capture_Prescaler 00277 * @{ 00278 */ 00279 typedef enum 00280 { 00281 TIM1_ICPSC_DIV1 = ((uint8_t)0x00), 00282 TIM1_ICPSC_DIV2 = ((uint8_t)0x04), 00283 TIM1_ICPSC_DIV4 = ((uint8_t)0x08), 00284 TIM1_ICPSC_DIV8 = ((uint8_t)0x0C) 00285 }TIM1_ICPSC_TypeDef; 00286 00287 /** 00288 * @} 00289 */ 00290 00291 /** @defgroup TIM1_Output_Compare_Reference_Clear 00292 * @{ 00293 */ 00294 typedef enum 00295 { 00296 TIM1_OCReferenceClear_ETRF = ((uint8_t)0x08), 00297 TIM1_OCReferenceClear_OCREFCLR = ((uint8_t)0x00) 00298 } 00299 TIM1_OCReferenceClear_TypeDef; 00300 00301 /** 00302 * @} 00303 */ 00304 00305 /** @defgroup TIM1_Interrupts 00306 * @{ 00307 */ 00308 typedef enum 00309 { 00310 TIM1_IT_Update = ((uint8_t)0x01), 00311 TIM1_IT_CC1 = ((uint8_t)0x02), 00312 TIM1_IT_CC2 = ((uint8_t)0x04), 00313 TIM1_IT_CC3 = ((uint8_t)0x08), 00314 TIM1_IT_CC4 = ((uint8_t)0x10), 00315 TIM1_IT_COM = ((uint8_t)0x20), 00316 TIM1_IT_Trigger = ((uint8_t)0x40), 00317 TIM1_IT_Break = ((uint8_t)0x80) 00318 }TIM1_IT_TypeDef; 00319 00320 /** 00321 * @} 00322 */ 00323 00324 /** @defgroup TIM1_External_Trigger_Prescaler 00325 * @{ 00326 */ 00327 typedef enum 00328 { 00329 TIM1_ExtTRGPSC_OFF = ((uint8_t)0x00), 00330 TIM1_ExtTRGPSC_DIV2 = ((uint8_t)0x10), 00331 TIM1_ExtTRGPSC_DIV4 = ((uint8_t)0x20), 00332 TIM1_ExtTRGPSC_DIV8 = ((uint8_t)0x30) 00333 }TIM1_ExtTRGPSC_TypeDef; 00334 00335 /** 00336 * @} 00337 */ 00338 00339 /** @defgroup TIM1_Internal_Trigger_Selection 00340 * @{ 00341 */ 00342 typedef enum 00343 { 00344 TIM1_TRGSelection_TIM4 = ((uint8_t)0x00), /*!< TRIG Input source = TIM TRIG Output */ 00345 TIM1_TRGSelection_TIM5 = ((uint8_t)0x10), /*!< TRIG Input source = TIM TRIG Output */ 00346 TIM1_TRGSelection_TIM3 = ((uint8_t)0x20), /*!< TRIG Input source = TIM TRIG Output */ 00347 TIM1_TRGSelection_TIM2 = ((uint8_t)0x30), /*!< TRIG Input source = TIM TRIG Output */ 00348 TIM1_TRGSelection_TI1F_ED = ((uint8_t)0x40), 00349 TIM1_TRGSelection_TI1FP1 = ((uint8_t)0x50), 00350 TIM1_TRGSelection_TI2FP2 = ((uint8_t)0x60), 00351 TIM1_TRGSelection_ETRF = ((uint8_t)0x70) 00352 }TIM1_TRGSelection_TypeDef; 00353 00354 /** 00355 * @} 00356 */ 00357 00358 /** @defgroup TIM1_TI_External_Clock_Source 00359 * @{ 00360 */ 00361 typedef enum 00362 { 00363 TIM1_TIxExternalCLK1Source_TI1ED = ((uint8_t)0x40), 00364 TIM1_TIxExternalCLK1Source_TI1 = ((uint8_t)0x50), 00365 TIM1_TIxExternalCLK1Source_TI2 = ((uint8_t)0x60) 00366 }TIM1_TIxExternalCLK1Source_TypeDef; 00367 00368 /** 00369 * @} 00370 */ 00371 00372 /** @defgroup TIM1_External_Trigger_Polarity 00373 * @{ 00374 */ 00375 typedef enum 00376 { 00377 TIM1_ExtTRGPolarity_Inverted = ((uint8_t)0x80), 00378 TIM1_ExtTRGPolarity_NonInverted = ((uint8_t)0x00) 00379 }TIM1_ExtTRGPolarity_TypeDef; 00380 00381 /** 00382 * @} 00383 */ 00384 00385 /** @defgroup TIM1_Prescaler_Reload_Mode 00386 * @{ 00387 */ 00388 typedef enum 00389 { 00390 TIM1_PSCReloadMode_Update = ((uint8_t)0x00), 00391 TIM1_PSCReloadMode_Immediate = ((uint8_t)0x01) 00392 }TIM1_PSCReloadMode_TypeDef; 00393 00394 /** 00395 * @} 00396 */ 00397 00398 /** @defgroup TIM1_Encoder_Mode 00399 * @{ 00400 */ 00401 typedef enum 00402 { 00403 TIM1_EncoderMode_TI1 = ((uint8_t)0x01), 00404 TIM1_EncoderMode_TI2 = ((uint8_t)0x02), 00405 TIM1_EncoderMode_TI12 = ((uint8_t)0x03) 00406 }TIM1_EncoderMode_TypeDef; 00407 00408 /** 00409 * @} 00410 */ 00411 00412 /** @defgroup TIM1_Event_Source 00413 * @{ 00414 */ 00415 typedef enum 00416 { 00417 TIM1_EventSource_Update = ((uint8_t)0x01), 00418 TIM1_EventSource_CC1 = ((uint8_t)0x02), 00419 TIM1_EventSource_CC2 = ((uint8_t)0x04), 00420 TIM1_EventSource_CC3 = ((uint8_t)0x08), 00421 TIM1_EventSource_CC4 = ((uint8_t)0x10), 00422 TIM1_EventSource_COM = ((uint8_t)0x20), 00423 TIM1_EventSource_Trigger = ((uint8_t)0x40), 00424 TIM1_EventSource_Break = ((uint8_t)0x80) 00425 }TIM1_EventSource_TypeDef; 00426 00427 /** 00428 * @} 00429 */ 00430 00431 /** @defgroup TIM1_Update_Source 00432 * @{ 00433 */ 00434 typedef enum 00435 { 00436 TIM1_UpdateSource_Global = ((uint8_t)0x00), 00437 TIM1_UpdateSource_Regular = ((uint8_t)0x01) 00438 }TIM1_UpdateSource_TypeDef; 00439 00440 /** 00441 * @} 00442 */ 00443 00444 /** @defgroup TIM1_Trigger_Output_Source 00445 * @{ 00446 */ 00447 typedef enum 00448 { 00449 TIM1_TRGOSource_Reset = ((uint8_t)0x00), 00450 TIM1_TRGOSource_Enable = ((uint8_t)0x10), 00451 TIM1_TRGOSource_Update = ((uint8_t)0x20), 00452 TIM1_TRGOSource_OC1 = ((uint8_t)0x30), 00453 TIM1_TRGOSource_OC1REF = ((uint8_t)0x40), 00454 TIM1_TRGOSource_OC2REF = ((uint8_t)0x50), 00455 TIM1_TRGOSource_OC3REF = ((uint8_t)0x60), 00456 TIM1_TRGOSource_OC4REF = ((uint8_t)0x70) 00457 }TIM1_TRGOSource_TypeDef; 00458 00459 /** 00460 * @} 00461 */ 00462 00463 /** @defgroup TIM1_Slave_Mode 00464 * @{ 00465 */ 00466 typedef enum 00467 { 00468 TIM1_SlaveMode_Reset = ((uint8_t)0x04), 00469 TIM1_SlaveMode_Gated = ((uint8_t)0x05), 00470 TIM1_SlaveMode_Trigger = ((uint8_t)0x06), 00471 TIM1_SlaveMode_External1 = ((uint8_t)0x07) 00472 }TIM1_SlaveMode_TypeDef; 00473 00474 /** 00475 * @} 00476 */ 00477 00478 /** @defgroup TIM1_Flags 00479 * @{ 00480 */ 00481 typedef enum 00482 { 00483 TIM1_FLAG_Update = ((uint16_t)0x0001), 00484 TIM1_FLAG_CC1 = ((uint16_t)0x0002), 00485 TIM1_FLAG_CC2 = ((uint16_t)0x0004), 00486 TIM1_FLAG_CC3 = ((uint16_t)0x0008), 00487 TIM1_FLAG_CC4 = ((uint16_t)0x0010), 00488 TIM1_FLAG_COM = ((uint16_t)0x0020), 00489 TIM1_FLAG_Trigger = ((uint16_t)0x0040), 00490 TIM1_FLAG_Break = ((uint16_t)0x0080), 00491 TIM1_FLAG_CC1OF = ((uint16_t)0x0200), 00492 TIM1_FLAG_CC2OF = ((uint16_t)0x0400), 00493 TIM1_FLAG_CC3OF = ((uint16_t)0x0800), 00494 TIM1_FLAG_CC4OF = ((uint16_t)0x1000) 00495 }TIM1_FLAG_TypeDef; 00496 00497 /** 00498 * @} 00499 */ 00500 00501 /** @defgroup TIM1_Forced_Action 00502 * @{ 00503 */ 00504 typedef enum 00505 { 00506 TIM1_ForcedAction_Active = ((uint8_t)0x50), 00507 TIM1_ForcedAction_Inactive = ((uint8_t)0x40) 00508 }TIM1_ForcedAction_TypeDef; 00509 00510 /** 00511 * @} 00512 */ 00513 00514 /** @defgroup TIM1_DMA_Source_Requests 00515 * @{ 00516 */ 00517 typedef enum 00518 { 00519 TIM1_DMASource_Update = ((uint8_t)0x01), /*!< TIM1 DMA Update Request*/ 00520 TIM1_DMASource_CC1 = ((uint8_t)0x02), /*!< TIM1 DMA CC1 Request*/ 00521 TIM1_DMASource_CC2 = ((uint8_t)0x04), /*!< TIM1 DMA CC2 Request*/ 00522 TIM1_DMASource_CC3 = ((uint8_t)0x08), /*!< TIM1 DMA CC3 Request*/ 00523 TIM1_DMASource_CC4 = ((uint8_t)0x10), /*!< TIM1 DMA CC4 Request*/ 00524 TIM1_DMASource_COM = ((uint8_t)0x20) /*!< TIM1 DMA COM Req */ 00525 } TIM1_DMASource_TypeDef; 00526 00527 /** 00528 * @} 00529 */ 00530 00531 /** @defgroup TIM1_DMA_Base_Address 00532 * @{ 00533 */ 00534 typedef enum 00535 { 00536 TIM1_DMABase_CR1 = ((uint8_t)0x00), 00537 TIM1_DMABase_CR2 = ((uint8_t)0x01), 00538 TIM1_DMABase_SMCR = ((uint8_t)0x02), 00539 TIM1_DMABase_ETR = ((uint8_t)0x03), 00540 TIM1_DMABase_DER = ((uint8_t)0x04), 00541 TIM1_DMABase_IER = ((uint8_t)0x05), 00542 TIM1_DMABase_SR1 = ((uint8_t)0x06), 00543 TIM1_DMABase_SR2 = ((uint8_t)0x07), 00544 TIM1_DMABase_EGR = ((uint8_t)0x08), 00545 TIM1_DMABase_CCMR1 = ((uint8_t)0x09), 00546 TIM1_DMABase_CCMR2 = ((uint8_t)0x0A), 00547 TIM1_DMABase_CCMR3 = ((uint8_t)0x0B), 00548 TIM1_DMABase_CCMR4 = ((uint8_t)0x0C), 00549 TIM1_DMABase_CCER1 = ((uint8_t)0x0D), 00550 TIM1_DMABase_CCER2 = ((uint8_t)0x0E), 00551 TIM1_DMABase_CNTH = ((uint8_t)0x0F), 00552 TIM1_DMABase_CNTL = ((uint8_t)0x10), 00553 TIM1_DMABase_PSCH = ((uint8_t)0x11), 00554 TIM1_DMABase_PSCL = ((uint8_t)0x12), 00555 TIM1_DMABase_ARRH = ((uint8_t)0x13), 00556 TIM1_DMABase_ARRL = ((uint8_t)0x14), 00557 TIM1_DMABase_RCR = ((uint8_t)0x15), 00558 TIM1_DMABase_CCR1H = ((uint8_t)0x16), 00559 TIM1_DMABase_CCR1L = ((uint8_t)0x17), 00560 TIM1_DMABase_CCR2H = ((uint8_t)0x18), 00561 TIM1_DMABase_CCR2L = ((uint8_t)0x19), 00562 TIM1_DMABase_CCR3H = ((uint8_t)0x1A), 00563 TIM1_DMABase_CCR3L = ((uint8_t)0x1B), 00564 TIM1_DMABase_CCR4H = ((uint8_t)0x1C), 00565 TIM1_DMABase_CCR4L = ((uint8_t)0x1D), 00566 TIM1_DMABase_BKR = ((uint8_t)0x1E), 00567 TIM1_DMABase_DTR = ((uint8_t)0x1F) 00568 00569 } TIM1_DMABase_TypeDef; 00570 00571 /** 00572 * @} 00573 */ 00574 00575 /** @defgroup TIM1_DMA_Burst_Length 00576 * @{ 00577 */ 00578 typedef enum 00579 { 00580 TIM1_DMABurstLength_1Byte = ((uint8_t)0x00), 00581 TIM1_DMABurstLength_2Byte = ((uint8_t)0x01), 00582 TIM1_DMABurstLength_3Byte = ((uint8_t)0x02), 00583 TIM1_DMABurstLength_4Byte = ((uint8_t)0x03), 00584 TIM1_DMABurstLength_5Byte = ((uint8_t)0x04), 00585 TIM1_DMABurstLength_6Byte = ((uint8_t)0x05), 00586 TIM1_DMABurstLength_7Byte = ((uint8_t)0x06), 00587 TIM1_DMABurstLength_8Byte = ((uint8_t)0x07), 00588 TIM1_DMABurstLength_9Byte = ((uint8_t)0x08), 00589 TIM1_DMABurstLength_10Byte = ((uint8_t)0x09), 00590 TIM1_DMABurstLength_11Byte = ((uint8_t)0x0A), 00591 TIM1_DMABurstLength_12Byte = ((uint8_t)0x0B), 00592 TIM1_DMABurstLength_13Byte = ((uint8_t)0x0C), 00593 TIM1_DMABurstLength_14Byte = ((uint8_t)0x0D), 00594 TIM1_DMABurstLength_15Byte = ((uint8_t)0x0E), 00595 TIM1_DMABurstLength_16Byte = ((uint8_t)0x0F), 00596 TIM1_DMABurstLength_17Byte = ((uint8_t)0x10), 00597 TIM1_DMABurstLength_18Byte = ((uint8_t)0x11), 00598 TIM1_DMABurstLength_19Byte = ((uint8_t)0x12), 00599 TIM1_DMABurstLength_20Byte = ((uint8_t)0x13), 00600 TIM1_DMABurstLength_21Byte = ((uint8_t)0x14), 00601 TIM1_DMABurstLength_22Byte = ((uint8_t)0x15), 00602 TIM1_DMABurstLength_23Byte = ((uint8_t)0x16), 00603 TIM1_DMABurstLength_24Byte = ((uint8_t)0x17), 00604 TIM1_DMABurstLength_25Byte = ((uint8_t)0x18), 00605 TIM1_DMABurstLength_26Byte = ((uint8_t)0x19), 00606 TIM1_DMABurstLength_27Byte = ((uint8_t)0x1A), 00607 TIM1_DMABurstLength_28Byte = ((uint8_t)0x1B), 00608 TIM1_DMABurstLength_29Byte = ((uint8_t)0x1C), 00609 TIM1_DMABurstLength_30Byte = ((uint8_t)0x1D), 00610 TIM1_DMABurstLength_31Byte = ((uint8_t)0x1E), 00611 TIM1_DMABurstLength_32Byte = ((uint8_t)0x1F) 00612 00613 } TIM1_DMABurstLength_TypeDef; 00614 00615 /** 00616 * @} 00617 */ 00618 00619 /** 00620 * @} 00621 */ 00622 00623 /* Exported constants --------------------------------------------------------*/ 00624 /* Exported macros -----------------------------------------------------------*/ 00625 /** @defgroup TIM1_Exported_Macros 00626 * @{ 00627 */ 00628 #define IS_TIM1_OC_MODE(MODE) (((MODE) == TIM1_OCMode_Timing) || \ 00629 ((MODE) == TIM1_OCMode_Active) || \ 00630 ((MODE) == TIM1_OCMode_Inactive) || \ 00631 ((MODE) == TIM1_OCMode_Toggle)|| \ 00632 ((MODE) == TIM1_OCMode_PWM1) || \ 00633 ((MODE) == TIM1_OCMode_PWM2)) 00634 00635 #define IS_TIM1_OCM(MODE)(((MODE) == TIM1_OCMode_Timing) || \ 00636 ((MODE) == TIM1_OCMode_Active) || \ 00637 ((MODE) == TIM1_OCMode_Inactive) || \ 00638 ((MODE) == TIM1_OCMode_Toggle)|| \ 00639 ((MODE) == TIM1_OCMode_PWM1) || \ 00640 ((MODE) == TIM1_OCMode_PWM2) || \ 00641 ((MODE) == (uint8_t)TIM1_ForcedAction_Active) || \ 00642 ((MODE) == (uint8_t)TIM1_ForcedAction_Inactive)) 00643 00644 #define IS_TIM1_OPM_MODE(MODE) (((MODE) == TIM1_OPMode_Single) || \ 00645 ((MODE) == TIM1_OPMode_Repetitive)) 00646 00647 #define IS_TIM1_CHANNEL(CHANNEL) (((CHANNEL) == TIM1_Channel_1) || \ 00648 ((CHANNEL) == TIM1_Channel_2) || \ 00649 ((CHANNEL) == TIM1_Channel_3) || \ 00650 ((CHANNEL) == TIM1_Channel_4)) 00651 00652 #define IS_TIM1_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM1_Channel_1) || \ 00653 ((CHANNEL) == TIM1_Channel_2)) 00654 00655 #define IS_TIM1_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM1_Channel_1) || \ 00656 ((CHANNEL) == TIM1_Channel_2) || \ 00657 ((CHANNEL) == TIM1_Channel_3)) 00658 00659 #define IS_TIM1_COUNTER_MODE(MODE) (((MODE) == TIM1_CounterMode_Up) || \ 00660 ((MODE) == TIM1_CounterMode_Down) || \ 00661 ((MODE) == TIM1_CounterMode_CenterAligned1) || \ 00662 ((MODE) == TIM1_CounterMode_CenterAligned2) || \ 00663 ((MODE) == TIM1_CounterMode_CenterAligned3)) 00664 00665 #define IS_TIM1_OC_POLARITY(POLARITY) (((POLARITY) == TIM1_OCPolarity_High) || \ 00666 ((POLARITY) == TIM1_OCPolarity_Low)) 00667 00668 #define IS_TIM1_OCN_POLARITY(POLARITY) (((POLARITY) == TIM1_OCNPolarity_High) || \ 00669 ((POLARITY) == TIM1_OCNPolarity_Low)) 00670 00671 #define IS_TIM1_OUTPUT_STATE(STATE) (((STATE) == TIM1_OutputState_Disable) || \ 00672 ((STATE) == TIM1_OutputState_Enable)) 00673 00674 #define IS_TIM1_OUTPUTN_STATE(STATE) (((STATE) == TIM1_OutputNState_Disable) ||\ 00675 ((STATE) == TIM1_OutputNState_Enable)) 00676 00677 #define IS_TIM1_BREAK_STATE(STATE) (((STATE) == TIM1_BreakState_Enable) || \ 00678 ((STATE) == TIM1_BreakState_Disable)) 00679 00680 #define IS_TIM1_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM1_BreakPolarity_Low) || \ 00681 ((POLARITY) == TIM1_BreakPolarity_High)) 00682 00683 #define IS_TIM1_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM1_AutomaticOutput_Enable) || \ 00684 ((STATE) == TIM1_AutomaticOutput_Disable)) 00685 00686 #define IS_TIM1_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM1_LockLevel_Off) || \ 00687 ((LEVEL) == TIM1_LockLevel_1) || \ 00688 ((LEVEL) == TIM1_LockLevel_2) || \ 00689 ((LEVEL) == TIM1_LockLevel_3)) 00690 00691 #define IS_TIM1_OSSI_STATE(STATE) (((STATE) == TIM1_OSSIState_Enable) || \ 00692 ((STATE) == TIM1_OSSIState_Disable)) 00693 00694 #define IS_TIM1_OCIDLE_STATE(STATE) (((STATE) == TIM1_OCIdleState_Set) || \ 00695 ((STATE) == TIM1_OCIdleState_Reset)) 00696 00697 #define IS_TIM1_OCNIDLE_STATE(STATE) (((STATE) == TIM1_OCNIdleState_Set) || \ 00698 ((STATE) == TIM1_OCNIdleState_Reset)) 00699 00700 #define IS_TIM1_IC_POLARITY(POLARITY) (((POLARITY) == TIM1_ICPolarity_Rising) || \ 00701 ((POLARITY) == TIM1_ICPolarity_Falling)) 00702 00703 #define IS_TIM1_IC_SELECTION(SELECTION) (((SELECTION) == TIM1_ICSelection_DirectTI) || \ 00704 ((SELECTION) == TIM1_ICSelection_IndirectTI) || \ 00705 ((SELECTION) == TIM1_ICSelection_TRGI)) 00706 00707 #define IS_TIM1_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM1_ICPSC_DIV1) || \ 00708 ((PRESCALER) == TIM1_ICPSC_DIV2) || \ 00709 ((PRESCALER) == TIM1_ICPSC_DIV4) || \ 00710 ((PRESCALER) == TIM1_ICPSC_DIV8)) 00711 00712 #define IS_TIM1_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM1_OCReferenceClear_ETRF) || \ 00713 ((SOURCE) == TIM1_OCReferenceClear_OCREFCLR)) 00714 00715 #define IS_TIM1_IT(IT) ((IT) != 0x00) 00716 00717 #define IS_TIM1_GET_IT(IT) (((IT) == TIM1_IT_Update) || \ 00718 ((IT) == TIM1_IT_CC1) || \ 00719 ((IT) == TIM1_IT_CC2) || \ 00720 ((IT) == TIM1_IT_CC3) || \ 00721 ((IT) == TIM1_IT_CC4) || \ 00722 ((IT) == TIM1_IT_COM) || \ 00723 ((IT) == TIM1_IT_Trigger) || \ 00724 ((IT) == TIM1_IT_Break)) 00725 00726 #define IS_TIM1_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM1_ExtTRGPSC_OFF) || \ 00727 ((PRESCALER) == TIM1_ExtTRGPSC_DIV2) || \ 00728 ((PRESCALER) == TIM1_ExtTRGPSC_DIV4) || \ 00729 ((PRESCALER) == TIM1_ExtTRGPSC_DIV8)) 00730 00731 #define IS_TIM1_TRIGGER_SELECTION(SELECTION) \ 00732 (((SELECTION) == TIM1_TRGSelection_TIM2) || \ 00733 ((SELECTION) == TIM1_TRGSelection_TIM3) || \ 00734 ((SELECTION) == TIM1_TRGSelection_TIM4) || \ 00735 ((SELECTION) == TIM1_TRGSelection_TIM5) || \ 00736 ((SELECTION) == TIM1_TRGSelection_TI1F_ED) || \ 00737 ((SELECTION) == TIM1_TRGSelection_TI1FP1) || \ 00738 ((SELECTION) == TIM1_TRGSelection_TI2FP2) || \ 00739 ((SELECTION) == TIM1_TRGSelection_ETRF)) 00740 00741 00742 #define IS_TIM1_TIX_TRIGGER_SELECTION(SELECTION) \ 00743 (((SELECTION) == TIM1_TRGSelection_TI1F_ED) || \ 00744 ((SELECTION) == TIM1_TRGSelection_TI1FP1) || \ 00745 ((SELECTION) == TIM1_TRGSelection_TI2FP2)) 00746 00747 #define IS_TIM1_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM1_TIxExternalCLK1Source_TI1ED) || \ 00748 ((SOURCE) == TIM1_TIxExternalCLK1Source_TI2) || \ 00749 ((SOURCE) == TIM1_TIxExternalCLK1Source_TI1)) 00750 00751 #define IS_TIM1_EXT_POLARITY(POLARITY) (((POLARITY) == TIM1_ExtTRGPolarity_Inverted) || \ 00752 ((POLARITY) == TIM1_ExtTRGPolarity_NonInverted)) 00753 00754 #define IS_TIM1_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM1_PSCReloadMode_Update) || \ 00755 ((RELOAD) == TIM1_PSCReloadMode_Immediate)) 00756 00757 #define IS_TIM1_ENCODER_MODE(MODE) (((MODE) == TIM1_EncoderMode_TI1) || \ 00758 ((MODE) == TIM1_EncoderMode_TI2) || \ 00759 ((MODE) == TIM1_EncoderMode_TI12)) 00760 00761 #define IS_TIM1_EVENT_SOURCE(SOURCE) ((SOURCE) != 0x00) 00762 00763 #define IS_TIM1_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM1_TRGOSource_Reset) || \ 00764 ((SOURCE) == TIM1_TRGOSource_Enable) || \ 00765 ((SOURCE) == TIM1_TRGOSource_Update) || \ 00766 ((SOURCE) == TIM1_TRGOSource_OC1) || \ 00767 ((SOURCE) == TIM1_TRGOSource_OC1REF) || \ 00768 ((SOURCE) == TIM1_TRGOSource_OC2REF) || \ 00769 ((SOURCE) == TIM1_TRGOSource_OC3REF) || \ 00770 ((SOURCE) == TIM1_TRGOSource_OC4REF)) 00771 00772 00773 #define IS_TIM1_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM1_UpdateSource_Global) || \ 00774 ((SOURCE) == TIM1_UpdateSource_Regular)) 00775 00776 #define IS_TIM1_GET_FLAG(FLAG) (((FLAG) == TIM1_FLAG_Update) || \ 00777 ((FLAG) == TIM1_FLAG_CC1) || \ 00778 ((FLAG) == TIM1_FLAG_CC2) || \ 00779 ((FLAG) == TIM1_FLAG_CC3) || \ 00780 ((FLAG) == TIM1_FLAG_CC4) || \ 00781 ((FLAG) == TIM1_FLAG_COM) || \ 00782 ((FLAG) == TIM1_FLAG_Trigger)|| \ 00783 ((FLAG) == TIM1_FLAG_Break) || \ 00784 ((FLAG) == TIM1_FLAG_CC1OF) || \ 00785 ((FLAG) == TIM1_FLAG_CC2OF) || \ 00786 ((FLAG) == TIM1_FLAG_CC3OF) || \ 00787 ((FLAG) == TIM1_FLAG_CC4OF)) 00788 00789 00790 #define IS_TIM1_SLAVE_MODE(MODE) (((MODE) == TIM1_SlaveMode_Reset) || \ 00791 ((MODE) == TIM1_SlaveMode_Gated) || \ 00792 ((MODE) == TIM1_SlaveMode_Trigger) || \ 00793 ((MODE) == TIM1_SlaveMode_External1)) 00794 00795 #define IS_TIM1_CLEAR_FLAG(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xE100) == 0x0000) && ((FLAG) != 0x0000)) 00796 00797 #define IS_TIM1_FORCED_ACTION(ACTION) (((ACTION) == TIM1_ForcedAction_Active) || \ 00798 ((ACTION) == TIM1_ForcedAction_Inactive)) 00799 00800 #define IS_TIM1_DMA_SOURCE(SOURCE) \ 00801 (((SOURCE) == TIM1_DMASource_Update) || \ 00802 ((SOURCE) == TIM1_DMASource_CC1) || \ 00803 ((SOURCE) == TIM1_DMASource_CC2) || \ 00804 ((SOURCE) == TIM1_DMASource_CC3) || \ 00805 ((SOURCE) == TIM1_DMASource_CC4) || \ 00806 ((SOURCE) == TIM1_DMASource_COM)) 00807 00808 #define IS_TIM1_DMABase(SOURCE) \ 00809 (((SOURCE) == TIM1_DMABase_CR1) || \ 00810 ((SOURCE) == TIM1_DMABase_CR2) || \ 00811 ((SOURCE) == TIM1_DMABase_SMCR) || \ 00812 ((SOURCE) == TIM1_DMABase_ETR) || \ 00813 ((SOURCE) == TIM1_DMABase_DER) || \ 00814 ((SOURCE) == TIM1_DMABase_IER) || \ 00815 ((SOURCE) == TIM1_DMABase_SR1) || \ 00816 ((SOURCE) == TIM1_DMABase_SR2) || \ 00817 ((SOURCE) == TIM1_DMABase_EGR) || \ 00818 ((SOURCE) == TIM1_DMABase_CCMR1) || \ 00819 ((SOURCE) == TIM1_DMABase_CCMR2 ) || \ 00820 ((SOURCE) == TIM1_DMABase_CCMR3) || \ 00821 ((SOURCE) == TIM1_DMABase_CCMR4) || \ 00822 ((SOURCE) == TIM1_DMABase_CCER1) || \ 00823 ((SOURCE) == TIM1_DMABase_CCER2) || \ 00824 ((SOURCE) == TIM1_DMABase_CNTH) || \ 00825 ((SOURCE) == TIM1_DMABase_CNTL) || \ 00826 ((SOURCE) == TIM1_DMABase_PSCH) || \ 00827 ((SOURCE) == TIM1_DMABase_PSCL) || \ 00828 ((SOURCE) == TIM1_DMABase_ARRH) || \ 00829 ((SOURCE) == TIM1_DMABase_ARRL) || \ 00830 ((SOURCE) == TIM1_DMABase_RCR) || \ 00831 ((SOURCE) == TIM1_DMABase_CCR1H) || \ 00832 ((SOURCE) == TIM1_DMABase_CCR1L) || \ 00833 ((SOURCE) == TIM1_DMABase_CCR2H ) || \ 00834 ((SOURCE) == TIM1_DMABase_CCR2L) || \ 00835 ((SOURCE) == TIM1_DMABase_CCR3H) || \ 00836 ((SOURCE) == TIM1_DMABase_CCR3L) || \ 00837 ((SOURCE) == TIM1_DMABase_CCR4H) || \ 00838 ((SOURCE) == TIM1_DMABase_CCR4L) || \ 00839 ((SOURCE) == TIM1_DMABase_BKR) || \ 00840 ((SOURCE) == TIM1_DMABase_DTR)) 00841 00842 #define IS_TIM1_DMABurstLength(SOURCE) \ 00843 (((SOURCE) == TIM1_DMABurstLength_1Byte) || \ 00844 ((SOURCE) == TIM1_DMABurstLength_2Byte) || \ 00845 ((SOURCE) == TIM1_DMABurstLength_3Byte) || \ 00846 ((SOURCE) == TIM1_DMABurstLength_4Byte) || \ 00847 ((SOURCE) == TIM1_DMABurstLength_5Byte) || \ 00848 ((SOURCE) == TIM1_DMABurstLength_6Byte) || \ 00849 ((SOURCE) == TIM1_DMABurstLength_7Byte) || \ 00850 ((SOURCE) == TIM1_DMABurstLength_8Byte) || \ 00851 ((SOURCE) == TIM1_DMABurstLength_9Byte) || \ 00852 ((SOURCE) == TIM1_DMABurstLength_10Byte) || \ 00853 ((SOURCE) == TIM1_DMABurstLength_11Byte ) || \ 00854 ((SOURCE) == TIM1_DMABurstLength_12Byte) || \ 00855 ((SOURCE) == TIM1_DMABurstLength_13Byte) || \ 00856 ((SOURCE) == TIM1_DMABurstLength_14Byte) || \ 00857 ((SOURCE) == TIM1_DMABurstLength_15Byte) || \ 00858 ((SOURCE) == TIM1_DMABurstLength_16Byte) || \ 00859 ((SOURCE) == TIM1_DMABurstLength_17Byte) || \ 00860 ((SOURCE) == TIM1_DMABurstLength_18Byte) || \ 00861 ((SOURCE) == TIM1_DMABurstLength_19Byte) || \ 00862 ((SOURCE) == TIM1_DMABurstLength_20Byte) || \ 00863 ((SOURCE) == TIM1_DMABurstLength_21Byte) || \ 00864 ((SOURCE) == TIM1_DMABurstLength_22Byte) || \ 00865 ((SOURCE) == TIM1_DMABurstLength_23Byte) || \ 00866 ((SOURCE) == TIM1_DMABurstLength_24Byte) || \ 00867 ((SOURCE) == TIM1_DMABurstLength_25Byte) || \ 00868 ((SOURCE) == TIM1_DMABurstLength_26Byte) || \ 00869 ((SOURCE) == TIM1_DMABurstLength_27Byte) || \ 00870 ((SOURCE) == TIM1_DMABurstLength_28Byte) || \ 00871 ((SOURCE) == TIM1_DMABurstLength_29Byte) || \ 00872 ((SOURCE) == TIM1_DMABurstLength_30Byte) || \ 00873 ((SOURCE) == TIM1_DMABurstLength_31Byte) || \ 00874 ((SOURCE) == TIM1_DMABurstLength_32Byte)) 00875 00876 /** TIM1 External Trigger Filer Value */ 00877 #define IS_TIM1_EXT_TRG_FILTER(FILTER) ((FILTER) <= 0x0F) 00878 00879 /** TIM1 Input Capture Filer Value */ 00880 #define IS_TIM1_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0F) 00881 /** 00882 * @} 00883 */ 00884 00885 /* Exported Functions -----------------------------------------------------------*/ 00886 00887 /* TimeBase management ********************************************************/ 00888 void TIM1_DeInit(void); 00889 void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler, 00890 TIM1_CounterMode_TypeDef TIM1_CounterMode, 00891 uint16_t TIM1_Period, 00892 uint8_t TIM1_RepetitionCounter); 00893 void TIM1_PrescalerConfig(uint16_t Prescaler, 00894 TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode); 00895 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode); 00896 void TIM1_SetCounter(uint16_t Counter); 00897 void TIM1_SetAutoreload(uint16_t Autoreload); 00898 uint16_t TIM1_GetCounter(void); 00899 uint16_t TIM1_GetPrescaler(void); 00900 void TIM1_UpdateDisableConfig(FunctionalState NewState); 00901 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource); 00902 void TIM1_ARRPreloadConfig(FunctionalState NewState); 00903 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode); 00904 void TIM1_Cmd(FunctionalState NewState); 00905 00906 /* Output Compare management **************************************************/ 00907 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode, 00908 TIM1_OutputState_TypeDef TIM1_OutputState, 00909 TIM1_OutputNState_TypeDef TIM1_OutputNState, 00910 uint16_t TIM1_Pulse, 00911 TIM1_OCPolarity_TypeDef TIM1_OCPolarity, 00912 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, 00913 TIM1_OCIdleState_TypeDef TIM1_OCIdleState, 00914 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState); 00915 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode, 00916 TIM1_OutputState_TypeDef TIM1_OutputState, 00917 TIM1_OutputNState_TypeDef TIM1_OutputNState, 00918 uint16_t TIM1_Pulse, 00919 TIM1_OCPolarity_TypeDef TIM1_OCPolarity, 00920 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, 00921 TIM1_OCIdleState_TypeDef TIM1_OCIdleState, 00922 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState); 00923 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode, 00924 TIM1_OutputState_TypeDef TIM1_OutputState, 00925 TIM1_OutputNState_TypeDef TIM1_OutputNState, 00926 uint16_t TIM1_Pulse, 00927 TIM1_OCPolarity_TypeDef TIM1_OCPolarity, 00928 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity, 00929 TIM1_OCIdleState_TypeDef TIM1_OCIdleState, 00930 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState); 00931 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState, 00932 TIM1_LockLevel_TypeDef TIM1_LockLevel, 00933 uint8_t TIM1_DeadTime, 00934 TIM1_BreakState_TypeDef TIM1_Break, 00935 TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity, 00936 TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput); 00937 void TIM1_CtrlPWMOutputs(FunctionalState NewState); 00938 void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode); 00939 void TIM1_SetCompare1(uint16_t Compare1); 00940 void TIM1_SetCompare2(uint16_t Compare2); 00941 void TIM1_SetCompare3(uint16_t Compare3); 00942 void TIM1_SetCompare4(uint16_t Compare4); 00943 void TIM1_CCPreloadControl(FunctionalState NewState); 00944 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction); 00945 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction); 00946 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction); 00947 void TIM1_OC1PreloadConfig(FunctionalState NewState); 00948 void TIM1_OC2PreloadConfig(FunctionalState NewState); 00949 void TIM1_OC3PreloadConfig(FunctionalState NewState); 00950 void TIM1_OC4PreloadConfig(FunctionalState NewState); 00951 void TIM1_OC1FastConfig(FunctionalState NewState); 00952 void TIM1_OC2FastConfig(FunctionalState NewState); 00953 void TIM1_OC3FastConfig(FunctionalState NewState); 00954 void TIM1_ClearOC1Ref(FunctionalState NewState); 00955 void TIM1_ClearOC2Ref(FunctionalState NewState); 00956 void TIM1_ClearOC3Ref(FunctionalState NewState); 00957 void TIM1_ClearOC4Ref(FunctionalState NewState); 00958 void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity); 00959 void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity); 00960 void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity); 00961 void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity); 00962 void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity); 00963 void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity); 00964 void TIM1_SelectOCREFClear(TIM1_OCReferenceClear_TypeDef TIM1_OCReferenceClear); 00965 void TIM1_SelectCOM(FunctionalState NewState); 00966 void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState); 00967 void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState); 00968 00969 /* Input Capture management ***************************************************/ 00970 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel, 00971 TIM1_ICPolarity_TypeDef TIM1_ICPolarity, 00972 TIM1_ICSelection_TypeDef TIM1_ICSelection, 00973 TIM1_ICPSC_TypeDef TIM1_ICPrescaler, 00974 uint8_t TIM1_ICFilter); 00975 void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel, 00976 TIM1_ICPolarity_TypeDef TIM1_ICPolarity, 00977 TIM1_ICSelection_TypeDef TIM1_ICSelection, 00978 TIM1_ICPSC_TypeDef TIM1_ICPrescaler, 00979 uint8_t TIM1_ICFilter); 00980 uint16_t TIM1_GetCapture1(void); 00981 uint16_t TIM1_GetCapture2(void); 00982 uint16_t TIM1_GetCapture3(void); 00983 uint16_t TIM1_GetCapture4(void); 00984 void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler); 00985 void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler); 00986 void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler); 00987 void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler); 00988 00989 /* Interrupts, DMA and flags management ***************************************/ 00990 void TIM1_ITConfig(TIM1_IT_TypeDef TIM1_IT, FunctionalState NewState); 00991 void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource); 00992 FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG); 00993 void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG); 00994 ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT); 00995 void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT); 00996 void TIM1_DMAConfig(TIM1_DMABase_TypeDef TIM1_DMABase, 00997 TIM1_DMABurstLength_TypeDef TIM1_DMABurstLength); 00998 void TIM1_DMACmd(TIM1_DMASource_TypeDef TIM1_DMASource, FunctionalState NewState); 00999 void TIM1_SelectCCDMA(FunctionalState NewState); 01000 01001 /* Clocks management **********************************************************/ 01002 void TIM1_InternalClockConfig(void); 01003 void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource, 01004 TIM1_ICPolarity_TypeDef TIM1_ICPolarity, 01005 uint8_t ICFilter); 01006 void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, 01007 TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, 01008 uint8_t ExtTRGFilter); 01009 void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, 01010 TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, 01011 uint8_t ExtTRGFilter); 01012 01013 /* Synchronization management *************************************************/ 01014 void TIM1_SelectInputTrigger(TIM1_TRGSelection_TypeDef TIM1_InputTriggerSource); 01015 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource); 01016 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode); 01017 void TIM1_SelectMasterSlaveMode(FunctionalState NewState); 01018 void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler, 01019 TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity, 01020 uint8_t ExtTRGFilter); 01021 01022 /* Specific interface management **********************************************/ 01023 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode, 01024 TIM1_ICPolarity_TypeDef TIM1_IC1Polarity, 01025 TIM1_ICPolarity_TypeDef TIM1_IC2Polarity); 01026 void TIM1_SelectHallSensor(FunctionalState NewState); 01027 01028 #endif /* __STM8L15x_TIM1_H */ 01029 01030 /** 01031 * @} 01032 */ 01033 01034 /** 01035 * @} 01036 */ 01037 01038 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/