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STM8L15x Standard Peripherals Drivers
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stm8l15x_itc.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_itc.h 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file contains all the functions prototypes for the ITC firmware 00008 * library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00013 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00014 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00015 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00016 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00017 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00018 * 00019 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00020 ****************************************************************************** 00021 */ 00022 00023 /* Define to prevent recursive inclusion -------------------------------------*/ 00024 #ifndef __STM8L15x_ITC_H__ 00025 #define __STM8L15x_ITC_H__ 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm8l15x.h" 00029 00030 /** @addtogroup STM8L15x_StdPeriph_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup ITC 00035 * @{ 00036 */ 00037 /* Exported types ------------------------------------------------------------*/ 00038 00039 /** @defgroup ITC_Exported_Types 00040 * @{ 00041 */ 00042 00043 /** @defgroup ITC_Interrupt_Lines_selection 00044 * @{ 00045 */ 00046 typedef enum { 00047 FLASH_IRQn = (uint8_t)1, /*!< Flash interrupt */ 00048 DMA1_CHANNEL0_1_IRQn = (uint8_t)2, /*!< DMA Channels 0/1 */ 00049 DMA1_CHANNEL2_3_IRQn = (uint8_t)3, /*!< DMA Channels 2/3 */ 00050 EXTIE_F_PVD_IRQn = (uint8_t)5, /*!< GPIOE/F and PVD interrupt */ 00051 EXTI0_IRQn = (uint8_t)8, /*!< PIN0 interrupt */ 00052 EXTI1_IRQn = (uint8_t)9, /*!< PIN1 interrupt */ 00053 EXTI2_IRQn = (uint8_t)10, /*!< PIN2 interrupt */ 00054 EXTI3_IRQn = (uint8_t)11, /*!< PIN3 interrupt */ 00055 EXTI4_IRQn = (uint8_t)12, /*!< PIN4 interrupt */ 00056 EXTI5_IRQn = (uint8_t)13, /*!< PIN5 interrupt */ 00057 EXTI6_IRQn = (uint8_t)14, /*!< PIN6 interrupt */ 00058 EXTI7_IRQn = (uint8_t)15, /*!< PIN7 interrupt */ 00059 ADC1_COMP_IRQn = (uint8_t)18, /*!< ADC1/Comparator interrupt */ 00060 TIM4_UPD_OVF_TRG_IRQn = (uint8_t)25, /*!< TIM4 Update/Overflow/Trigger interrupt */ 00061 SPI1_IRQn = (uint8_t)26, /*!< SPI1 interrupt */ 00062 #if defined (STM8L15X_MD) 00063 RTC_IRQn = (uint8_t)4, /*!< RTC interrupt */ 00064 EXTIB_IRQn = (uint8_t)6, /*!< GPIOB interrupt */ 00065 EXTID_IRQn = (uint8_t)7, /*!< GPIOD interrupt */ 00066 LCD_IRQn = (uint8_t)16, /*!< LCD Driver interrupt */ 00067 SWITCH_CSS_BREAK_DAC_IRQn = (uint8_t)17, /*!< Clock switch/CSS interrupt/TIM1 Break /DAC interrupt */ 00068 TIM2_UPD_OVF_TRG_BRK_IRQn = (uint8_t)19, /*!< TIM2 Update/Overflow/Trigger/Break interrupt*/ 00069 TIM2_CC_IRQn = (uint8_t)20, /*!< TIM2 input captute/output compare interrupt */ 00070 TIM3_UPD_OVF_TRG_BRK_IRQn = (uint8_t)21, /*!< TIM3 Update/Overflow/Trigger/Break interrupt */ 00071 TIM3_CC_IRQn = (uint8_t)22, /*!< TIM3 capture/compare interrupt */ 00072 TIM1_UPD_OVF_TRG_IRQn = (uint8_t)23, /*!< TIM1 TIM1 Update/Overflow/Trigger interrupt */ 00073 TIM1_CC_IRQn = (uint8_t)24, /*!< TIM1 capture/compare interrupt */ 00074 USART1_TX_IRQn = (uint8_t)27, /*!< USART1 TX interrupt */ 00075 USART1_RX_IRQn = (uint8_t)28, /*!< USART1 RX interrupt */ 00076 I2C1_IRQn = (uint8_t)29 /*!< I2C1 interrupt */ 00077 #elif defined (STM8L15X_LD) 00078 RTC_CSSLSE_IRQn = (uint8_t)4, /*!< RTC / CSSLSE interrupt */ 00079 EXTIB_IRQn = (uint8_t)6, /*!< GPIOB interrupt */ 00080 EXTID_IRQn = (uint8_t)7, /*!< GPIOD interrupt */ 00081 SWITCH_CSS_IRQn = (uint8_t)17, /*!< Clock switch/CSS interrupt/TIM1 Break /DAC interrupt */ 00082 TIM2_UPD_OVF_TRG_BRK_IRQn = (uint8_t)19, /*!< TIM2 Update/Overflow/Trigger/Break interrupt*/ 00083 TIM2_CC_IRQn = (uint8_t)20, /*!< TIM2 input captute/output compare interrupt */ 00084 TIM3_UPD_OVF_TRG_BRK_IRQn = (uint8_t)21, /*!< TIM3 Update/Overflow/Trigger/Break interrupt */ 00085 TIM3_CC_IRQn = (uint8_t)22, /*!< TIM3 capture/compare interrupt */ 00086 USART1_TX_IRQn = (uint8_t)27, /*!< USART1 TX interrupt */ 00087 USART1_RX_IRQn = (uint8_t)28, /*!< USART1 RX interrupt */ 00088 I2C1_IRQn = (uint8_t)29 /*!< I2C1 interrupt */ 00089 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00090 RTC_CSSLSE_IRQn = (uint8_t)4, /*!< RTC / CSSLSE interrupt */ 00091 EXTIB_G_IRQn = (uint8_t)6, /*!< GPIOB / G interrupt */ 00092 EXTID_H_IRQn = (uint8_t)7, /*!< GPIOD / H interrupt */ 00093 LCD_AES_IRQn = (uint8_t)16, /*!< LCD / AES interrupt */ 00094 SWITCH_CSS_BREAK_DAC_IRQn = (uint8_t)17, /*!< Clock switch/CSS interrupt/TIM1 Break /DAC interrupt */ 00095 TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn = (uint8_t)19, /*!< TIM2 Update/Overflow/Trigger/Break /USART2 TX interrupt*/ 00096 TIM2_CC_USART2_RX_IRQn = (uint8_t)20, /*!< TIM2 capture/compare / USART2 RX interrupt */ 00097 TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn = (uint8_t)21, /*!< TIM3 Update/Overflow/Trigger/Break / USART3 TX interrupt */ 00098 TIM3_CC_USART3_RX_IRQn = (uint8_t)22, /*!< TIM3 capture/compare / USART3 RX interrupt */ 00099 TIM1_UPD_OVF_TRG_IRQn = (uint8_t)23, /*!< TIM1 TIM1 Update/Overflow/Trigger interrupt */ 00100 TIM1_CC_IRQn = (uint8_t)24, /*!< TIM1 capture/compare interrupt */ 00101 USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn = (uint8_t)27, /*!< USART1 TX / TIM5 Update/Overflow/Trigger/Break interrupt */ 00102 USART1_RX_TIM5_CC_IRQn = (uint8_t)28, /*!< USART1 RX / TIM5 capture/compare interrupt */ 00103 I2C1_SPI2_IRQn = (uint8_t)29 /*!< I2C1 / SPI2 interrupt */ 00104 #endif /* STM8L15X_MD */ 00105 }IRQn_TypeDef; 00106 00107 #ifdef STM8L15X_MD 00108 #define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \ 00109 ((Irq) == DMA1_CHANNEL0_1_IRQn) || \ 00110 ((Irq) == DMA1_CHANNEL2_3_IRQn) || \ 00111 ((Irq) == RTC_IRQn) || \ 00112 ((Irq) == EXTIE_F_PVD_IRQn) || \ 00113 ((Irq) == EXTIB_IRQn) || \ 00114 ((Irq) == EXTID_IRQn) || \ 00115 ((Irq) == EXTI0_IRQn) || \ 00116 ((Irq) == EXTI1_IRQn) || \ 00117 ((Irq) == EXTI2_IRQn) || \ 00118 ((Irq) == EXTI3_IRQn) || \ 00119 ((Irq) == EXTI4_IRQn) || \ 00120 ((Irq) == EXTI5_IRQn) || \ 00121 ((Irq) == EXTI6_IRQn) || \ 00122 ((Irq) == EXTI7_IRQn) || \ 00123 ((Irq) == LCD_IRQn) || \ 00124 ((Irq) == SWITCH_CSS_BREAK_DAC_IRQn) || \ 00125 ((Irq) == ADC1_COMP_IRQn) || \ 00126 ((Irq) == TIM2_UPD_OVF_TRG_BRK_IRQn) || \ 00127 ((Irq) == TIM2_CC_IRQn) || \ 00128 ((Irq) == TIM3_UPD_OVF_TRG_BRK_IRQn) || \ 00129 ((Irq) == TIM3_CC_IRQn) || \ 00130 ((Irq) == TIM1_UPD_OVF_TRG_IRQn) || \ 00131 ((Irq) == TIM1_CC_IRQn) || \ 00132 ((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \ 00133 ((Irq) == SPI1_IRQn) || \ 00134 ((Irq) == USART1_TX_IRQn) || \ 00135 ((Irq) == USART1_RX_IRQn) || \ 00136 ((Irq) == I2C1_IRQn)) 00137 #elif defined (STM8L15X_LD) 00138 #define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \ 00139 ((Irq) == DMA1_CHANNEL0_1_IRQn) || \ 00140 ((Irq) == DMA1_CHANNEL2_3_IRQn) || \ 00141 ((Irq) == RTC_CSSLSE_IRQn) || \ 00142 ((Irq) == EXTIE_F_PVD_IRQn) || \ 00143 ((Irq) == EXTIB_IRQn) || \ 00144 ((Irq) == EXTID_IRQn) || \ 00145 ((Irq) == EXTI0_IRQn) || \ 00146 ((Irq) == EXTI1_IRQn) || \ 00147 ((Irq) == EXTI2_IRQn) || \ 00148 ((Irq) == EXTI3_IRQn) || \ 00149 ((Irq) == EXTI4_IRQn) || \ 00150 ((Irq) == EXTI5_IRQn) || \ 00151 ((Irq) == EXTI6_IRQn) || \ 00152 ((Irq) == EXTI7_IRQn) || \ 00153 ((Irq) == SWITCH_CSS_IRQn) || \ 00154 ((Irq) == ADC1_COMP_IRQn) || \ 00155 ((Irq) == TIM2_UPD_OVF_TRG_BRK_IRQn) || \ 00156 ((Irq) == TIM2_CC_IRQn) || \ 00157 ((Irq) == TIM3_UPD_OVF_TRG_BRK_IRQn) || \ 00158 ((Irq) == TIM3_CC_IRQn) || \ 00159 ((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \ 00160 ((Irq) == SPI1_IRQn) || \ 00161 ((Irq) == USART1_TX_IRQn) || \ 00162 ((Irq) == USART1_RX_IRQn) || \ 00163 ((Irq) == I2C1_IRQn)) 00164 #elif defined (STM8L15X_HD) || defined (STM8L15X_MDP) 00165 #define IS_ITC_IRQ(Irq) (((Irq) == FLASH_IRQn) || \ 00166 ((Irq) == DMA1_CHANNEL0_1_IRQn) || \ 00167 ((Irq) == DMA1_CHANNEL2_3_IRQn) || \ 00168 ((Irq) == RTC_CSSLSE_IRQn) || \ 00169 ((Irq) == EXTIE_F_PVD_IRQn) || \ 00170 ((Irq) == EXTIB_G_IRQn) || \ 00171 ((Irq) == EXTID_H_IRQn) || \ 00172 ((Irq) == EXTI0_IRQn) || \ 00173 ((Irq) == EXTI1_IRQn) || \ 00174 ((Irq) == EXTI2_IRQn) || \ 00175 ((Irq) == EXTI3_IRQn) || \ 00176 ((Irq) == EXTI4_IRQn) || \ 00177 ((Irq) == EXTI5_IRQn) || \ 00178 ((Irq) == EXTI6_IRQn) || \ 00179 ((Irq) == EXTI7_IRQn) || \ 00180 ((Irq) == LCD_AES_IRQn) || \ 00181 ((Irq) == SWITCH_CSS_BREAK_DAC_IRQn) || \ 00182 ((Irq) == ADC1_COMP_IRQn) || \ 00183 ((Irq) == TIM2_UPD_OVF_TRG_BRK_USART2_TX_IRQn) || \ 00184 ((Irq) == TIM2_CC_USART2_RX_IRQn) || \ 00185 ((Irq) == TIM3_UPD_OVF_TRG_BRK_USART3_TX_IRQn) || \ 00186 ((Irq) == TIM3_CC_USART3_RX_IRQn) || \ 00187 ((Irq) == TIM1_UPD_OVF_TRG_IRQn) || \ 00188 ((Irq) == TIM1_CC_IRQn) || \ 00189 ((Irq) == TIM4_UPD_OVF_TRG_IRQn) || \ 00190 ((Irq) == SPI1_IRQn) || \ 00191 ((Irq) == USART1_TX_TIM5_UPD_OVF_TRG_BRK_IRQn) || \ 00192 ((Irq) == USART1_RX_TIM5_CC_IRQn) || \ 00193 ((Irq) == I2C1_SPI2_IRQn)) 00194 #endif /* STM8L15X_MD */ 00195 00196 /** 00197 * @} 00198 */ 00199 00200 /** @defgroup ITC_Priority_Level_selection 00201 * @{ 00202 */ 00203 typedef enum { 00204 ITC_PriorityLevel_0 = (uint8_t)0x02, /*!< Software priority level 0 (cannot be written) */ 00205 ITC_PriorityLevel_1 = (uint8_t)0x01, /*!< Software priority level 1 */ 00206 ITC_PriorityLevel_2 = (uint8_t)0x00, /*!< Software priority level 2 */ 00207 ITC_PriorityLevel_3 = (uint8_t)0x03 /*!< Software priority level 3 */ 00208 } ITC_PriorityLevel_TypeDef; 00209 00210 #define IS_ITC_PRIORITY(PriorityValue) \ 00211 (((PriorityValue) == ITC_PriorityLevel_0) || \ 00212 ((PriorityValue) == ITC_PriorityLevel_1) || \ 00213 ((PriorityValue) == ITC_PriorityLevel_2) || \ 00214 ((PriorityValue) == ITC_PriorityLevel_3)) 00215 00216 /** 00217 * @} 00218 */ 00219 00220 /** 00221 * @} 00222 */ 00223 /* Exported constants --------------------------------------------------------*/ 00224 00225 /** @defgroup ITC_Exported_Constants 00226 * @{ 00227 */ 00228 00229 #define CPU_SOFT_INT_DISABLED ((uint8_t)0x28) /*!< Mask for I1 and I0 bits in CPU_CC register */ 00230 00231 /** 00232 * @} 00233 */ 00234 00235 /* Exported macros -----------------------------------------------------------*/ 00236 00237 /** @defgroup ITC_Exported_Constants 00238 * @{ 00239 */ 00240 #define IS_ITC_INTERRUPTS_DISABLED (ITC_GetSoftIntStatus() == CPU_SOFT_INT_DISABLED) 00241 00242 /** 00243 * @} 00244 */ 00245 00246 /* Exported functions ------------------------------------------------------- */ 00247 /* Function used to set the ITC configuration to the default reset state ******/ 00248 void ITC_DeInit(void); 00249 00250 /* ITC configuration and management functions ******/ 00251 uint8_t ITC_GetCPUCC(void); 00252 uint8_t ITC_GetSoftIntStatus(void); 00253 void ITC_SetSoftwarePriority(IRQn_TypeDef IRQn, ITC_PriorityLevel_TypeDef ITC_PriorityLevel); 00254 ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(IRQn_TypeDef IRQn); 00255 00256 #endif /* __STM8L15x_ITC_H__ */ 00257 00258 /** 00259 * @} 00260 */ 00261 00262 /** 00263 * @} 00264 */ 00265 00266 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/