|
STM8L15x Standard Peripherals Drivers
|
stm8l15x_i2c.h
Go to the documentation of this file.
00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_i2c.h 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file contains all the functions prototypes for the I2C firmware 00008 * library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00013 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00014 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00015 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00016 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00017 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00018 * 00019 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00020 ****************************************************************************** 00021 */ 00022 00023 /* Define to prevent recursive inclusion -------------------------------------*/ 00024 #ifndef __STM8L15x_I2C_H 00025 #define __STM8L15x_I2C_H 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm8l15x.h" 00029 00030 /** @addtogroup STM8L15x_StdPeriph_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup I2C 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup I2C_Exported_Types 00040 * @{ 00041 */ 00042 /** @defgroup I2C_mode 00043 * @{ 00044 */ 00045 typedef enum 00046 { 00047 I2C_Mode_I2C = (uint8_t)0x00, /*!< I2C mode */ 00048 I2C_Mode_SMBusDevice = (uint8_t)0x02, /*!< SMBus Device mode */ 00049 I2C_Mode_SMBusHost = (uint8_t)0x0A /*!< SMBus Host mode */ 00050 } I2C_Mode_TypeDef; 00051 00052 /** 00053 * @} 00054 */ 00055 00056 /** @defgroup I2C_duty_cycle_in_fast_mode 00057 * @{ 00058 */ 00059 typedef enum 00060 { 00061 I2C_DutyCycle_2 = (uint8_t)0x00, /*!< Fast mode Tlow/THigh = 2 */ 00062 I2C_DutyCycle_16_9 = (uint8_t)0x40 /*!< Fast mode Tlow/Thigh = 16/9 */ 00063 } I2C_DutyCycle_TypeDef; 00064 00065 /** 00066 * @} 00067 */ 00068 00069 /** @defgroup I2C_acknowledgement 00070 * @{ 00071 */ 00072 typedef enum 00073 { 00074 I2C_Ack_Disable = (uint8_t)0x00, /*!< No acknowledge */ 00075 I2C_Ack_Enable = (uint8_t)0x04 /*!< Acknowledge Enabled */ 00076 } I2C_Ack_TypeDef; 00077 /** 00078 * @} 00079 */ 00080 00081 /** @defgroup I2C_Position_Acknowledgement 00082 * @{ 00083 */ 00084 typedef enum 00085 { 00086 I2C_AckPosition_Current = (uint8_t)0x00, /*!< Acknowledge on the current byte */ 00087 I2C_AckPosition_Next = (uint8_t)0x08 /*!< Acknowledge on the next byte */ 00088 } I2C_AckPosition_TypeDef; 00089 00090 /** 00091 * @} 00092 */ 00093 00094 /** @defgroup I2C_acknowledged_address 00095 * @{ 00096 */ 00097 typedef enum 00098 { 00099 I2C_AcknowledgedAddress_7bit = (uint8_t)0x00, /*!< 7-bit slave address (10-bit address not acknowledged) */ 00100 I2C_AcknowledgedAddress_10bit = (uint8_t)0x80 /*!< 10-bit slave address (7-bit address not acknowledged) */ 00101 } I2C_AcknowledgedAddress_TypeDef; 00102 /** 00103 * @} 00104 */ 00105 00106 /** @defgroup I2C_transfer_direction 00107 * @{ 00108 */ 00109 00110 /** 00111 * Warning: the values correspond to the ADD0 bit position in the OARL register 00112 */ 00113 typedef enum 00114 { 00115 I2C_Direction_Transmitter = (uint8_t)0x00, /*!< Transmission direction */ 00116 I2C_Direction_Receiver = (uint8_t)0x01 /*!< Reception direction */ 00117 } I2C_Direction_TypeDef; 00118 00119 /** 00120 * @} 00121 */ 00122 00123 /** @defgroup I2C_SMBus_alert_pin_level 00124 * @{ 00125 */ 00126 typedef enum 00127 { 00128 I2C_SMBusAlert_High = (uint8_t)0x00, /*!< SMBAlert pin high */ 00129 I2C_SMBusAlert_Low = (uint8_t)0x01 /*!< SMBAlert pin Low */ 00130 } I2C_SMBusAlert_TypeDef; 00131 00132 /** 00133 * @} 00134 */ 00135 00136 /** @defgroup I2C_PEC_position 00137 * @{ 00138 */ 00139 typedef enum 00140 { 00141 I2C_PECPosition_Current = (uint8_t)0x00, /*!< Current byte in shift register is PEC */ 00142 I2C_PECPosition_Next = (uint8_t)0x08 /*!< Next byte in shift register is PEC */ 00143 } I2C_PECPosition_TypeDef; 00144 /** 00145 * @} 00146 */ 00147 00148 /** @defgroup I2C_flags_definition 00149 * @{ 00150 */ 00151 /** 00152 * @brief Elements values convention: 0xXXYY 00153 * X = SRx registers index 00154 * X = 1 : SR1 00155 * X = 2 : SR2 00156 * X = 3 : SR3 00157 * Y = Flag mask in the register 00158 */ 00159 00160 typedef enum 00161 { 00162 /* SR1 register flags */ 00163 I2C_FLAG_TXE = (uint16_t)0x0180, /*!< Transmit Data Register Empty flag */ 00164 I2C_FLAG_RXNE = (uint16_t)0x0140, /*!< Read Data Register Not Empty flag */ 00165 I2C_FLAG_STOPF = (uint16_t)0x0110, /*!< Stop detected flag */ 00166 I2C_FLAG_ADD10 = (uint16_t)0x0108, /*!< 10-bit Header sent flag */ 00167 I2C_FLAG_BTF = (uint16_t)0x0104, /*!< Data Byte Transfer Finished flag */ 00168 I2C_FLAG_ADDR = (uint16_t)0x0102, /*!< Address Sent/Matched (master/slave) flag */ 00169 I2C_FLAG_SB = (uint16_t)0x0101, /*!< Start bit sent flag */ 00170 00171 /* SR2 register flags */ 00172 I2C_FLAG_SMBALERT = (uint16_t)0x0280, /*!< SMBUS Alert flag */ 00173 I2C_FLAG_TIMEOUT = (uint16_t)0x0240, /*!< Time out flag */ 00174 I2C_FLAG_WUFH = (uint16_t)0x0220, /*!< Wake Up From Halt flag */ 00175 I2C_FLAG_PECERR = (uint16_t)0x0210, /*!< PEC error flag */ 00176 I2C_FLAG_OVR = (uint16_t)0x0208, /*!< Overrun/Underrun flag */ 00177 I2C_FLAG_AF = (uint16_t)0x0204, /*!< Acknowledge Failure flag */ 00178 I2C_FLAG_ARLO = (uint16_t)0x0202, /*!< Arbitration Loss flag */ 00179 I2C_FLAG_BERR = (uint16_t)0x0201, /*!< Misplaced Start or Stop condition */ 00180 00181 /* SR3 register flags */ 00182 I2C_FLAG_DUALF = (uint16_t)0x0380, /*!< DUAL Flag */ 00183 I2C_FLAG_SMBHOST = (uint16_t)0x0340, /*!< SMBUS host Flag */ 00184 I2C_FLAG_SMBDEFAULT = (uint16_t)0x0320, /*!< SMBUS default flag */ 00185 I2C_FLAG_GENCALL = (uint16_t)0x0310, /*!< General Call header received Flag */ 00186 I2C_FLAG_TRA = (uint16_t)0x0304, /*!< Transmitter Receiver flag */ 00187 I2C_FLAG_BUSY = (uint16_t)0x0302, /*!< Bus Busy flag */ 00188 I2C_FLAG_MSL = (uint16_t)0x0301 /*!< Master Slave flag */ 00189 } I2C_FLAG_TypeDef; 00190 00191 00192 /** 00193 * @} 00194 */ 00195 00196 /** @defgroup I2C_interrupts_definition 00197 * @{ 00198 */ 00199 00200 /** 00201 * @brief I2C Pending bits 00202 * Elements values convention: 0xXYZZ 00203 * X = SRx registers index 00204 * X = 0 : ITR 00205 * X = 1 : SR1 00206 * X = 2 : SR2 00207 * Y = Position of the corresponding Interrupt 00208 * ZZ = flag mask in the dedicated register(X register) 00209 */ 00210 00211 typedef enum 00212 { 00213 I2C_IT_ERR = (uint16_t)0x0001, /*!< Error Interruption */ 00214 I2C_IT_EVT = (uint16_t)0x0002, /*!< Event Interruption */ 00215 I2C_IT_BUF = (uint16_t)0x0004, /*!< Buffer Interruption */ 00216 /* SR1 register*/ 00217 I2C_IT_TXE = (uint16_t)0x1680, /*!< Transmit Data Register Empty */ 00218 I2C_IT_RXNE = (uint16_t)0x1640, /*!< Read Data Register Not Empty */ 00219 I2C_IT_STOPF = (uint16_t)0x1210, /*!< Stop detected */ 00220 I2C_IT_ADD10 = (uint16_t)0x1208, /*!< 10-bit Header sent */ 00221 I2C_IT_BTF = (uint16_t)0x1204, /*!< Data Byte Transfer Finished */ 00222 I2C_IT_ADDR = (uint16_t)0x1202, /*!< Address Sent/Matched (master/slave) */ 00223 I2C_IT_SB = (uint16_t)0x1201, /*!< Start bit sent */ 00224 00225 /* SR2 register*/ 00226 I2C_IT_SMBALERT = (uint16_t)0x2180, /*!< SMBUS alert */ 00227 I2C_IT_TIMEOUT = (uint16_t)0x2140, /*!< Time out */ 00228 I2C_IT_WUFH = (uint16_t)0x2220, /*!< PEC error */ 00229 I2C_IT_PECERR = (uint16_t)0x2110, /*!< Wake Up From Halt */ 00230 I2C_IT_OVR = (uint16_t)0x2108, /*!< Overrun/Underrun */ 00231 I2C_IT_AF = (uint16_t)0x2104, /*!< Acknowledge Failure */ 00232 I2C_IT_ARLO = (uint16_t)0x2102, /*!< Arbitration Loss */ 00233 I2C_IT_BERR = (uint16_t)0x2101 /*!< Misplaced Start or Stop condition */ 00234 } I2C_IT_TypeDef; 00235 /** 00236 * @} 00237 */ 00238 00239 /** @defgroup I2C_Events 00240 * @{ 00241 */ 00242 00243 /** 00244 * @brief I2C possible events 00245 * Values convention: 0xXXYY 00246 * XX = Event SR3 corresponding value 00247 * YY = Event SR1 corresponding value 00248 * @note if Event = EV3_2 the rule above does not apply 00249 * YY = Event SR2 corresponding value 00250 */ 00251 00252 typedef enum 00253 { 00254 /** 00255 =============================================================================== 00256 I2C Master Events (Events grouped in order of communication) 00257 =============================================================================== 00258 */ 00259 /** 00260 * @brief Communication start 00261 * 00262 * After sending the START condition (I2C_GenerateSTART() function) the master 00263 * has to wait for this event. It means that the Start condition has been correctly 00264 * released on the I2C bus (the bus is free, no other devices is communicating). 00265 * 00266 */ 00267 /* --EV5 */ 00268 I2C_EVENT_MASTER_MODE_SELECT = (uint16_t)0x0301, /*!< BUSY, MSL and SB flag */ 00269 00270 /** 00271 * @brief Address Acknowledge 00272 * 00273 * After checking on EV5 (start condition correctly released on the bus), the 00274 * master sends the address of the slave(s) with which it will communicate 00275 * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 00276 * Master transmitter or Receiver). 00277 * Then the master has to wait that a slave acknowledges his address. 00278 * If an acknowledge is sent on the bus, one of the following events will 00279 * be set: 00280 * 00281 * 1) In case of Master Receiver (7-bit addressing): 00282 * the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set. 00283 * 00284 * 2) In case of Master Transmitter (7-bit addressing): 00285 * the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set 00286 * 00287 * 3) In case of 10-Bit addressing mode, the master (just after generating the START 00288 * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 00289 * function). 00290 * Then master should wait on EV9. It means that the 10-bit addressing 00291 * header has been correctly sent on the bus. 00292 * Then master should send the second part of the 10-bit address (LSB) using 00293 * the function I2C_Send7bitAddress(). Then master should wait for event EV6. 00294 * 00295 */ 00296 /* --EV6 */ 00297 I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782, /*!< BUSY, MSL, ADDR, TXE and TRA flags */ 00298 I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = (uint16_t)0x0302, /*!< BUSY, MSL and ADDR flags */ 00299 /* --EV9 */ 00300 I2C_EVENT_MASTER_MODE_ADDRESS10 = (uint16_t)0x0308, /*!< BUSY, MSL and ADD10 flags */ 00301 00302 /** 00303 * @brief Communication events 00304 * 00305 * If a communication is established (START condition generated and slave address 00306 * acknowledged) then the master has to check on one of the following events for 00307 * communication procedures: 00308 * 00309 * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 00310 * the data received from the slave (I2C_ReceiveData() function). 00311 * 00312 * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 00313 * function) then to wait on event EV8 or EV8_2. 00314 * These two events are similar: 00315 * - EV8 means that the data has been written in the data register and is 00316 * being shifted out. 00317 * - EV8_2 means that the data has been physically shifted out and output 00318 * on the bus. 00319 * In most cases, using EV8 is sufficient for the application. 00320 * Using EV8_2 leads to a slower communication but ensure more reliable test. 00321 * EV8_2 is also more suitable than EV8 for testing on the last data transmission 00322 * (before Stop condition generation). 00323 * 00324 * @note In case the user software does not guarantee that this event EV7 is 00325 * managed before the current byte end of transfer, then user may check on EV7 00326 * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). 00327 * In this case the communication may be slower. 00328 * 00329 */ 00330 /* Master RECEIVER mode -----------------------------*/ 00331 /* --EV7 */ 00332 I2C_EVENT_MASTER_BYTE_RECEIVED = (uint16_t)0x0340, /*!< BUSY, MSL and RXNE flags */ 00333 00334 /* Master TRANSMITTER mode --------------------------*/ 00335 /* --EV8 */ 00336 I2C_EVENT_MASTER_BYTE_TRANSMITTING = (uint16_t)0x0780, /*!< TRA, BUSY, MSL, TXE flags */ 00337 /* --EV8_2 */ 00338 00339 I2C_EVENT_MASTER_BYTE_TRANSMITTED = (uint16_t)0x0784, /*!< EV8_2: TRA, BUSY, MSL, TXE and BTF flags */ 00340 00341 /** 00342 =============================================================================== 00343 I2C Slave Events (Events grouped in order of communication) 00344 =============================================================================== 00345 */ 00346 00347 /** 00348 * @brief Communication start events 00349 * 00350 * Wait on one of these events at the start of the communication. It means that 00351 * the I2C peripheral detected a Start condition on the bus (generated by master 00352 * device) followed by the peripheral address. 00353 * The peripheral generates an ACK condition on the bus (if the acknowledge 00354 * feature is enabled through function I2C_AcknowledgeConfig()) and the events 00355 * listed above are set : 00356 * 00357 * 1) In normal case (only one address managed by the slave), when the address 00358 * sent by the master matches the own address of the peripheral (configured by 00359 * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 00360 * (where XXX could be TRANSMITTER or RECEIVER). 00361 * 00362 * 2) In case the address sent by the master matches the second address of the 00363 * peripheral (configured by the function I2C_OwnAddress2Config() and enabled 00364 * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 00365 * (where XXX could be TRANSMITTER or RECEIVER) are set. 00366 * 00367 * 3) In case the address sent by the master is General Call (address 0x00) and 00368 * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 00369 * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. 00370 * 00371 */ 00372 00373 /* --EV1 (all the events below are variants of EV1) */ 00374 /* 1) Case of One Single Address managed by the slave */ 00375 I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = (uint16_t)0x0202, /*!< BUSY and ADDR flags */ 00376 I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682, /*!< TRA, BUSY, TXE and ADDR flags */ 00377 00378 /* 2) Case of Dual address managed by the slave */ 00379 I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED = (uint16_t)0x8200, /*! DUALF and BUSY flags */ 00380 I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED = (uint16_t)0x8680, /*! DUALF, TRA, BUSY and TXE flags */ 00381 00382 /* 3) Case of General Call enabled for the slave */ 00383 I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = (uint16_t)0x1200, /*!< EV2: GENCALL and BUSY flags */ 00384 00385 /** 00386 * @brief Communication events 00387 * 00388 * Wait on one of these events when EV1 has already been checked : 00389 * 00390 * - Slave RECEIVER mode: 00391 * - EV2: When the application is expecting a data byte to be received. 00392 * - EV4: When the application is expecting the end of the communication: 00393 * master sends a stop condition and data transmission is stopped. 00394 * 00395 * - Slave Transmitter mode: 00396 * - EV3: When a byte has been transmitted by the slave and the application 00397 * is expecting the end of the byte transmission. 00398 * The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING 00399 * are similar. The second one can optionally be used when the user software 00400 * doesn't guarantee the EV3 is managed before the current byte end of transfer. 00401 * - EV3_2: When the master sends a NACK in order to tell slave that data transmission 00402 * shall end (before sending the STOP condition). 00403 * In this case slave has to stop sending data bytes and expect a Stop 00404 * condition on the bus. 00405 * 00406 * @note In case the user software does not guarantee that the event EV2 is 00407 * managed before the current byte end of transfer, then user may check on EV2 00408 * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). 00409 * In this case the communication may be slower. 00410 * 00411 */ 00412 /* Slave RECEIVER mode --------------------------*/ 00413 /* --EV2 */ 00414 I2C_EVENT_SLAVE_BYTE_RECEIVED = (uint16_t)0x0240, /*!< BUSY and RXNE flags */ 00415 /* --EV4 */ 00416 I2C_EVENT_SLAVE_STOP_DETECTED = (uint16_t)0x0010, /*!< STOPF flag */ 00417 00418 /* Slave TRANSMITTER mode -----------------------*/ 00419 /* --EV3 */ 00420 I2C_EVENT_SLAVE_BYTE_TRANSMITTED = (uint16_t)0x0684, /*!< TRA, BUSY, TXE and BTF flags */ 00421 I2C_EVENT_SLAVE_BYTE_TRANSMITTING = (uint16_t)0x0680, /*!< TRA, BUSY and TXE flags */ 00422 /* --EV3_2 */ 00423 I2C_EVENT_SLAVE_ACK_FAILURE = (uint16_t)0x0004 /*!< AF flag */ 00424 } I2C_Event_TypeDef; 00425 00426 /** 00427 * @} 00428 */ 00429 00430 /** @defgroup I2C_Registers 00431 * @{ 00432 */ 00433 typedef enum 00434 { 00435 I2C_Register_CR1 = (uint8_t)0x00, /*!< Control register 1 */ 00436 I2C_Register_CR2 = (uint8_t)0x01, /*!< Control register 2 */ 00437 I2C_Register_FREQR = (uint8_t)0x02, /*!< Frequency register */ 00438 I2C_Register_OARL = (uint8_t)0x03, /*!< Own address register LSB */ 00439 I2C_Register_OARH = (uint8_t)0x04, /*!< Own address register MSB */ 00440 I2C_Register_DR = (uint8_t)0x06, /*!< Data register */ 00441 I2C_Register_SR1 = (uint8_t)0x07, /*!< Status register 1 */ 00442 I2C_Register_SR2 = (uint8_t)0x08, /*!< Status register 2 */ 00443 I2C_Register_SR3 = (uint8_t)0x09, /*!< Status register 3 */ 00444 I2C_Register_ITR = (uint8_t)0x0A, /*!< Interrupt and DMA register */ 00445 I2C_Register_CCRL = (uint8_t)0x0B, /*!< Clock control register low */ 00446 I2C_Register_CCRH = (uint8_t)0x0C, /*!< Clock control register high */ 00447 I2C_Register_TRISER = (uint8_t)0x0D, /*!< TRISE register */ 00448 I2C_Register_PECR = (uint8_t)0x0E /*!< PEC register */ 00449 } I2C_Register_TypeDef; 00450 /** 00451 * @} 00452 */ 00453 00454 /** 00455 * @} 00456 */ 00457 /* Exported constants --------------------------------------------------------*/ 00458 /** @defgroup I2C_Exported_Constants 00459 * @{ 00460 */ 00461 #define I2C_MAX_STANDARD_FREQ ((uint32_t)100000) 00462 #define I2C_MAX_FAST_FREQ ((uint32_t)400000) 00463 00464 /** 00465 *@} 00466 */ 00467 00468 /* Exported macro -----------------------------------------------------------*/ 00469 /** @defgroup I2C_Exported_Macros 00470 * @{ 00471 */ 00472 00473 /** 00474 * @brief Macro used by the assert function to check the different functions parameters. 00475 */ 00476 00477 /** 00478 * @brief Macro used by the assert function to check the different I2C modes. 00479 */ 00480 #define IS_I2C_MODE(MODE)(((MODE) == I2C_Mode_I2C) || \ 00481 ((MODE) == I2C_Mode_SMBusDevice) || \ 00482 ((MODE) == I2C_Mode_SMBusHost)) 00483 00484 /** 00485 * @brief Macro used by the assert function to check the different I2C duty cycles. 00486 */ 00487 #define IS_I2C_DUTY_CYCLE(CYCLE)(((CYCLE) == I2C_DutyCycle_2) || \ 00488 ((CYCLE) == I2C_DutyCycle_16_9)) 00489 00490 /** 00491 * @brief Macro used by the assert function to check the different acknowledgement configuration 00492 */ 00493 #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Disable) || \ 00494 ((STATE) == I2C_Ack_Enable)) 00495 /** 00496 * @brief Macro used by the assert function to check the different acknowledgement position 00497 */ 00498 #define IS_I2C_ACK_POSITION(POSITION) (((POSITION) == I2C_AckPosition_Next) || \ 00499 ((POSITION) == I2C_AckPosition_Current)) 00500 00501 /** 00502 * @brief Macro used by the assert function to check the different I2C PEC positions. 00503 */ 00504 #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Current) || \ 00505 ((POSITION) == I2C_PECPosition_Next)) 00506 00507 /** 00508 * @brief Macro used by the assert function to check the different I2C addressing modes. 00509 */ 00510 #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDMODE) (((ADDMODE) == I2C_AcknowledgedAddress_7bit) || \ 00511 ((ADDMODE) == I2C_AcknowledgedAddress_10bit)) 00512 00513 /** 00514 * @brief Macro used by the assert function to check the different I2C SMBus Alert pin configuration. 00515 */ 00516 #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_High) || \ 00517 ((ALERT) == I2C_SMBusAlert_Low)) 00518 00519 /** 00520 * @brief Macro used by the assert function to check the different I2C communication direction. 00521 */ 00522 #define IS_I2C_DIRECTION(DIR)(((DIR) == I2C_Direction_Transmitter) || \ 00523 ((DIR) == I2C_Direction_Receiver )) 00524 00525 /** 00526 * @brief Macro used by the assert function to check the different I2C flags. 00527 */ 00528 #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || \ 00529 ((FLAG) == I2C_FLAG_RXNE) || \ 00530 ((FLAG) == I2C_FLAG_STOPF) || \ 00531 ((FLAG) == I2C_FLAG_ADD10) || \ 00532 ((FLAG) == I2C_FLAG_BTF) || \ 00533 ((FLAG) == I2C_FLAG_ADDR) || \ 00534 ((FLAG) == I2C_FLAG_SB) || \ 00535 ((FLAG) == I2C_FLAG_SMBALERT) || \ 00536 ((FLAG) == I2C_FLAG_TIMEOUT) || \ 00537 ((FLAG) == I2C_FLAG_WUFH) || \ 00538 ((FLAG) == I2C_FLAG_PECERR) || \ 00539 ((FLAG) == I2C_FLAG_OVR) || \ 00540 ((FLAG) == I2C_FLAG_AF) || \ 00541 ((FLAG) == I2C_FLAG_ARLO) || \ 00542 ((FLAG) == I2C_FLAG_BERR) || \ 00543 ((FLAG) == I2C_FLAG_DUALF) || \ 00544 ((FLAG) == I2C_FLAG_SMBHOST) || \ 00545 ((FLAG) == I2C_FLAG_SMBDEFAULT) || \ 00546 ((FLAG) == I2C_FLAG_GENCALL) || \ 00547 ((FLAG) == I2C_FLAG_TRA) || \ 00548 ((FLAG) == I2C_FLAG_BUSY) || \ 00549 ((FLAG) == I2C_FLAG_MSL)) 00550 00551 /** 00552 * @brief Macro used by the assert function to check the I2C flags to clear. 00553 */ 00554 #define IS_I2C_CLEAR_FLAG(FLAG) ((((uint16_t)(FLAG) & (uint16_t)0xFD00) == 0x00) && ((uint16_t)(FLAG) != 0x00)) 00555 00556 /** 00557 * @brief Macro used by the assert_param function in order to check the different 00558 * sensitivity values for the Interrupts 00559 */ 00560 #define IS_I2C_CONFIG_IT(IT) ((((uint16_t)(IT) & (uint16_t)0xFFF8) == 0x00) && ((uint16_t)(IT) != 0x00)) 00561 00562 /** 00563 * @brief Macro used by the assert function to check the different I2C possible 00564 * pending bits to clear by writing 0. 00565 */ 00566 #define IS_I2C_CLEAR_IT(IT) ((((uint16_t)(IT) & (uint16_t)0xDC00) == 0x00) && ((uint16_t)(IT) != 0x00)) 00567 00568 /** 00569 * @brief Macro used by the assert function to check the different I2C possible pending bits. 00570 */ 00571 #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_OVR) ||\ 00572 ((IT) == I2C_IT_AF) ||\ 00573 ((IT) == I2C_IT_ARLO) ||\ 00574 ((IT) == I2C_IT_BERR) ||\ 00575 ((IT) == I2C_IT_TXE) ||\ 00576 ((IT) == I2C_IT_RXNE) ||\ 00577 ((IT) == I2C_IT_STOPF) ||\ 00578 ((IT) == I2C_IT_ADD10) ||\ 00579 ((IT) == I2C_IT_BTF) ||\ 00580 ((IT) == I2C_IT_ADDR) ||\ 00581 ((IT) == I2C_IT_PECERR) ||\ 00582 ((IT) == I2C_IT_TIMEOUT) ||\ 00583 ((IT) == I2C_IT_SMBALERT) ||\ 00584 ((IT) == I2C_IT_WUFH) ||\ 00585 ((IT) == I2C_IT_SB)) 00586 /** 00587 * @brief Macro used by the assert function to check the different I2C possible events. 00588 */ 00589 #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ 00590 ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ 00591 ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ 00592 ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ 00593 ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ 00594 ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ 00595 ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_DUALF)) || \ 00596 ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | (uint16_t)I2C_FLAG_GENCALL)) || \ 00597 ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ 00598 ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_DUALF)) || \ 00599 ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | (uint16_t)I2C_FLAG_GENCALL)) || \ 00600 ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE) || \ 00601 ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ 00602 ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ 00603 ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ 00604 ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ 00605 ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ 00606 ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ 00607 ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ 00608 ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10)) 00609 /** 00610 * @brief Macro used by the assert function to check the different I2C registers. 00611 */ 00612 #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ 00613 ((REGISTER) == I2C_Register_CR2) || \ 00614 ((REGISTER) == I2C_Register_FREQR) || \ 00615 ((REGISTER) == I2C_Register_OARL) || \ 00616 ((REGISTER) == I2C_Register_OARH) || \ 00617 ((REGISTER) == I2C_Register_DR) || \ 00618 ((REGISTER) == I2C_Register_SR1) || \ 00619 ((REGISTER) == I2C_Register_SR2) || \ 00620 ((REGISTER) == I2C_Register_SR3) || \ 00621 ((REGISTER) == I2C_Register_ITR) || \ 00622 ((REGISTER) == I2C_Register_CCRL) || \ 00623 ((REGISTER) == I2C_Register_CCRH) || \ 00624 ((REGISTER) == I2C_Register_TRISER) || \ 00625 ((REGISTER) == I2C_Register_PECR)) 00626 /** 00627 * @brief Macro used by the assert function to check the different I2C possible own address. 00628 */ 00629 #define IS_I2C_OWN_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF) 00630 00631 /** 00632 * @brief Macro used by the assert function to check the different I2C address 00633 * The address must be even 00634 */ 00635 #define IS_I2C_ADDRESS(ADD) (((ADD) & (uint8_t)0x01) == (uint8_t)0x00) 00636 00637 /** 00638 * @brief Macro used by the assert function to check that I2C Output clock frequency must be between 1Hz and 400kHz. 00639 */ 00640 #define IS_I2C_OUTPUT_CLOCK_FREQ(FREQ) (((FREQ) >= (uint8_t)1) && ((FREQ) <= I2C_MAX_FAST_FREQ)) 00641 00642 /** 00643 * @} 00644 */ 00645 00646 /* Exported functions ------------------------------------------------------- */ 00647 00648 /* Function used to set the I2C configuration to the default reset state *****/ 00649 void I2C_DeInit(I2C_TypeDef* I2Cx); 00650 00651 /* Initialization and Configuration functions *********************************/ 00652 void I2C_Init(I2C_TypeDef* I2Cx, uint32_t OutputClockFrequency, uint16_t OwnAddress, 00653 I2C_Mode_TypeDef I2C_Mode, I2C_DutyCycle_TypeDef I2C_DutyCycle, 00654 I2C_Ack_TypeDef I2C_Ack, I2C_AcknowledgedAddress_TypeDef I2C_AcknowledgedAddress); 00655 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 00656 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 00657 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 00658 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 00659 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 00660 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); 00661 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); 00662 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); 00663 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); 00664 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 00665 void I2C_AckPositionConfig(I2C_TypeDef* I2Cx, I2C_AckPosition_TypeDef I2C_AckPosition); 00666 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, I2C_DutyCycle_TypeDef I2C_DutyCycle); 00667 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, I2C_SMBusAlert_TypeDef I2C_SMBusAlert); 00668 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, I2C_Direction_TypeDef I2C_Direction); 00669 00670 /* Data transfers functions ***************************************************/ 00671 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); 00672 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); 00673 00674 /* PEC management functions ***************************************************/ 00675 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, I2C_PECPosition_TypeDef I2C_PECPosition); 00676 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); 00677 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); 00678 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); 00679 00680 /* DMA transfers management functions *****************************************/ 00681 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 00682 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 00683 00684 /* Interrupts, events and flags management functions **************************/ 00685 00686 void I2C_ITConfig(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT, FunctionalState NewState); 00687 uint8_t I2C_ReadRegister(I2C_TypeDef* I2Cx, I2C_Register_TypeDef I2C_Register); 00688 00689 /** 00690 * @brief 00691 * 00692 @verbatim 00693 ================================================================================ 00694 I2C State Monitoring Functions 00695 ================================================================================ 00696 This I2C driver provides three different ways for I2C state monitoring 00697 depending on the application requirements and constraints: 00698 00699 00700 1) Basic state monitoring: 00701 Using I2C_CheckEvent() function: 00702 It compares the status registers (SR1, SR2 and SR3) content to a given event 00703 (can be the combination of one or more flags). 00704 It returns SUCCESS if the current status includes the given flags 00705 and returns ERROR if one or more flags are missing in the current status. 00706 - When to use: 00707 - This function is suitable for most applications as well as for startup 00708 activity since the events are fully described in the product reference manual 00709 (RM0031). 00710 - It is also suitable for users who need to define their own events. 00711 - Limitations: 00712 - If an error occurs (ie. error flags are set besides to the monitored flags), 00713 the I2C_CheckEvent() function may return SUCCESS despite the communication 00714 hold or corrupted real state. 00715 In this case, it is advised to use error interrupts to monitor the error 00716 events and handle them in the interrupt IRQ handler. 00717 00718 @note 00719 For error management, it is advised to use the following functions: 00720 - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). 00721 - I2Cx_IRQHandler() which is called when the I2C interrupts occur. 00722 Where x is the peripheral instance (I2C1,...) 00723 - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the 00724 I2Cx_IRQHandler() function in order to determine which error occurred. 00725 - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 00726 and/or I2C_GenerateStop() in order to clear the error flag and 00727 source and return to correct communication status. 00728 00729 00730 2) Advanced state monitoring: 00731 Using the function I2C_GetLastEvent() which returns the image of both SR1 00732 & SR3 status registers in a single word (uint16_t) (Status Register 3 value 00733 is shifted left by 8 bits and concatenated to Status Register 1). 00734 - When to use: 00735 - This function is suitable for the same applications above but it allows to 00736 overcome the limitations of I2C_GetFlagStatus() function (see below). 00737 The returned value could be compared to events already defined in the 00738 library (stm8l15x_i2c.h) or to custom values defined by user. 00739 - This function is suitable when multiple flags are monitored at the same time. 00740 - At the opposite of I2C_CheckEvent() function, this function allows user to 00741 choose when an event is accepted (when all events flags are set and no 00742 other flags are set or just when the needed flags are set like 00743 I2C_CheckEvent() function). 00744 - Limitations: 00745 - User may need to define his own events. 00746 - Same remark concerning the error management is applicable for this 00747 function if user decides to check only regular communication flags (and 00748 ignores error flags). 00749 00750 00751 3) Flag-based state monitoring: 00752 Using the function I2C_GetFlagStatus() which simply returns the status of 00753 one single flag (ie. I2C_FLAG_RXNE ...). 00754 - When to use: 00755 - This function could be used for specific applications or in debug phase. 00756 - It is suitable when only one flag checking is needed (most I2C events 00757 are monitored through multiple flags). 00758 - Limitations: 00759 - When calling this function, the Status register is accessed. Some flags are 00760 cleared when the status register is accessed. So checking the status 00761 of one Flag, may clear other ones. 00762 - Function may need to be called twice or more in order to monitor one 00763 single event. 00764 00765 00766 @endverbatim 00767 * 00768 */ 00769 00770 /** 00771 =============================================================================== 00772 1. Basic state monitoring 00773 =============================================================================== 00774 */ 00775 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, I2C_Event_TypeDef I2C_Event); 00776 /** 00777 =============================================================================== 00778 2. Advanced state monitoring 00779 =============================================================================== 00780 */ 00781 I2C_Event_TypeDef I2C_GetLastEvent(I2C_TypeDef* I2Cx); 00782 /** 00783 =============================================================================== 00784 3. Flag-based state monitoring 00785 =============================================================================== 00786 */ 00787 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, I2C_FLAG_TypeDef I2C_FLAG); 00788 00789 void I2C_ClearFlag(I2C_TypeDef* I2Cx, I2C_FLAG_TypeDef I2C_FLAG); 00790 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT); 00791 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, I2C_IT_TypeDef I2C_IT); 00792 00793 #endif /* __STM8L15x_I2C_H */ 00794 00795 /** 00796 * @} 00797 */ 00798 00799 /** 00800 * @} 00801 */ 00802 00803 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/