NI-TClk
Synchronization in Multiple PXI Chassis
If devices are in multiple PXI chassis, the Sync Pulse signal is not automatically routed, and you must configure the system so that all of the PXI_CLK10 signals in all of the chassis are driven from the same clock source.
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Note To minimize phase differences between the chassis, use matched-length cables to drive PXI_CLK10 to the different chassis. |
Routing the Triggers
When you synchronize several NI modular instruments in multiple PXI chassis with homogeneous or heterogeneous triggers, use the instrument driver VIs or functions to route the triggers so that the triggers can be shared. Also, use the following NI-TClk VIs or functions:
| LabVIEW VI | C Function |
|---|---|
| niTClk Synchronize VI | niTClk_Synchronize |
| niTClk Initiate VI | niTClk_Initiate |
| (optional) niTClk Is Done VI or niTClk Wait Until Done VI |
(optional) niTClk_IsDone or niTClk_WaitUntilDone |
| N/A | niTClk_GetExtendedErrorInfo |
Also, use the NI-TClk properties or attributes listed in the following table to specify how the triggers are shared between devices.
When the sample clock rates, sample clock timebase rates, and/or the sample counts are different in acquisition sessions sharing the reference trigger, you should also set the holdoff attributes for the reference trigger master using the instrument driver.
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Note To get synchronous triggers, set only the master session (the first session by default) to use a software trigger. Sending a trigger to each device individually may not keep the devices in sync. |
Routing the Sync Pulse Signal
To route the Sync Pulse signal in a multiple chassis system, use PXI synchronization modules, such as the NI PXI-6653, in each chassis. If you install these modules in Slot 2, you can conveniently use them to supply a common 10 MHz clock signal to all the chassis.
Use the following NI-TClk properties or attributes to specify the routing of the Sync Pulse signal:
| LabVIEW Property | C Attribute |
|---|---|
| Sync Pulse Source | NITCLK_ATTR_SYNC_PULSE_SOURCE |
| Export Sync Pulse Output Terminal | NITCLK_ATTR_EXPORTED_SYNC_PULSE_OUTPUT_TERMINAL |
Example
For example, if chassis A contains the device that is exporting the Sync Pulse signal, and chassis A is connected through the PXI synchronization modules and cables to chassis B and chassis C, then the following signal routing is recommended:
- Route the Sync Pulse signal from the device that is exporting this signal to the PXI synchronization module using a PXI trigger line (line X).
- Resynchronize to PXI_CLK10 in the PXI synchronization module and route the Sync Pulse signal to the following locations:
- Another PXI trigger line (line Y) in the same chassis (where line Y is different from line X)
- The PXI synchronization modules in chassis B and chassis C
- Program the devices in chassis A to receive the signal from the PXI trigger line Y.
- Route the Sync Pulse signal—without resynchronizing—from the PXI synchronization module on chassis B and chassis C to the PXI trigger line Y on chassis B and chassis C.
- Program the devices in chassis B and chassis C to receive the Sync Pulse signal from PXI trigger line Y.
If PXI trigger line Y is not available in chassis B and chassis C, you can use any other available line. Using the same line in all chassis simplifies programming.
When using this configuration, keep the total signal propagation delay of the cables and the PXI synchronization modules to less than 100 ns.
For more information about synchronizing multiple PXI chassis, contact National Instruments technical support. For information on 18-slot PXI chassis, refer to Configuring PXI Chassis with Multiple Bus Segments (18-Slot Chassis).