Block Diagram Tests (VI Analyzer Toolkit)

Note  The VI Analyzer tests are available only if you install and activate the LabVIEW VI Analyzer Toolkit. Refer to the National Instruments Web site for more information about the VI Analyzer Toolkit.

Tests in the Block Diagram category of VI Analyzer tests analyze VI performance and style related to the block diagram. The VI Analyzer groups the Block Diagram tests into three subcategories: Performance, Style, and Warnings.

Performance

The tests in the following list analyze coding conventions that affect VI performance.

• Arrays and Strings in Loops—Checks loops to see if they contain Build Array or Concatenate Strings functions. Avoid using these functions in loops because each call to them requires a dynamic resizing of the array or string, which can affect memory and processor time. This test does not check timed loops.
• Coercion Dots—Checks the total number of coercion dots on the block diagram and the number of coercion dots on individual wires and compares them to user-specified limits.
• Enabled Debugging—Checks whether debugging is enabled or disabled. Disabling debugging improves VI performance.
• Wait in While Loop—Checks While Loops with front panel control terminals for structures or functions other than I/O functions that regulate the speed of the While Loop.
• Wired Terminals in Subdiagrams—Checks to see if any control or indicator that is wired on the connector pane does not reside within the top-level diagram. In order to avoid unnecessary memory copies, place control and indicator terminals that are wired on the connector pane should be placed on the top-level diagram.

Style

The tests in the following list analyze block diagrams for issues related to LabVIEW style. Refer to the LabVIEW Style Checklist for information about LabVIEW style.

• Backwards Wires—Checks whether wires flow from left to right.
• Control Terminal Label Visible—Checks if labels of block diagram control terminals are visible. To easily identify control terminals on the block diagram, always make labels visible.
• Control Terminal Wiring—Checks whether wires exit control terminals from the right side and enter indicator terminals on the left side.
• Sequence Structure Usage—Checks whether the block diagram includes Stacked Sequence structures that contain more than the user-specified maximum number of frames. The test does not check Flat Sequence structures.
• String Constant Style—Checks the style of string constants on the block diagram. String constants containing no characters fail the test. Replace them with an empty string constant. String constants set to Normal Display that contain only white space—such as spaces, tabs, or line feeds—fail the test. Set the constants to '\' Codes Display to improve block diagram readability.
• Unused Code—Checks for unnecessary code on the block diagram.
• Wire Bends—Compares the total number of bends on a wire to a user-specified maximum and compares the length of each wire segment to a user-specified minimum.
• Wires Under Objects—Checks for wires that run under objects or other wires.

Warnings

The tests in the following list analyze block diagrams for potential design problems.

• Adding Array Size Elements—Checks whether the Add Array Elements function connects to the output of the Array Size function to determine the size of a multidimensional array. Wire the Multiply Array Elements function to the size(s) output of the Array Size function to determine whether a multidimensional array is empty.
• Breakpoint Detection—Checks for breakpoints on the block diagram, including breakpoints on wires, nodes, and subdiagrams.
• Bundling Duplicate Names—Checks element names in the Bundle By Name and Unbundle By Name functions for duplicates. Duplicate elements can cause confusing and sometimes incorrect block diagram behavior.
• Error Cluster Wired—Checks that the error output on a block diagram node is wired. You can set the test to ignore VIs with automatic error handling disabled. You also can ignore nodes that usually have unwired error outputs.
• For Loop Iteration Count—Checks For Loops to ensure that the VI does not use both auto-indexing arrays and the N terminal to govern the number of iterations the For Loop runs. You also can check for multiple auto-indexing arrays governing the iteration count.
• Globals and Locals—Checks whether a block diagram contains global and local variables.
• Hidden Objects in Structures—Checks whether any objects in structures are hidden outside the visible bounds of the structure.
• Hidden Tunnels—Checks tunnels, shift registers, and other structure border elements to see if they overlap each other. Overlapping tunnels can make your block diagram difficult to read. The test currently does not check dynamic event tunnels, tunnels on Timed Loops with frames, or tunnels on Timed Sequence Structures.
• Indexer Datatype—Checks functions that index array elements and string characters to ensure that signed or unsigned 8-bit or 16-bit integer data types do not index string or array elements. The test ignores functions that use constants for indexing.
• Pattern Label—Checks whether a file dialog box that uses file patterns specifies a pattern label. The items you can check are the File Dialog Express VI and the browse options on a path control.
• Reentrant VI Issues—Checks for uninitialized shift registers and non-reentrant subVIs in a reentrant VI. Because reentrant VIs maintain multiple data spaces, unexpected results can occur when using uninitialized shift registers. Additionally, parallelism could be inhibited if the reentrant VI calls non-reentrant subVIs.
• Typedef Cluster Constants—Checks cluster constants on the block diagram that are linked to type definition controls to determine whether their values match the default value of the type definition control. If a constant has a non-default value and the structure of the type definition changes, the value of the constant might reset. Use the Bundle By Name function to change the value of any elements inside a cluster constant linked to a type definition control.