FSP_S_CONFIG Struct Reference

Fsp S Configuration. More...

#include <FspsUpd.h>

Public Attributes
UINT32	LogoPtr
	Offset 0x0020 - Logo Pointer Points to PEI Display Logo Image.
UINT32	LogoSize
	Offset 0x0024 - Logo Size Size of PEI Display Logo Image.
UINT32	GraphicsConfigPtr
	Offset 0x0028 - Graphics Configuration Ptr Points to VBT.
UINT8	Device4Enable
	Offset 0x002C - Enable Device 4 Enable/disable Device 4 $EN_DIS.
UINT8	PchHdaEnable
	Offset 0x002D - Enable Intel HD Audio (Azalia) Enable/disable Azalia controller. More...
UINT8	PchHdaDspEnable
	Offset 0x002E - Enable HD Audio DSP Enable/disable HD Audio DSP feature. More...
UINT8	PchHdaIoBufferOwnership
	Offset 0x002F - Select HDAudio IoBuffer Ownership Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port. More...
UINT8	PchCio2Enable
	Offset 0x0030 - Enable CIO2 Controller Enable/disable SKYCAM CIO2 Controller. More...
UINT8	ScsEmmcEnabled
	Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller. More...
UINT8	ScsEmmcHs400Enabled
	Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode. More...
UINT8	ScsSdCardEnabled
	Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller. More...
UINT8	PchIshEnable
	Offset 0x0034 - Enable PCH ISH Controller Enable/disable ISH Controller. More...
UINT8	ShowSpiController
	Offset 0x0035 - Show SPI controller Enable/disable to show SPI controller. More...
UINT8	SpiFlashCfgLockDown
	Offset 0x0036 - Flash Configuration Lock Down Enable/disable flash lock down. More...
UINT8	UnusedUpdSpace0
	Offset 0x0037.
UINT32	MicrocodeRegionBase
	Offset 0x0038 - MicrocodeRegionBase Memory Base of Microcode Updates.
UINT32	MicrocodeRegionSize
	Offset 0x003C - MicrocodeRegionSize Size of Microcode Updates.
UINT8	TurboMode
	Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode. More...
UINT8	SataSalpSupport
	Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. More...
UINT8	SataPortsEnable [8]
	Offset 0x0042 - Enable SATA ports Enable/disable SATA ports. More...
UINT8	SataPortsDevSlp [8]
	Offset 0x004A - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. More...
UINT8	PortUsb20Enable [16]
	Offset 0x0052 - Enable USB2 ports Enable/disable per USB2 ports. More...
UINT8	PortUsb30Enable [10]
	Offset 0x0062 - Enable USB3 ports Enable/disable per USB3 ports. More...
UINT8	XdciEnable
	Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller. More...
UINT8	SsicPortEnable
	Offset 0x006D - Enable XHCI SSIC Enable Enable/disable XHCI SSIC port. More...
UINT8	UnusedUpdSpace1
	Offset 0x006E.
UINT8	NumOfDevIntConfig
	Offset 0x006F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. More...
UINT32	DevIntConfigPtr
	Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. More...
UINT8	SerialIoDevMode [11]
	Offset 0x0074 - Enable SerialIo Device Mode 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode respectively. More...
UINT8	PxRcConfig [8]
	Offset 0x007F - PIRQx to IRQx Map Config PIRQx to IRQx mapping. More...
UINT8	GpioIrqRoute
	Offset 0x0087 - Select GPIO IRQ Route GPIO IRQ Select. More...
UINT8	SciIrqSelect
	Offset 0x0088 - Select SciIrqSelect SCI IRQ Select. More...
UINT8	TcoIrqSelect
	Offset 0x0089 - Select TcoIrqSelect TCO IRQ Select. More...
UINT8	TcoIrqEnable
	Offset 0x008A - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS.
UINT8	PchHdaVerbTableEntryNum
	Offset 0x008B - PCH HDA Verb Table Entry Number Number of Entries in Verb Table.
UINT32	PchHdaVerbTablePtr
	Offset 0x008C - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table.
UINT8	UnusedUpdSpace2
	Offset 0x0090.
UINT8	SataEnable
	Offset 0x0091 - Enable SATA Enable/disable SATA controller. More...
UINT8	SataMode
	Offset 0x0092 - SATA Mode Select SATA controller working mode. More...
UINT8	Usb2AfePetxiset [16]
	Offset 0x0093 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. More...
UINT8	Usb2AfeTxiset [16]
	Offset 0x00A3 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. More...
UINT8	Usb2AfePredeemp [16]
	Offset 0x00B3 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. More...
UINT8	Usb2AfePehalfbit [16]
	Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. More...
UINT8	Usb3HsioTxDeEmphEnable [10]
	Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. More...
UINT8	Usb3HsioTxDeEmph [10]
	Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). More...
UINT8	Usb3HsioTxDownscaleAmpEnable [10]
	Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. More...
UINT8	Usb3HsioTxDownscaleAmp [10]
	Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. More...
UINT8	PchLanEnable
	Offset 0x00FB - Enable LAN Enable/disable LAN controller. More...
UINT8	DelayUsbPdoProgramming
	Offset 0x00FC - Delay USB PDO Programming Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. More...
UINT8	UnusedUpdSpace3 [23]
	Offset 0x00FD.
UINT8	PcieRpClkReqSupport [24]
	Offset 0x0114 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support. More...
UINT8	PcieRpClkReqNumber [24]
	Offset 0x012C - Configure CLKREQ Number Configure Root Port CLKREQ Number if CLKREQ is supported. More...
UINT8	UnusedUpdSpace4 [5]
	Offset 0x0144.
UINT8	Heci3Enabled
	Offset 0x0149 - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. More...
UINT8	UnusedUpdSpace5 [9]
	Offset 0x014A.
UINT8	AmtEnabled
	Offset 0x0153 - AMT Switch Enable/Disable. More...
UINT8	WatchDog
	Offset 0x0154 - WatchDog Timer Switch Enable/Disable. More...
UINT8	AsfEnabled
	Offset 0x0155 - ASF Switch Enable/Disable. More...
UINT8	ManageabilityMode
	Offset 0x0156 - Manageability Mode set by Mebx Enable/Disable. More...
UINT8	FwProgress
	Offset 0x0157 - PET Progress Enable/Disable. More...
UINT16	WatchDogTimerOs
	Offset 0x0158 - OS Timer 16 bits Value, Set OS watchdog timer. More...
UINT16	WatchDogTimerBios
	Offset 0x015A - BIOS Timer 16 bits Value, Set BIOS watchdog timer. More...
UINT8	AmtSolEnabled
	Offset 0x015C - SOL Switch Enable/Disable. More...
UINT8	PcieRpClkSrcNumber [24]
	Offset 0x015D - Configure CLKSRC Number Configure Root Port CLKSRC Number. More...
UINT8	UnusedUpdSpace6 [139]
	Offset 0x0175.
UINT16	DefaultSvid
	Offset 0x0200 - Subsystem Vendor ID for SA devices Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086.
UINT16	DefaultSid
	Offset 0x0202 - Subsystem Device ID for SA devices Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015.
UINT8	CridEnable
	Offset 0x0204 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS.
UINT8	DmiAspm
	Offset 0x0205 - DMI ASPM 0=Disable, 2(Default)=L1 0:Disable, 2:L1.
UINT16	PegPhysicalSlotNumber [3]
	Offset 0x0206 - PCIe Physical Slot Number per root port Physical Slot Number per root port.
UINT8	PegDeEmphasis [3]
	Offset 0x020C - PCIe DeEmphasis control per root port 0: -6dB, 1(Default): -3.5dB 0:-6dB, 1:-3.5dB.
UINT8	PegSlotPowerLimitValue [3]
	Offset 0x020F - PCIe Slot Power Limit value per root port Slot power limit value per root port.
UINT8	PegSlotPowerLimitScale [3]
	Offset 0x0212 - PCIe Slot Power Limit scale per root port Slot power limit scale per root port 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x.
UINT8	PavpEnable
	Offset 0x0215 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS.
UINT8	CdClock
	Offset 0x0216 - CdClock Frequency selection 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)= 675 Mhz 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz.
UINT8	PeiGraphicsPeimInit
	Offset 0x0217 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS.
UINT8	SaImguEnable
	Offset 0x0218 - Enable/Disable SA IMGU(SKYCAM) Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM) $EN_DIS.
UINT8	GmmEnable
	Offset 0x0219 - Enable or disable GMM device 0=Disable, 1(Default)=Enable $EN_DIS.
UINT8	X2ApicOptOut
	Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS.
UINT8	UnusedUpdSpace7 [1]
	Offset 0x021B.
UINT32	VtdBaseAddress [2]
	Offset 0x021C - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine.
UINT8	UnusedUpdSpace8 [19]
	Offset 0x0224.
UINT8	SaPostMemProductionRsvd [16]
	Offset 0x0237 - SaPostMemProductionRsvd Reserved for SA Post-Mem Production $EN_DIS.
UINT8	UnusedUpdSpace9 [7]
	Offset 0x0247.
UINT8	Psi3Enable [5]
	Offset 0x024E - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. More...
UINT8	Psi4Enable [5]
	Offset 0x0253 - Power State 4 enable/disable PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes.
UINT8	ImonSlope [5]
	Offset 0x0258 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. More...
UINT8	ImonOffset [5]
	Offset 0x025D - Imon offset correction PCODE MMIO Mailbox: Imon offset correction. More...
UINT8	VrConfigEnable [5]
	Offset 0x0262 - Enable/Disable BIOS configuration of VR Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes.
UINT8	TdcEnable [5]
	Offset 0x0267 - Thermal Design Current enable/disable PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes.
UINT8	TdcTimeWindow [5]
	Offset 0x026C - HECI3 state PCODE MMIO Mailbox: Thermal Design Current time window. More...
UINT8	TdcLock [5]
	Offset 0x0271 - Thermal Design Current Lock PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes.
UINT8	PsysSlope
	Offset 0x0276 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction. More...
UINT8	PsysOffset
	Offset 0x0277 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction. More...
UINT8	AcousticNoiseMitigation
	Offset 0x0278 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature. More...
UINT8	FastPkgCRampDisableIa
	Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
UINT8	SlowSlewRateForIa
	Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. More...
UINT8	SlowSlewRateForGt
	Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. More...
UINT8	SlowSlewRateForSa
	Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. More...
UINT8	UnusedUpdSpace10 [9]
	Offset 0x027D.
UINT16	TdcPowerLimit [5]
	Offset 0x0286 - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit. More...
UINT32	VrPowerDeliveryDesign
	Offset 0x0290 - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. More...
UINT8	UnusedUpdSpace11 [4]
	Offset 0x0294.
UINT16	AcLoadline [5]
	Offset 0x0298 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. More...
UINT16	DcLoadline [5]
	Offset 0x02A2 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. More...
UINT16	Psi1Threshold [5]
	Offset 0x02AC - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. More...
UINT16	Psi2Threshold [5]
	Offset 0x02B6 - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. More...
UINT16	Psi3Threshold [5]
	Offset 0x02C0 - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. More...
UINT16	IccMax [5]
	Offset 0x02CA - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit. More...
UINT16	VrVoltageLimit [5]
	Offset 0x02D4 - VR Voltage Limit PCODE MMIO Mailbox: VR Voltage Limit. More...
UINT8	UnusedUpdSpace12
	Offset 0x02DE.
UINT8	FastPkgCRampDisableGt
	Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
UINT8	FastPkgCRampDisableSa
	Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
UINT8	UnusedUpdSpace13
	Offset 0x02E1.
UINT8	SendVrMbxCmd
	Offset 0x02E2 - Enable VR specific mailbox command VR specific mailbox commands. More...
UINT8	SendVrMbxCmd1
	Offset 0x02E3 - Select VR specific mailbox command to send VR specific mailbox commands. More...
UINT32	CpuS3ResumeMtrrData
	Offset 0x02E4 - CpuS3ResumeMtrrData Pointer to CPU S3 Resume MTRR Data.
CPU_CONFIG_FSP_DATA	CpuConfig
	Offset 0x02E8 - Cpu Configuration Cpu Configuration data.
UINT64	MicrocodePatchAddress
	Offset 0x02F0 - MicrocodePatchAddress Pointer to microcode patch that is suitable for this processor. More...
UINT16	CpuS3ResumeMtrrDataSize
	Offset 0x02F8 - CpuS3ResumeMtrrDataSize Size of S3 resume MTRR data.
UINT8	UnusedUpdSpace14
	Offset 0x02FA.
UINT8	PchSkyCamPortATermOvrEnable
	Offset 0x02FB - Enable SkyCam PortA Termination override Enable/disable PortA Termination override. More...
UINT8	PchSkyCamPortBTermOvrEnable
	Offset 0x02FC - Enable SkyCam PortB Termination override Enable/disable PortB Termination override. More...
UINT8	PchSkyCamPortCTermOvrEnable
	Offset 0x02FD - Enable SkyCam PortC Termination override Enable/disable PortC Termination override. More...
UINT8	PchSkyCamPortDTermOvrEnable
	Offset 0x02FE - Enable SkyCam PortD Termination override Enable/disable PortD Termination override. More...
UINT8	PchSkyCamPortATrimEnable
	Offset 0x02FF - Enable SkyCam PortA Clk Trim Enable/disable PortA Clk Trim. More...
UINT8	PchSkyCamPortBTrimEnable
	Offset 0x0300 - Enable SkyCam PortB Clk Trim Enable/disable PortB Clk Trim. More...
UINT8	PchSkyCamPortCTrimEnable
	Offset 0x0301 - Enable SkyCam PortC Clk Trim Enable/disable PortC Clk Trim. More...
UINT8	PchSkyCamPortDTrimEnable
	Offset 0x0302 - Enable SkyCam PortD Clk Trim Enable/disable PortD Clk Trim. More...
UINT8	PchSkyCamPortACtleEnable
	Offset 0x0303 - Enable SkyCam PortA Ctle Enable/disable PortA Ctle. More...
UINT8	PchSkyCamPortBCtleEnable
	Offset 0x0304 - Enable SkyCam PortB Ctle Enable/disable PortB Ctle. More...
UINT8	PchSkyCamPortCDCtleEnable
	Offset 0x0305 - Enable SkyCam PortCD Ctle Enable/disable PortCD Ctle. More...
UINT8	PchSkyCamPortACtleCapValue
	Offset 0x0306 - Enable SkyCam PortA Ctle Cap Value Enable/disable PortA Ctle Cap Value.
UINT8	PchSkyCamPortBCtleCapValue
	Offset 0x0307 - Enable SkyCam PortB Ctle Cap Value Enable/disable PortB Ctle Cap Value.
UINT8	PchSkyCamPortCDCtleCapValue
	Offset 0x0308 - Enable SkyCam PortCD Ctle Cap Value Enable/disable PortCD Ctle Cap Value.
UINT8	PchSkyCamPortACtleResValue
	Offset 0x0309 - Enable SkyCam PortA Ctle Res Value Enable/disable PortA Ctle Res Value.
UINT8	PchSkyCamPortBCtleResValue
	Offset 0x030A - Enable SkyCam PortB Ctle Res Value Enable/disable PortB Ctle Res Value.
UINT8	PchSkyCamPortCDCtleResValue
	Offset 0x030B - Enable SkyCam PortCD Ctle Res Value Enable/disable PortCD Ctle Res Value.
UINT8	PchSkyCamPortAClkTrimValue
	Offset 0x030C - Enable SkyCam PortA Clk Trim Value Enable/disable PortA Clk Trim Value.
UINT8	PchSkyCamPortBClkTrimValue
	Offset 0x030D - Enable SkyCam PortB Clk Trim Value Enable/disable PortB Clk Trim Value.
UINT8	PchSkyCamPortCClkTrimValue
	Offset 0x030E - Enable SkyCam PortC Clk Trim Value Enable/disable PortC Clk Trim Value.
UINT8	PchSkyCamPortDClkTrimValue
	Offset 0x030F - Enable SkyCam PortD Clk Trim Value Enable/disable PortD Clk Trim Value.
UINT16	PchSkyCamPortADataTrimValue
	Offset 0x0310 - Enable SkyCam Port A Data Trim Value Enable/disable Port A Data Trim Value.
UINT16	PchSkyCamPortBDataTrimValue
	Offset 0x0312 - Enable SkyCam Port B Data Trim Value Enable/disable Port B Data Trim Value.
UINT16	PchSkyCamPortCDDataTrimValue
	Offset 0x0314 - Enable SkyCam C/D Data Trim Value Enable/disable C/D Data Trim Value.
UINT8	PchDmiAspm
	Offset 0x0316 - Enable DMI ASPM ASPM on PCH side of the DMI Link. More...
UINT8	PchPwrOptEnable
	Offset 0x0317 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. More...
UINT8	PchWriteProtectionEnable [5]
	Offset 0x0318 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware.
UINT8	PchReadProtectionEnable [5]
	Offset 0x031D - PCH Flash Protection Ranges Read Enble Read is blocked by hardware.
UINT16	PchProtectedRangeLimit [5]
	Offset 0x0322 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison.
UINT16	PchProtectedRangeBase [5]
	Offset 0x032C - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
UINT8	PchHdaPme
	Offset 0x0336 - Enable Pme Enable Azalia wake-on-ring. More...
UINT8	PchHdaIoBufferVoltage
	Offset 0x0337 - IO Buffer Voltage I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V.
UINT8	PchHdaVcType
	Offset 0x0338 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1.
UINT8	PchHdaLinkFrequency
	Offset 0x0339 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz.
UINT8	PchHdaIDispLinkFrequency
	Offset 0x033A - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
UINT8	PchHdaIDispLinkTmode
	Offset 0x033B - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
UINT8	PchHdaDspUaaCompliance
	Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). More...
UINT8	PchHdaIDispCodecDisconnect
	Offset 0x033D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. More...
UINT8	PchHdaDspEndpointDmic
	Offset 0x033E - DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum) 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array.
UINT8	PchHdaDspEndpointBluetooth
	Offset 0x033F - DSP Bluetooth enablement 0: Disable; 1: Enable. More...
UINT32	PchHdaDspFeatureMask
	Offset 0x0340 - Bitmask of supported DSP features [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6]. More...
UINT32	PchHdaDspPpModuleMask
	Offset 0x0344 - Bitmask of supported DSP Pre/Post-Processing Modules Deprecated: Specific pre/post-processing module bit position must be coherent with the ACPI implementation: _SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Support.
UINT8	PchHdaDspEndpointI2s
	Offset 0x0348 - DSP I2S enablement 0: Disable; 1: Enable. More...
UINT8	PchIoApicBdfValid
	Offset 0x0349 - Enable PCH Io Apic Set to 1 if BDF value is valid. More...
UINT8	PchIoApicBusNumber
	Offset 0x034A - PCH Io Apic Bus Number Bus/Device/Function used as Requestor / Completer ID. More...
UINT8	PchIoApicDeviceNumber
	Offset 0x034B - PCH Io Apic Device Number Bus/Device/Function used as Requestor / Completer ID. More...
UINT8	PchIoApicFunctionNumber
	Offset 0x034C - PCH Io Apic Function Number Bus/Device/Function used as Requestor / Completer ID. More...
UINT8	PchIoApicEntry24_119
	Offset 0x034D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. More...
UINT8	PchIoApicId
	Offset 0x034E - PCH Io Apic ID This member determines IOAPIC ID. More...
UINT8	PchIoApicRangeSelect
	Offset 0x034F - PCH Io Apic Range Select Define address bits 19:12 for the IOxAPIC range. More...
UINT8	PchIshSpiGpioAssign
	Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8	PchIshUart0GpioAssign
	Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8	PchIshUart1GpioAssign
	Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8	PchIshI2c0GpioAssign
	Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8	PchIshI2c1GpioAssign
	Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8	PchIshI2c2GpioAssign
	Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable. More...
UINT8	PchIshGp0GpioAssign
	Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8	PchIshGp1GpioAssign
	Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8	PchIshGp2GpioAssign
	Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8	PchIshGp3GpioAssign
	Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8	PchIshGp4GpioAssign
	Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8	PchIshGp5GpioAssign
	Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8	PchIshGp6GpioAssign
	Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8	PchIshGp7GpioAssign
	Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable. More...
UINT8	PchIshPdtUnlock
	Offset 0x035E - PCH ISH PDT Unlock Msg 0: False; 1: True. More...
UINT8	PchLanLtrEnable
	Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. More...
UINT8	PchLanK1OffEnable
	Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management 0: Disable; 1: Enable. More...
UINT8	PchLanClkReqSupported
	Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported 0: Disable; 1: Enable. More...
UINT8	PchLanClkReqNumber
	Offset 0x0362 - CLKREQ# used by GbE Valid if ClkReqSupported is TRUE.
UINT8	PchLockDownBiosLock
	Offset 0x0363 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. More...
UINT8	PchLockDownSpiEiss
	Offset 0x0364 - Enable LOCKDOWN SPI Eiss Enable InSMM.STS (EISS) in SPI. More...
UINT8	PchCrid
	Offset 0x0365 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. More...
UINT16	PchSubSystemVendorId
	Offset 0x0366 - PCH Sub system vendor ID Default Subsystem Vendor ID of the PCH devices. More...
UINT16	PchSubSystemId
	Offset 0x0368 - PCH Sub system ID Default Subsystem ID of the PCH devices. More...
UINT8	PchLegacyIoLowLatency
	Offset 0x036A - PCH Legacy IO Low Latency Enable todo $EN_DIS.
UINT8	UnusedUpdSpace15 [5]
	Offset 0x036B.
UINT8	PcieRpHotPlug [24]
	Offset 0x0370 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available.
UINT8	PcieRpPmSci [24]
	Offset 0x0388 - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled.
UINT8	PcieRpExtSync [24]
	Offset 0x03A0 - Enable PCIE RP Ext Sync Indicate whether the extended synch is enabled.
UINT8	PcieRpTransmitterHalfSwing [24]
	Offset 0x03B8 - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled.
UINT8	PcieRpClkReqDetect [24]
	Offset 0x03D0 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management.
UINT8	PcieRpAdvancedErrorReporting [24]
	Offset 0x03E8 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled.
UINT8	PcieRpUnsupportedRequestReport [24]
	Offset 0x0400 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled.
UINT8	PcieRpFatalErrorReport [24]
	Offset 0x0418 - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled.
UINT8	PcieRpNoFatalErrorReport [24]
	Offset 0x0430 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled.
UINT8	PcieRpCorrectableErrorReport [24]
	Offset 0x0448 - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled.
UINT8	PcieRpSystemErrorOnFatalError [24]
	Offset 0x0460 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled.
UINT8	PcieRpSystemErrorOnNonFatalError [24]
	Offset 0x0478 - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled.
UINT8	PcieRpSystemErrorOnCorrectableError [24]
	Offset 0x0490 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled.
UINT8	PcieRpMaxPayload [24]
	Offset 0x04A8 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
UINT8	PcieRpDeviceResetPadActiveHigh [24]
	Offset 0x04C0 - PCIE RP Device Reset Pad Active High Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad.
UINT8	PcieRpPcieSpeed [24]
	Offset 0x04D8 - PCIE RP Pcie Speed Determines each PCIE Port speed capability. More...
UINT8	PcieRpGen3EqPh3Method [24]
	Offset 0x04F0 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). More...
UINT8	PcieRpPhysicalSlotNumber [24]
	Offset 0x0508 - PCIE RP Physical Slot Number Indicates the slot number for the root port. More...
UINT8	PcieRpCompletionTimeout [24]
	Offset 0x0520 - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). More...
UINT32	PcieRpDeviceResetPad [24]
	Offset 0x0538 - PCIE RP Device Reset Pad The PCH pin assigned to device PERST# signal if available, zero otherwise. More...
UINT8	PcieRpAspm [24]
	Offset 0x0598 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). More...
UINT8	PcieRpL1Substates [24]
	Offset 0x05B0 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). More...
UINT8	PcieRpLtrEnable [24]
	Offset 0x05C8 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism.
UINT8	PcieRpLtrConfigLock [24]
	Offset 0x05E0 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable.
UINT8	PcieEqPh3LaneParamCm [24]
	Offset 0x05F8 - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM. More...
UINT8	PcieEqPh3LaneParamCp [24]
	Offset 0x0610 - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM. More...
UINT8	PcieSwEqCoeffListCm [5]
	Offset 0x0628 - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM. More...
UINT8	PcieSwEqCoeffListCp [5]
	Offset 0x062D - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM. More...
UINT8	PcieDisableRootPortClockGating
	Offset 0x0632 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. More...
UINT8	PcieEnablePeerMemoryWrite
	Offset 0x0633 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. More...
UINT8	PcieAllowNoLtrIccPllShutdown
	Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable or leaving untouched. More...
UINT8	PcieComplianceTestMode
	Offset 0x0635 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. More...
UINT16	PcieDetectTimeoutMs
	Offset 0x0636 - PCIE Rp Detect Timeout Ms Will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.
UINT8	PcieRpFunctionSwap
	Offset 0x0638 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. More...
UINT8	PchPmPmeB0S5Dis
	Offset 0x0639 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. More...
UINT8	PchPmSlpS0VmEnable
	Offset 0x063A - PCH Pm Slp S0 Voltage Margining Enable Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state. More...
UINT8	UnusedUpdSpace16 [5]
	Offset 0x063B.
UINT8	PchPmWolEnableOverride
	Offset 0x0640 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. More...
UINT8	PchPmPcieWakeFromDeepSx
	Offset 0x0641 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. More...
UINT8	PchPmWoWlanEnable
	Offset 0x0642 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. More...
UINT8	PchPmWoWlanDeepSxEnable
	Offset 0x0643 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. More...
UINT8	PchPmLanWakeFromDeepSx
	Offset 0x0644 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. More...
UINT8	PchPmDeepSxPol
	Offset 0x0645 - PCH Pm Deep Sx Pol Deep Sx Policy. More...
UINT8	PchPmSlpS3MinAssert
	Offset 0x0646 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. More...
UINT8	PchPmSlpS4MinAssert
	Offset 0x0647 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. More...
UINT8	PchPmSlpSusMinAssert
	Offset 0x0648 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. More...
UINT8	PchPmSlpAMinAssert
	Offset 0x0649 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. More...
UINT8	UnusedUpdSpace17 [6]
	Offset 0x064A.
UINT8	PchPmLpcClockRun
	Offset 0x0650 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled. More...
UINT8	PchPmSlpStrchSusUp
	Offset 0x0651 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. More...
UINT8	PchPmSlpLanLowDc
	Offset 0x0652 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. More...
UINT8	PchPmPwrBtnOverridePeriod
	Offset 0x0653 - PCH Pm Pwr Btn Override Period PCH power button override period. More...
UINT8	PchPmDisableDsxAcPresentPulldown
	Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. More...
UINT8	PchPmCapsuleResetType
	Offset 0x0655 - PCH Pm Capsule Reset Type Deprecated: Determines type of reset issued during UpdateCapsule(). More...
UINT8	PchPmDisableNativePowerButton
	Offset 0x0656 - PCH Pm Disable Native Power Button Power button native mode disable. More...
UINT8	PchPmSlpS0Enable
	Offset 0x0657 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. More...
UINT8	PchPmMeWakeSts
	Offset 0x0658 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. More...
UINT8	PchPmWolOvrWkSts
	Offset 0x0659 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. More...
UINT8	PchPmPwrCycDur
	Offset 0x065A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. More...
UINT8	UnusedUpdSpace18
	Offset 0x065B.
UINT8	PchPort61hEnable
	Offset 0x065C - PCH Port 61h Config Enable/Disable Used for the emulation feature for Port61h read. More...
UINT8	SataPwrOptEnable
	Offset 0x065D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. More...
UINT8	EsataSpeedLimit
	Offset 0x065E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. More...
UINT8	SataSpeedLimit
	Offset 0x065F - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
UINT8	SataPortsHotPlug [8]
	Offset 0x0660 - Enable SATA Port HotPlug Enable SATA Port HotPlug.
UINT8	SataPortsInterlockSw [8]
	Offset 0x0668 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw.
UINT8	SataPortsExternal [8]
	Offset 0x0670 - Enable SATA Port External Enable SATA Port External.
UINT8	SataPortsSpinUp [8]
	Offset 0x0678 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device.
UINT8	SataPortsSolidStateDrive [8]
	Offset 0x0680 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD.
UINT8	SataPortsEnableDitoConfig [8]
	Offset 0x0688 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
UINT8	SataPortsDmVal [8]
	Offset 0x0690 - Enable SATA Port DmVal DITO multiplier. More...
UINT16	SataPortsDitoVal [8]
	Offset 0x0698 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625.
UINT8	SataPortsZpOdd [8]
	Offset 0x06A8 - Enable SATA Port ZpOdd Support zero power ODD.
UINT8	SataRstRaidAlternateId
	Offset 0x06B0 - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID. More...
UINT8	SataRstRaid0
	Offset 0x06B1 - PCH Sata Rst Raid0 RAID0. More...
UINT8	SataRstRaid1
	Offset 0x06B2 - PCH Sata Rst Raid1 RAID1. More...
UINT8	SataRstRaid10
	Offset 0x06B3 - PCH Sata Rst Raid10 RAID10. More...
UINT8	SataRstRaid5
	Offset 0x06B4 - PCH Sata Rst Raid5 RAID5. More...
UINT8	SataRstIrrt
	Offset 0x06B5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology. More...
UINT8	SataRstOromUiBanner
	Offset 0x06B6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. More...
UINT8	SataRstOromUiDelay
	Offset 0x06B7 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
UINT8	SataRstHddUnlock
	Offset 0x06B8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. More...
UINT8	SataRstLedLocate
	Offset 0x06B9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. More...
UINT8	SataRstIrrtOnly
	Offset 0x06BA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. More...
UINT8	SataRstSmartStorage
	Offset 0x06BB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. More...
UINT8	SataRstPcieEnable [3]
	Offset 0x06BC - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping.
UINT8	SataRstPcieStoragePort [3]
	Offset 0x06BF - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
UINT8	SataRstPcieDeviceResetDelay [3]
	Offset 0x06C2 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. More...
UINT8	PchScsEmmcHs400TuningRequired
	Offset 0x06C5 - Enable eMMC HS400 Training Determine if HS400 Training is required. More...
UINT8	PchScsEmmcHs400DllDataValid
	Offset 0x06C6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid. More...
UINT8	PchScsEmmcHs400RxStrobeDll1
	Offset 0x06C7 - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
UINT8	PchScsEmmcHs400TxDataDll
	Offset 0x06C8 - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
UINT8	PchScsEmmcHs400DriverStrength
	Offset 0x06C9 - I/O Driver Strength I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm.
UINT8	SerialIoGpio
	Offset 0x06CA - Enable Pch Serial IO GPIO Determines if enable Serial IO GPIO. More...
UINT8	SerialIoI2cVoltage [6]
	Offset 0x06CB - IO voltage for I2C controllers Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V.
UINT8	SerialIoSpiCsPolarity [2]
	Offset 0x06D1 - SPI ChipSelect signal polarity Selects SPI ChipSelect signal polarity.
UINT8	SerialIoUartHwFlowCtrl [3]
	Offset 0x06D3 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS linesh.
UINT8	SerialIoDebugUartNumber
	Offset 0x06D6 - UART Number For Debug Purpose UART number for debug purpose. More...
UINT8	SerialIoEnableDebugUartAfterPost
	Offset 0x06D7 - Enable Debug UART Controller Enable debug UART controller after post.
UINT8	PchSirqEnable
	Offset 0x06D8 - Enable Serial IRQ Determines if enable Serial IRQ. More...
UINT8	PchSirqMode
	Offset 0x06D9 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. More...
UINT8	PchStartFramePulse
	Offset 0x06DA - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
UINT8	PchThermalDeviceEnable
	Offset 0x06DB - Enable Thermal Device Enable Thermal Device. More...
UINT16	PchT0Level
	Offset 0x06DC - Thermal Throttling Custimized T0Level Value Custimized T0Level value.
UINT16	PchT1Level
	Offset 0x06DE - Thermal Throttling Custimized T1Level Value Custimized T1Level value.
UINT16	PchT2Level
	Offset 0x06E0 - Thermal Throttling Custimized T2Level Value Custimized T2Level value.
UINT8	PchTsmicLock
	Offset 0x06E2 - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip. More...
UINT8	PchTTEnable
	Offset 0x06E3 - Enable The Thermal Throttle Enable the thermal throttle function. More...
UINT8	PchTTState13Enable
	Offset 0x06E4 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. More...
UINT8	PchTTLock
	Offset 0x06E5 - Thermal Throttle Lock Thermal Throttle Lock. More...
UINT8	TTSuggestedSetting
	Offset 0x06E6 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. More...
UINT8	TTCrossThrottling
	Offset 0x06E7 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS.
UINT8	PchDmiTsawEn
	Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. More...
UINT8	DmiSuggestedSetting
	Offset 0x06E9 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. More...
UINT8	DmiTS0TW
	Offset 0x06EA - Thermal Sensor 0 Target Width Thermal Sensor 0 Target Width.
UINT8	DmiTS1TW
	Offset 0x06EB - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width.
UINT8	DmiTS2TW
	Offset 0x06EC - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width.
UINT8	DmiTS3TW
	Offset 0x06ED - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width.
UINT8	SataP0T1M
	Offset 0x06EE - Port 0 T1 Multipler Port 0 T1 Multipler.
UINT8	SataP0T2M
	Offset 0x06EF - Port 0 T2 Multipler Port 0 T2 Multipler.
UINT8	SataP0T3M
	Offset 0x06F0 - Port 0 T3 Multipler Port 0 T3 Multipler.
UINT8	SataP0TDisp
	Offset 0x06F1 - Port 0 Tdispatch Port 0 Tdispatch.
UINT8	SataP1T1M
	Offset 0x06F2 - Port 1 T1 Multipler Port 1 T1 Multipler.
UINT8	SataP1T2M
	Offset 0x06F3 - Port 1 T2 Multipler Port 1 T2 Multipler.
UINT8	SataP1T3M
	Offset 0x06F4 - Port 1 T3 Multipler Port 1 T3 Multipler.
UINT8	SataP1TDisp
	Offset 0x06F5 - Port 1 Tdispatch Port 1 Tdispatch.
UINT8	SataP0Tinact
	Offset 0x06F6 - Port 0 Tinactive Port 0 Tinactive.
UINT8	SataP0TDispFinit
	Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. More...
UINT8	SataP1Tinact
	Offset 0x06F8 - Port 1 Tinactive Port 1 Tinactive.
UINT8	SataP1TDispFinit
	Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. More...
UINT8	SataThermalSuggestedSetting
	Offset 0x06FA - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. More...
UINT8	PchMemoryThrottlingEnable
	Offset 0x06FB - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. More...
UINT8	PchMemoryPmsyncEnable [2]
	Offset 0x06FC - Memory Thermal Throttling Enable Memory Thermal Throttling.
UINT8	PchMemoryC0TransmitEnable [2]
	Offset 0x06FE - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
UINT8	PchMemoryPinSelection [2]
	Offset 0x0700 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
UINT16	PchTemperatureHotLevel
	Offset 0x0702 - Thermal Device Temperature Decides the temperature.
UINT8	PchDisableComplianceMode
	Offset 0x0704 - Disable XHCI Compliance Mode This policy will disable XHCI compliance mode on all ports. More...
UINT8	Usb2OverCurrentPin [16]
	Offset 0x0705 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N.
UINT8	Usb3OverCurrentPin [10]
	Offset 0x0715 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N.
UINT8	Early8254ClockGatingEnable
	Offset 0x071F - Enable 8254 Static Clock Gating in early POST time Set 8254CGE=1 is required for C11 support. More...
UINT8	SataRstOptaneMemory
	Offset 0x0720 - PCH Sata Rst Optane Memory Optane Memory $EN_DIS.
UINT8	SataRstCpuAttachedStorage
	Offset 0x0721 - PCH SATA RST CPU attached storage RST CPU attached storage $EN_DIS.
UINT8	UnusedUpdSpace19 [2]
	Offset 0x0722.
UINT32	PchPcieDeviceOverrideTablePtr
	Offset 0x0724 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. More...
UINT8	EnableTcoTimer
	Offset 0x0728 - Enable TCO timer. More...
UINT8	EcCmdProvisionEav
	Offset 0x0729 - EcCmdProvisionEav Ephemeral Authorization Value default values. More...
UINT8	EcCmdLock
	Offset 0x072A - EcCmdLock EcCmdLock default values. More...
UINT8	UnusedUpdSpace20 [5]
	Offset 0x072B.
UINT64	SendEcCmd
	Offset 0x0730 - SendEcCmd SendEcCmd function pointer. More...
UINT64	BgpdtHash [4]
	Offset 0x0738 - BgpdtHash[4] BgpdtHash values.
UINT64	BiosGuardModulePtr
	Offset 0x0758 - BiosGuardModulePtr BiosGuardModulePtr default values.
UINT32	BiosGuardAttr
	Offset 0x0760 - BiosGuardAttr BiosGuardAttr default values.
UINT8	SgxSinitNvsData
	Offset 0x0764 - SgxSinitNvsData SgxSinitNvsData default values.
UINT8	UnusedUpdSpace21 [3]
	Offset 0x0765.
UINT64	SgxEpoch0
	Offset 0x0768 - SgxEpoch0 SgxEpoch0 default values.
UINT64	SgxEpoch1
	Offset 0x0770 - SgxEpoch1 SgxEpoch1 default values.
UINT8	MeUnconfigOnRtcClear
	Offset 0x0778 - Enable/Disable ME Unconfig on RTC clear Enable(Default): Enable ME Unconfig On Rtc Clear, Disable: Disable ME Unconfig On Rtc Clear $EN_DIS.
UINT8	MeUnconfigIsValid
	Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear. More...
UINT8	IslVrCmd
	Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues. More...
UINT8	ReservedFspsUpd [5]
	Offset 0x077B.

Detailed Description

Fsp S Configuration.

Definition at line 88 of file FspsUpd.h.

Member Data Documentation

UINT16 FSP_S_CONFIG::AcLoadline[5]

Offset 0x0298 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie.

1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU.

Definition at line 688 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AcousticNoiseMitigation

Offset 0x0278 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature.

0: Disabled; 1: Enabled $EN_DIS

Definition at line 633 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AmtEnabled

Offset 0x0153 - AMT Switch Enable/Disable.

0: Disable, 1: enable, Enable or disable AMT functionality. $EN_DIS

Definition at line 410 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AmtSolEnabled

Offset 0x015C - SOL Switch Enable/Disable.

0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx $EN_DIS

Definition at line 453 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::AsfEnabled

Offset 0x0155 - ASF Switch Enable/Disable.

0: Disable, 1: enable, Enable or disable ASF functionality. $EN_DIS

Definition at line 422 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::DcLoadline[5]

Offset 0x02A2 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie.

1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU.

Definition at line 694 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::DelayUsbPdoProgramming

Offset 0x00FC - Delay USB PDO Programming Enable/disable delay of PDO programming for USB from PEI phase to DXE phase.

0: disable, 1: enable $EN_DIS

Definition at line 373 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::DevIntConfigPtr

Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.

The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.

Definition at line 251 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::DmiSuggestedSetting

Offset 0x06E9 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values.

$EN_DIS

Definition at line 1843 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Early8254ClockGatingEnable

Offset 0x071F - Enable 8254 Static Clock Gating in early POST time Set 8254CGE=1 is required for C11 support.

However, set 8254CGE=1 in POST time might fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy OS boot before enabling this. $EN_DIS

Definition at line 1982 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EcCmdLock

Offset 0x072A - EcCmdLock EcCmdLock default values.

Locks Ephemeral Authorization Value sent previously

Definition at line 2024 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EcCmdProvisionEav

Offset 0x0729 - EcCmdProvisionEav Ephemeral Authorization Value default values.

Provisions an ephemeral shared secret to the EC

Definition at line 2019 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EnableTcoTimer

Offset 0x0728 - Enable TCO timer.

When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. $EN_DIS

Definition at line 2014 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::EsataSpeedLimit

Offset 0x065E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.

$EN_DIS

Definition at line 1561 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FastPkgCRampDisableGt

Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled.

0: False; 1: True $EN_DIS

Definition at line 733 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FastPkgCRampDisableIa

Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled.

0: False; 1: True $EN_DIS

Definition at line 640 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FastPkgCRampDisableSa

Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled.

0: False; 1: True $EN_DIS

Definition at line 740 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::FwProgress

Offset 0x0157 - PET Progress Enable/Disable.

0: Disable, 1: enable, Enable/Disable PET Events Progress to receive PET Events. $EN_DIS

Definition at line 435 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::GpioIrqRoute

Offset 0x0087 - Select GPIO IRQ Route GPIO IRQ Select.

The valid value is 14 or 15.

Definition at line 270 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Heci3Enabled

Offset 0x0149 - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.

0: disable, 1: enable $EN_DIS

Definition at line 400 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::IccMax[5]

Offset 0x02CA - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit.

0-255A in 1/4 A units. 400 = 100A

Definition at line 717 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ImonOffset[5]

Offset 0x025D - Imon offset correction PCODE MMIO Mailbox: Imon offset correction.

Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto

Definition at line 591 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ImonSlope[5]

Offset 0x0258 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction.

Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes

Definition at line 585 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::IslVrCmd

Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues.

Intersil VR mailbox command. 0 - no mailbox command sent. 1 - VR mailbox command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.

Definition at line 2087 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ManageabilityMode

Offset 0x0156 - Manageability Mode set by Mebx Enable/Disable.

0: Disable, 1: enable, Enable or disable Manageability Mode. $EN_DIS

Definition at line 428 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::MeUnconfigIsValid

Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear.

$EN_DIS

Definition at line 2081 of file FspsUpd.h.

UINT64 FSP_S_CONFIG::MicrocodePatchAddress

Offset 0x02F0 - MicrocodePatchAddress Pointer to microcode patch that is suitable for this processor.

0:Disable, 1:Enable

Definition at line 775 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::NumOfDevIntConfig

Offset 0x006F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry.

If this is not zero, the DevIntConfigPtr must not be NULL.

Definition at line 246 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchCio2Enable

Offset 0x0030 - Enable CIO2 Controller Enable/disable SKYCAM CIO2 Controller.

$EN_DIS

Definition at line 137 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchCrid

Offset 0x0365 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled.

$EN_DIS

Definition at line 1192 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchDisableComplianceMode

Offset 0x0704 - Disable XHCI Compliance Mode This policy will disable XHCI compliance mode on all ports.

Complicance Mode should be default enabled. $EN_DIS

Definition at line 1964 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchDmiAspm

Offset 0x0316 - Enable DMI ASPM ASPM on PCH side of the DMI Link.

$EN_DIS

Definition at line 921 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchDmiTsawEn

Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable.

$EN_DIS

Definition at line 1837 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaDspEnable

Offset 0x002E - Enable HD Audio DSP Enable/disable HD Audio DSP feature.

$EN_DIS

Definition at line 121 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaDspEndpointBluetooth

Offset 0x033F - DSP Bluetooth enablement 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1003 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaDspEndpointI2s

Offset 0x0348 - DSP I2S enablement 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1023 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PchHdaDspFeatureMask

Offset 0x0340 - Bitmask of supported DSP features [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6].

• BT Intel A2DP; [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation.

Definition at line 1010 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaDspUaaCompliance

Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported).

$EN_DIS

Definition at line 986 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaEnable

Offset 0x002D - Enable Intel HD Audio (Azalia) Enable/disable Azalia controller.

$EN_DIS

Definition at line 115 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaIDispCodecDisconnect

Offset 0x033D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.

$EN_DIS

Definition at line 992 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaIoBufferOwnership

Offset 0x002F - Select HDAudio IoBuffer Ownership Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port.

0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4 of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports own all the I/O buffers. 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports

Definition at line 131 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchHdaPme

Offset 0x0336 - Enable Pme Enable Azalia wake-on-ring.

$EN_DIS

Definition at line 954 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicBdfValid

Offset 0x0349 - Enable PCH Io Apic Set to 1 if BDF value is valid.

$EN_DIS

Definition at line 1029 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicBusNumber

Offset 0x034A - PCH Io Apic Bus Number Bus/Device/Function used as Requestor / Completer ID.

Default is 0xF0.

Definition at line 1034 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicDeviceNumber

Offset 0x034B - PCH Io Apic Device Number Bus/Device/Function used as Requestor / Completer ID.

Default is 0x1F.

Definition at line 1039 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicEntry24_119

Offset 0x034D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1050 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicFunctionNumber

Offset 0x034C - PCH Io Apic Function Number Bus/Device/Function used as Requestor / Completer ID.

Default is 0x00.

Definition at line 1044 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicId

Offset 0x034E - PCH Io Apic ID This member determines IOAPIC ID.

Default is 0x02.

Definition at line 1055 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIoApicRangeSelect

Offset 0x034F - PCH Io Apic Range Select Define address bits 19:12 for the IOxAPIC range.

Default is 0.

Definition at line 1060 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshEnable

Offset 0x0034 - Enable PCH ISH Controller Enable/disable ISH Controller.

$EN_DIS

Definition at line 161 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp0GpioAssign

Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1102 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp1GpioAssign

Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1108 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp2GpioAssign

Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1114 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp3GpioAssign

Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1120 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp4GpioAssign

Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1126 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp5GpioAssign

Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1132 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp6GpioAssign

Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1138 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshGp7GpioAssign

Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1144 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshI2c0GpioAssign

Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1084 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshI2c1GpioAssign

Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1090 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshI2c2GpioAssign

Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1096 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshPdtUnlock

Offset 0x035E - PCH ISH PDT Unlock Msg 0: False; 1: True.

$EN_DIS

Definition at line 1150 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshSpiGpioAssign

Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1066 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshUart0GpioAssign

Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1072 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchIshUart1GpioAssign

Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1078 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLanClkReqSupported

Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1168 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLanEnable

Offset 0x00FB - Enable LAN Enable/disable LAN controller.

$EN_DIS

Definition at line 366 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLanK1OffEnable

Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1162 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLanLtrEnable

Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable.

$EN_DIS

Definition at line 1156 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLockDownBiosLock

Offset 0x0363 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection.

$EN_DIS

Definition at line 1180 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchLockDownSpiEiss

Offset 0x0364 - Enable LOCKDOWN SPI Eiss Enable InSMM.STS (EISS) in SPI.

$EN_DIS

Definition at line 1186 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchMemoryThrottlingEnable

Offset 0x06FB - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.

$EN_DIS

Definition at line 1937 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PchPcieDeviceOverrideTablePtr

Offset 0x0724 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings.

This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0.

Definition at line 2006 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmCapsuleResetType

Offset 0x0655 - PCH Pm Capsule Reset Type Deprecated: Determines type of reset issued during UpdateCapsule().

Always Warm reset. $EN_DIS

Definition at line 1508 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmDeepSxPol

Offset 0x0645 - PCH Pm Deep Sx Pol Deep Sx Policy.

$EN_DIS

Definition at line 1449 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmDisableDsxAcPresentPulldown

Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.

$EN_DIS

Definition at line 1502 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmDisableNativePowerButton

Offset 0x0656 - PCH Pm Disable Native Power Button Power button native mode disable.

$EN_DIS

Definition at line 1514 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmLanWakeFromDeepSx

Offset 0x0644 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx.

$EN_DIS

Definition at line 1443 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmLpcClockRun

Offset 0x0650 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled.

$EN_DIS

Definition at line 1479 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmMeWakeSts

Offset 0x0658 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.

$EN_DIS

Definition at line 1526 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPcieWakeFromDeepSx

Offset 0x0641 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx.

$EN_DIS

Definition at line 1424 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPmeB0S5Dis

Offset 0x0639 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.

$EN_DIS

Definition at line 1402 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPwrBtnOverridePeriod

Offset 0x0653 - PCH Pm Pwr Btn Override Period PCH power button override period.

000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.

Definition at line 1496 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmPwrCycDur

Offset 0x065A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second.

Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ...

Definition at line 1538 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpAMinAssert

Offset 0x0649 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy.

Default is PchSlpA2s.

Definition at line 1469 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpLanLowDc

Offset 0x0652 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power.

$EN_DIS

Definition at line 1491 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS0Enable

Offset 0x0657 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.

$EN_DIS

Definition at line 1520 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS0VmEnable

Offset 0x063A - PCH Pm Slp S0 Voltage Margining Enable Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state.

$EN_DIS

Definition at line 1408 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS3MinAssert

Offset 0x0646 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy.

Default is PchSlpS350ms.

Definition at line 1454 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpS4MinAssert

Offset 0x0647 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy.

Default is PchSlpS44s.

Definition at line 1459 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpStrchSusUp

Offset 0x0651 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up.

$EN_DIS

Definition at line 1485 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmSlpSusMinAssert

Offset 0x0648 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy.

Default is PchSlpSus4s.

Definition at line 1464 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWolEnableOverride

Offset 0x0640 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.

$EN_DIS

Definition at line 1418 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWolOvrWkSts

Offset 0x0659 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.

$EN_DIS

Definition at line 1532 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWoWlanDeepSxEnable

Offset 0x0643 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register.

$EN_DIS

Definition at line 1437 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPmWoWlanEnable

Offset 0x0642 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.

$EN_DIS

Definition at line 1430 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPort61hEnable

Offset 0x065C - PCH Port 61h Config Enable/Disable Used for the emulation feature for Port61h read.

The port is trapped and the SMI handler will toggle bit4 according to the handler's internal state. $EN_DIS

Definition at line 1549 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchPwrOptEnable

Offset 0x0317 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side.

$EN_DIS

Definition at line 927 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchScsEmmcHs400DllDataValid

Offset 0x06C6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid.

$EN_DIS

Definition at line 1710 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchScsEmmcHs400TuningRequired

Offset 0x06C5 - Enable eMMC HS400 Training Determine if HS400 Training is required.

$EN_DIS

Definition at line 1704 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSirqEnable

Offset 0x06D8 - Enable Serial IRQ Determines if enable Serial IRQ.

$EN_DIS

Definition at line 1762 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSirqMode

Offset 0x06D9 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.

$EN_DIS

Definition at line 1768 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortACtleEnable

Offset 0x0303 - Enable SkyCam PortA Ctle Enable/disable PortA Ctle.

$EN_DIS

Definition at line 838 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortATermOvrEnable

Offset 0x02FB - Enable SkyCam PortA Termination override Enable/disable PortA Termination override.

$EN_DIS

Definition at line 790 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortATrimEnable

Offset 0x02FF - Enable SkyCam PortA Clk Trim Enable/disable PortA Clk Trim.

$EN_DIS

Definition at line 814 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortBCtleEnable

Offset 0x0304 - Enable SkyCam PortB Ctle Enable/disable PortB Ctle.

$EN_DIS

Definition at line 844 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortBTermOvrEnable

Offset 0x02FC - Enable SkyCam PortB Termination override Enable/disable PortB Termination override.

$EN_DIS

Definition at line 796 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortBTrimEnable

Offset 0x0300 - Enable SkyCam PortB Clk Trim Enable/disable PortB Clk Trim.

$EN_DIS

Definition at line 820 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortCDCtleEnable

Offset 0x0305 - Enable SkyCam PortCD Ctle Enable/disable PortCD Ctle.

$EN_DIS

Definition at line 850 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortCTermOvrEnable

Offset 0x02FD - Enable SkyCam PortC Termination override Enable/disable PortC Termination override.

$EN_DIS

Definition at line 802 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortCTrimEnable

Offset 0x0301 - Enable SkyCam PortC Clk Trim Enable/disable PortC Clk Trim.

$EN_DIS

Definition at line 826 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortDTermOvrEnable

Offset 0x02FE - Enable SkyCam PortD Termination override Enable/disable PortD Termination override.

$EN_DIS

Definition at line 808 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchSkyCamPortDTrimEnable

Offset 0x0302 - Enable SkyCam PortD Clk Trim Enable/disable PortD Clk Trim.

$EN_DIS

Definition at line 832 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::PchSubSystemId

Offset 0x0368 - PCH Sub system ID Default Subsystem ID of the PCH devices.

Default is 0x7270.

Definition at line 1202 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::PchSubSystemVendorId

Offset 0x0366 - PCH Sub system vendor ID Default Subsystem Vendor ID of the PCH devices.

Default is 0x8086.

Definition at line 1197 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchThermalDeviceEnable

Offset 0x06DB - Enable Thermal Device Enable Thermal Device.

$EN_DIS

Definition at line 1779 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTsmicLock

Offset 0x06E2 - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip.

$EN_DIS

Definition at line 1800 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTTEnable

Offset 0x06E3 - Enable The Thermal Throttle Enable the thermal throttle function.

$EN_DIS

Definition at line 1806 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTTLock

Offset 0x06E5 - Thermal Throttle Lock Thermal Throttle Lock.

$EN_DIS

Definition at line 1819 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PchTTState13Enable

Offset 0x06E4 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.

$EN_DIS

Definition at line 1813 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieAllowNoLtrIccPllShutdown

Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable or leaving untouched.

$EN_DIS

Definition at line 1377 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieComplianceTestMode

Offset 0x0635 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board.

$EN_DIS

Definition at line 1383 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieDisableRootPortClockGating

Offset 0x0632 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules.

0: Disable; 1: Enable. $EN_DIS

Definition at line 1364 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieEnablePeerMemoryWrite

Offset 0x0633 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform.

$EN_DIS

Definition at line 1370 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieEqPh3LaneParamCm[24]

Offset 0x05F8 - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM.

Coefficient C-1.

Definition at line 1342 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieEqPh3LaneParamCp[24]

Offset 0x0610 - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM.

Coefficient C+1.

Definition at line 1347 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpAspm[24]

Offset 0x0598 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL).

Default is PchPcieAspmAutoConfig.

Definition at line 1321 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpClkReqNumber[24]

Offset 0x012C - Configure CLKREQ Number Configure Root Port CLKREQ Number if CLKREQ is supported.

Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on.

Definition at line 389 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpClkReqSupport[24]

Offset 0x0114 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support.

0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on.

Definition at line 383 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpClkSrcNumber[24]

Offset 0x015D - Configure CLKSRC Number Configure Root Port CLKSRC Number.

Each value in arrary can be between 0-6 for valid clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for port1, byte1 for port2, and so on.

Definition at line 460 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpCompletionTimeout[24]

Offset 0x0520 - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT).

Default is PchPcieCompletionTO_Default.

Definition at line 1309 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::PcieRpDeviceResetPad[24]

Offset 0x0538 - PCIE RP Device Reset Pad The PCH pin assigned to device PERST# signal if available, zero otherwise.

See also DeviceResetPadActiveHigh.

Definition at line 1315 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpFunctionSwap

Offset 0x0638 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled.

$EN_DIS

Definition at line 1396 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpGen3EqPh3Method[24]

Offset 0x04F0 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD).

0: Default; 2: Software Search; 4: Fixed Coeficients.

Definition at line 1299 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpL1Substates[24]

Offset 0x05B0 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).

Default is PchPcieL1SubstatesL1_1_2.

Definition at line 1327 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpPcieSpeed[24]

Offset 0x04D8 - PCIE RP Pcie Speed Determines each PCIE Port speed capability.

0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED).

Definition at line 1293 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieRpPhysicalSlotNumber[24]

Offset 0x0508 - PCIE RP Physical Slot Number Indicates the slot number for the root port.

Default is the value as root port index.

Definition at line 1304 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieSwEqCoeffListCm[5]

Offset 0x0628 - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM.

Coefficient C-1.

Definition at line 1352 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PcieSwEqCoeffListCp[5]

Offset 0x062D - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM.

Coefficient C+1.

Definition at line 1357 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PortUsb20Enable[16]

Offset 0x0052 - Enable USB2 ports Enable/disable per USB2 ports.

One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 218 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PortUsb30Enable[10]

Offset 0x0062 - Enable USB3 ports Enable/disable per USB3 ports.

One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 224 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::Psi1Threshold[5]

Offset 0x02AC - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments.

Range is 0-128A. Default Value = 20A.

Definition at line 700 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::Psi2Threshold[5]

Offset 0x02B6 - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments.

Range is 0-128A. Default Value = 5A.

Definition at line 706 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Psi3Enable[5]

Offset 0x024E - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable.

For all VR Indexes

Definition at line 573 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::Psi3Threshold[5]

Offset 0x02C0 - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments.

Range is 0-128A. Default Value = 1A.

Definition at line 712 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PsysOffset

Offset 0x0277 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction.

0 - Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset

Definition at line 627 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PsysSlope

Offset 0x0276 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction.

0 - Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25

Definition at line 621 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::PxRcConfig[8]

Offset 0x007F - PIRQx to IRQx Map Config PIRQx to IRQx mapping.

The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode.

Definition at line 265 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataEnable

Offset 0x0091 - Enable SATA Enable/disable SATA controller.

$EN_DIS

Definition at line 306 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataMode

Offset 0x0092 - SATA Mode Select SATA controller working mode.

0:AHCI, 1:RAID

Definition at line 312 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataP0TDispFinit

Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch.

$EN_DIS

Definition at line 1914 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataP1TDispFinit

Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch.

$EN_DIS

Definition at line 1925 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPortsDevSlp[8]

Offset 0x004A - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port.

0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 212 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPortsDmVal[8]

Offset 0x0690 - Enable SATA Port DmVal DITO multiplier.

Default is 15.

Definition at line 1601 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPortsEnable[8]

Offset 0x0042 - Enable SATA ports Enable/disable SATA ports.

One byte for each port, byte0 for port0, byte1 for port1, and so on.

Definition at line 206 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataPwrOptEnable

Offset 0x065D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side.

$EN_DIS

Definition at line 1555 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstHddUnlock

Offset 0x06B8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled.

$EN_DIS

Definition at line 1664 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstIrrt

Offset 0x06B5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology.

$EN_DIS

Definition at line 1647 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstIrrtOnly

Offset 0x06BA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports.

$EN_DIS

Definition at line 1677 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstLedLocate

Offset 0x06B9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.

$EN_DIS

Definition at line 1671 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstOromUiBanner

Offset 0x06B6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER.

$EN_DIS

Definition at line 1653 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstPcieDeviceResetDelay[3]

Offset 0x06C2 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds.

Default value is 100ms

Definition at line 1698 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid0

Offset 0x06B1 - PCH Sata Rst Raid0 RAID0.

$EN_DIS

Definition at line 1623 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid1

Offset 0x06B2 - PCH Sata Rst Raid1 RAID1.

$EN_DIS

Definition at line 1629 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid10

Offset 0x06B3 - PCH Sata Rst Raid10 RAID10.

$EN_DIS

Definition at line 1635 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaid5

Offset 0x06B4 - PCH Sata Rst Raid5 RAID5.

$EN_DIS

Definition at line 1641 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstRaidAlternateId

Offset 0x06B0 - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID.

0:Client, 1:Alternate, 2:Server

Definition at line 1617 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataRstSmartStorage

Offset 0x06BB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit.

$EN_DIS

Definition at line 1683 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataSalpSupport

Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management.

$EN_DIS

Definition at line 200 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SataThermalSuggestedSetting

Offset 0x06FA - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting.

$EN_DIS

Definition at line 1931 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SciIrqSelect

Offset 0x0088 - Select SciIrqSelect SCI IRQ Select.

The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.

Definition at line 275 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ScsEmmcEnabled

Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller.

$EN_DIS

Definition at line 143 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ScsEmmcHs400Enabled

Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode.

$EN_DIS

Definition at line 149 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ScsSdCardEnabled

Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller.

$EN_DIS

Definition at line 155 of file FspsUpd.h.

UINT64 FSP_S_CONFIG::SendEcCmd

Offset 0x0730 - SendEcCmd SendEcCmd function pointer.

 typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE 
EcCmdType, IN UINT8  EcCmd, IN UINT8  SendData, IN OUT UINT8  *ReceiveData); 

Definition at line 2035 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SendVrMbxCmd

Offset 0x02E2 - Enable VR specific mailbox command VR specific mailbox commands.

00b - no VR specific command sent. 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific command sent for PS4 exit issue. 11b - Reserved. $EN_DIS

Definition at line 752 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SendVrMbxCmd1

Offset 0x02E3 - Select VR specific mailbox command to send VR specific mailbox commands.

000b - no VR specific command sent. 001b - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 010b - VR specific command sent for PS4 exit issue. 100b - VR specific command sent for MPS VR decay issue.

Definition at line 759 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SerialIoDebugUartNumber

Offset 0x06D6 - UART Number For Debug Purpose UART number for debug purpose.

0:UART0, 1: UART1, 2:UART2.

Definition at line 1751 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SerialIoDevMode[11]

Offset 0x0074 - Enable SerialIo Device Mode 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode respectively.

One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.

Definition at line 258 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SerialIoGpio

Offset 0x06CA - Enable Pch Serial IO GPIO Determines if enable Serial IO GPIO.

$EN_DIS

Definition at line 1731 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::ShowSpiController

Offset 0x0035 - Show SPI controller Enable/disable to show SPI controller.

$EN_DIS

Definition at line 167 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlowSlewRateForGt

Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled.

0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16

Definition at line 654 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlowSlewRateForIa

Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled.

0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16

Definition at line 647 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SlowSlewRateForSa

Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled.

0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16

Definition at line 661 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SpiFlashCfgLockDown

Offset 0x0036 - Flash Configuration Lock Down Enable/disable flash lock down.

If platform decides to skip this programming, it must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. $EN_DIS

Definition at line 174 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::SsicPortEnable

Offset 0x006D - Enable XHCI SSIC Enable Enable/disable XHCI SSIC port.

$EN_DIS

Definition at line 236 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TcoIrqSelect

Offset 0x0089 - Select TcoIrqSelect TCO IRQ Select.

The valid value is 9, 10, 11, 20, 21, 22, 23.

Definition at line 280 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::TdcPowerLimit[5]

Offset 0x0286 - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit.

Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes

Definition at line 671 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TdcTimeWindow[5]

Offset 0x026C - HECI3 state PCODE MMIO Mailbox: Thermal Design Current time window.

Defined in milli seconds. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Indexe

Definition at line 609 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TTSuggestedSetting

Offset 0x06E6 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting.

$EN_DIS

Definition at line 1825 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::TurboMode

Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode.

0: disable, 1: enable $EN_DIS

Definition at line 194 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfePehalfbit[16]

Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis.

1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port.

Definition at line 336 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfePetxiset[16]

Offset 0x0093 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias.

000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.

Definition at line 318 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfePredeemp[16]

Offset 0x00B3 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis.

00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.

Definition at line 330 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb2AfeTxiset[16]

Offset 0x00A3 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias.

000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.

Definition at line 324 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDeEmph[10]

Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis).

One byte for each port.

Definition at line 348 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDeEmphEnable[10]

Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment.

Each value in arrary can be between 0-1. One byte for each port.

Definition at line 342 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDownscaleAmp[10]

Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h.

One byte for each port.

Definition at line 360 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::Usb3HsioTxDownscaleAmpEnable[10]

Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1.

One byte for each port.

Definition at line 354 of file FspsUpd.h.

UINT32 FSP_S_CONFIG::VrPowerDeliveryDesign

Offset 0x0290 - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board.

This value is an enum of the available power delivery segments that are defined in the Platform Design Guide.

Definition at line 678 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::VrVoltageLimit[5]

Offset 0x02D4 - VR Voltage Limit PCODE MMIO Mailbox: VR Voltage Limit.

Range is 0-7999mV.

Definition at line 722 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::WatchDog

Offset 0x0154 - WatchDog Timer Switch Enable/Disable.

0: Disable, 1: enable, Enable or disable WatchDog timer. $EN_DIS

Definition at line 416 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::WatchDogTimerBios

Offset 0x015A - BIOS Timer 16 bits Value, Set BIOS watchdog timer.

$EN_DIS

Definition at line 447 of file FspsUpd.h.

UINT16 FSP_S_CONFIG::WatchDogTimerOs

Offset 0x0158 - OS Timer 16 bits Value, Set OS watchdog timer.

$EN_DIS

Definition at line 441 of file FspsUpd.h.

UINT8 FSP_S_CONFIG::XdciEnable

Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller.

$EN_DIS

Definition at line 230 of file FspsUpd.h.

---

The documentation for this struct was generated from the following file:

• FspsUpd.h