|
|
UINT32 | LogoPtr |
| | Offset 0x0020 - Logo Pointer Points to PEI Display Logo Image.
|
| |
|
UINT32 | LogoSize |
| | Offset 0x0024 - Logo Size Size of PEI Display Logo Image.
|
| |
|
UINT32 | GraphicsConfigPtr |
| | Offset 0x0028 - Graphics Configuration Ptr Points to VBT.
|
| |
|
UINT8 | Device4Enable |
| | Offset 0x002C - Enable Device 4 Enable/disable Device 4 $EN_DIS.
|
| |
| UINT8 | PchHdaEnable |
| | Offset 0x002D - Enable Intel HD Audio (Azalia) Enable/disable Azalia controller. More...
|
| |
| UINT8 | PchHdaDspEnable |
| | Offset 0x002E - Enable HD Audio DSP Enable/disable HD Audio DSP feature. More...
|
| |
| UINT8 | PchHdaIoBufferOwnership |
| | Offset 0x002F - Select HDAudio IoBuffer Ownership Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 / I2S port. More...
|
| |
| UINT8 | PchCio2Enable |
| | Offset 0x0030 - Enable CIO2 Controller Enable/disable SKYCAM CIO2 Controller. More...
|
| |
| UINT8 | ScsEmmcEnabled |
| | Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller. More...
|
| |
| UINT8 | ScsEmmcHs400Enabled |
| | Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode. More...
|
| |
| UINT8 | ScsSdCardEnabled |
| | Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller. More...
|
| |
| UINT8 | PchIshEnable |
| | Offset 0x0034 - Enable PCH ISH Controller Enable/disable ISH Controller. More...
|
| |
| UINT8 | ShowSpiController |
| | Offset 0x0035 - Show SPI controller Enable/disable to show SPI controller. More...
|
| |
| UINT8 | SpiFlashCfgLockDown |
| | Offset 0x0036 - Flash Configuration Lock Down Enable/disable flash lock down. More...
|
| |
|
UINT8 | UnusedUpdSpace0 |
| | Offset 0x0037.
|
| |
|
UINT32 | MicrocodeRegionBase |
| | Offset 0x0038 - MicrocodeRegionBase Memory Base of Microcode Updates.
|
| |
|
UINT32 | MicrocodeRegionSize |
| | Offset 0x003C - MicrocodeRegionSize Size of Microcode Updates.
|
| |
| UINT8 | TurboMode |
| | Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode. More...
|
| |
| UINT8 | SataSalpSupport |
| | Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. More...
|
| |
| UINT8 | SataPortsEnable [8] |
| | Offset 0x0042 - Enable SATA ports Enable/disable SATA ports. More...
|
| |
| UINT8 | SataPortsDevSlp [8] |
| | Offset 0x004A - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. More...
|
| |
| UINT8 | PortUsb20Enable [16] |
| | Offset 0x0052 - Enable USB2 ports Enable/disable per USB2 ports. More...
|
| |
| UINT8 | PortUsb30Enable [10] |
| | Offset 0x0062 - Enable USB3 ports Enable/disable per USB3 ports. More...
|
| |
| UINT8 | XdciEnable |
| | Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller. More...
|
| |
| UINT8 | SsicPortEnable |
| | Offset 0x006D - Enable XHCI SSIC Enable Enable/disable XHCI SSIC port. More...
|
| |
|
UINT8 | UnusedUpdSpace1 |
| | Offset 0x006E.
|
| |
| UINT8 | NumOfDevIntConfig |
| | Offset 0x006F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. More...
|
| |
| UINT32 | DevIntConfigPtr |
| | Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. More...
|
| |
| UINT8 | SerialIoDevMode [11] |
| | Offset 0x0074 - Enable SerialIo Device Mode 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode respectively. More...
|
| |
| UINT8 | PxRcConfig [8] |
| | Offset 0x007F - PIRQx to IRQx Map Config PIRQx to IRQx mapping. More...
|
| |
| UINT8 | GpioIrqRoute |
| | Offset 0x0087 - Select GPIO IRQ Route GPIO IRQ Select. More...
|
| |
| UINT8 | SciIrqSelect |
| | Offset 0x0088 - Select SciIrqSelect SCI IRQ Select. More...
|
| |
| UINT8 | TcoIrqSelect |
| | Offset 0x0089 - Select TcoIrqSelect TCO IRQ Select. More...
|
| |
|
UINT8 | TcoIrqEnable |
| | Offset 0x008A - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS.
|
| |
|
UINT8 | PchHdaVerbTableEntryNum |
| | Offset 0x008B - PCH HDA Verb Table Entry Number Number of Entries in Verb Table.
|
| |
|
UINT32 | PchHdaVerbTablePtr |
| | Offset 0x008C - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table.
|
| |
|
UINT8 | UnusedUpdSpace2 |
| | Offset 0x0090.
|
| |
| UINT8 | SataEnable |
| | Offset 0x0091 - Enable SATA Enable/disable SATA controller. More...
|
| |
| UINT8 | SataMode |
| | Offset 0x0092 - SATA Mode Select SATA controller working mode. More...
|
| |
| UINT8 | Usb2AfePetxiset [16] |
| | Offset 0x0093 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. More...
|
| |
| UINT8 | Usb2AfeTxiset [16] |
| | Offset 0x00A3 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. More...
|
| |
| UINT8 | Usb2AfePredeemp [16] |
| | Offset 0x00B3 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. More...
|
| |
| UINT8 | Usb2AfePehalfbit [16] |
| | Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. More...
|
| |
| UINT8 | Usb3HsioTxDeEmphEnable [10] |
| | Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. More...
|
| |
| UINT8 | Usb3HsioTxDeEmph [10] |
| | Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). More...
|
| |
| UINT8 | Usb3HsioTxDownscaleAmpEnable [10] |
| | Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. More...
|
| |
| UINT8 | Usb3HsioTxDownscaleAmp [10] |
| | Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. More...
|
| |
| UINT8 | PchLanEnable |
| | Offset 0x00FB - Enable LAN Enable/disable LAN controller. More...
|
| |
| UINT8 | DelayUsbPdoProgramming |
| | Offset 0x00FC - Delay USB PDO Programming Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. More...
|
| |
|
UINT8 | UnusedUpdSpace3 [23] |
| | Offset 0x00FD.
|
| |
| UINT8 | PcieRpClkReqSupport [24] |
| | Offset 0x0114 - Enable PCIE RP CLKREQ Support Enable/disable PCIE Root Port CLKREQ support. More...
|
| |
| UINT8 | PcieRpClkReqNumber [24] |
| | Offset 0x012C - Configure CLKREQ Number Configure Root Port CLKREQ Number if CLKREQ is supported. More...
|
| |
|
UINT8 | UnusedUpdSpace4 [5] |
| | Offset 0x0144.
|
| |
| UINT8 | Heci3Enabled |
| | Offset 0x0149 - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. More...
|
| |
|
UINT8 | UnusedUpdSpace5 [9] |
| | Offset 0x014A.
|
| |
| UINT8 | AmtEnabled |
| | Offset 0x0153 - AMT Switch Enable/Disable. More...
|
| |
| UINT8 | WatchDog |
| | Offset 0x0154 - WatchDog Timer Switch Enable/Disable. More...
|
| |
| UINT8 | AsfEnabled |
| | Offset 0x0155 - ASF Switch Enable/Disable. More...
|
| |
| UINT8 | ManageabilityMode |
| | Offset 0x0156 - Manageability Mode set by Mebx Enable/Disable. More...
|
| |
| UINT8 | FwProgress |
| | Offset 0x0157 - PET Progress Enable/Disable. More...
|
| |
| UINT16 | WatchDogTimerOs |
| | Offset 0x0158 - OS Timer 16 bits Value, Set OS watchdog timer. More...
|
| |
| UINT16 | WatchDogTimerBios |
| | Offset 0x015A - BIOS Timer 16 bits Value, Set BIOS watchdog timer. More...
|
| |
| UINT8 | AmtSolEnabled |
| | Offset 0x015C - SOL Switch Enable/Disable. More...
|
| |
| UINT8 | PcieRpClkSrcNumber [24] |
| | Offset 0x015D - Configure CLKSRC Number Configure Root Port CLKSRC Number. More...
|
| |
|
UINT8 | UnusedUpdSpace6 [139] |
| | Offset 0x0175.
|
| |
|
UINT16 | DefaultSvid |
| | Offset 0x0200 - Subsystem Vendor ID for SA devices Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086.
|
| |
|
UINT16 | DefaultSid |
| | Offset 0x0202 - Subsystem Device ID for SA devices Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015.
|
| |
|
UINT8 | CridEnable |
| | Offset 0x0204 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS.
|
| |
|
UINT8 | DmiAspm |
| | Offset 0x0205 - DMI ASPM 0=Disable, 2(Default)=L1 0:Disable, 2:L1.
|
| |
|
UINT16 | PegPhysicalSlotNumber [3] |
| | Offset 0x0206 - PCIe Physical Slot Number per root port Physical Slot Number per root port.
|
| |
|
UINT8 | PegDeEmphasis [3] |
| | Offset 0x020C - PCIe DeEmphasis control per root port 0: -6dB, 1(Default): -3.5dB 0:-6dB, 1:-3.5dB.
|
| |
|
UINT8 | PegSlotPowerLimitValue [3] |
| | Offset 0x020F - PCIe Slot Power Limit value per root port Slot power limit value per root port.
|
| |
|
UINT8 | PegSlotPowerLimitScale [3] |
| | Offset 0x0212 - PCIe Slot Power Limit scale per root port Slot power limit scale per root port 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x.
|
| |
|
UINT8 | PavpEnable |
| | Offset 0x0215 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS.
|
| |
|
UINT8 | CdClock |
| | Offset 0x0216 - CdClock Frequency selection 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)= 675 Mhz 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz.
|
| |
|
UINT8 | PeiGraphicsPeimInit |
| | Offset 0x0217 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS.
|
| |
|
UINT8 | SaImguEnable |
| | Offset 0x0218 - Enable/Disable SA IMGU(SKYCAM) Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM) $EN_DIS.
|
| |
|
UINT8 | GmmEnable |
| | Offset 0x0219 - Enable or disable GMM device 0=Disable, 1(Default)=Enable $EN_DIS.
|
| |
|
UINT8 | X2ApicOptOut |
| | Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS.
|
| |
|
UINT8 | UnusedUpdSpace7 [1] |
| | Offset 0x021B.
|
| |
|
UINT32 | VtdBaseAddress [2] |
| | Offset 0x021C - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine.
|
| |
|
UINT8 | UnusedUpdSpace8 [19] |
| | Offset 0x0224.
|
| |
|
UINT8 | SaPostMemProductionRsvd [16] |
| | Offset 0x0237 - SaPostMemProductionRsvd Reserved for SA Post-Mem Production $EN_DIS.
|
| |
|
UINT8 | UnusedUpdSpace9 [7] |
| | Offset 0x0247.
|
| |
| UINT8 | Psi3Enable [5] |
| | Offset 0x024E - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. More...
|
| |
|
UINT8 | Psi4Enable [5] |
| | Offset 0x0253 - Power State 4 enable/disable PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes.
|
| |
| UINT8 | ImonSlope [5] |
| | Offset 0x0258 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. More...
|
| |
| UINT8 | ImonOffset [5] |
| | Offset 0x025D - Imon offset correction PCODE MMIO Mailbox: Imon offset correction. More...
|
| |
|
UINT8 | VrConfigEnable [5] |
| | Offset 0x0262 - Enable/Disable BIOS configuration of VR Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes.
|
| |
|
UINT8 | TdcEnable [5] |
| | Offset 0x0267 - Thermal Design Current enable/disable PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes.
|
| |
| UINT8 | TdcTimeWindow [5] |
| | Offset 0x026C - HECI3 state PCODE MMIO Mailbox: Thermal Design Current time window. More...
|
| |
|
UINT8 | TdcLock [5] |
| | Offset 0x0271 - Thermal Design Current Lock PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes.
|
| |
| UINT8 | PsysSlope |
| | Offset 0x0276 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction. More...
|
| |
| UINT8 | PsysOffset |
| | Offset 0x0277 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction. More...
|
| |
| UINT8 | AcousticNoiseMitigation |
| | Offset 0x0278 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature. More...
|
| |
| UINT8 | FastPkgCRampDisableIa |
| | Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT8 | SlowSlewRateForIa |
| | Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT8 | SlowSlewRateForGt |
| | Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT8 | SlowSlewRateForSa |
| | Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. More...
|
| |
|
UINT8 | UnusedUpdSpace10 [9] |
| | Offset 0x027D.
|
| |
| UINT16 | TdcPowerLimit [5] |
| | Offset 0x0286 - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit. More...
|
| |
| UINT32 | VrPowerDeliveryDesign |
| | Offset 0x0290 - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. More...
|
| |
|
UINT8 | UnusedUpdSpace11 [4] |
| | Offset 0x0294.
|
| |
| UINT16 | AcLoadline [5] |
| | Offset 0x0298 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. More...
|
| |
| UINT16 | DcLoadline [5] |
| | Offset 0x02A2 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. More...
|
| |
| UINT16 | Psi1Threshold [5] |
| | Offset 0x02AC - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. More...
|
| |
| UINT16 | Psi2Threshold [5] |
| | Offset 0x02B6 - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. More...
|
| |
| UINT16 | Psi3Threshold [5] |
| | Offset 0x02C0 - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. More...
|
| |
| UINT16 | IccMax [5] |
| | Offset 0x02CA - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit. More...
|
| |
| UINT16 | VrVoltageLimit [5] |
| | Offset 0x02D4 - VR Voltage Limit PCODE MMIO Mailbox: VR Voltage Limit. More...
|
| |
|
UINT8 | UnusedUpdSpace12 |
| | Offset 0x02DE.
|
| |
| UINT8 | FastPkgCRampDisableGt |
| | Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT8 | FastPkgCRampDisableSa |
| | Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
|
| |
|
UINT8 | UnusedUpdSpace13 |
| | Offset 0x02E1.
|
| |
| UINT8 | SendVrMbxCmd |
| | Offset 0x02E2 - Enable VR specific mailbox command VR specific mailbox commands. More...
|
| |
| UINT8 | SendVrMbxCmd1 |
| | Offset 0x02E3 - Select VR specific mailbox command to send VR specific mailbox commands. More...
|
| |
|
UINT32 | CpuS3ResumeMtrrData |
| | Offset 0x02E4 - CpuS3ResumeMtrrData Pointer to CPU S3 Resume MTRR Data.
|
| |
|
CPU_CONFIG_FSP_DATA | CpuConfig |
| | Offset 0x02E8 - Cpu Configuration Cpu Configuration data.
|
| |
| UINT64 | MicrocodePatchAddress |
| | Offset 0x02F0 - MicrocodePatchAddress Pointer to microcode patch that is suitable for this processor. More...
|
| |
|
UINT16 | CpuS3ResumeMtrrDataSize |
| | Offset 0x02F8 - CpuS3ResumeMtrrDataSize Size of S3 resume MTRR data.
|
| |
|
UINT8 | UnusedUpdSpace14 |
| | Offset 0x02FA.
|
| |
| UINT8 | PchSkyCamPortATermOvrEnable |
| | Offset 0x02FB - Enable SkyCam PortA Termination override Enable/disable PortA Termination override. More...
|
| |
| UINT8 | PchSkyCamPortBTermOvrEnable |
| | Offset 0x02FC - Enable SkyCam PortB Termination override Enable/disable PortB Termination override. More...
|
| |
| UINT8 | PchSkyCamPortCTermOvrEnable |
| | Offset 0x02FD - Enable SkyCam PortC Termination override Enable/disable PortC Termination override. More...
|
| |
| UINT8 | PchSkyCamPortDTermOvrEnable |
| | Offset 0x02FE - Enable SkyCam PortD Termination override Enable/disable PortD Termination override. More...
|
| |
| UINT8 | PchSkyCamPortATrimEnable |
| | Offset 0x02FF - Enable SkyCam PortA Clk Trim Enable/disable PortA Clk Trim. More...
|
| |
| UINT8 | PchSkyCamPortBTrimEnable |
| | Offset 0x0300 - Enable SkyCam PortB Clk Trim Enable/disable PortB Clk Trim. More...
|
| |
| UINT8 | PchSkyCamPortCTrimEnable |
| | Offset 0x0301 - Enable SkyCam PortC Clk Trim Enable/disable PortC Clk Trim. More...
|
| |
| UINT8 | PchSkyCamPortDTrimEnable |
| | Offset 0x0302 - Enable SkyCam PortD Clk Trim Enable/disable PortD Clk Trim. More...
|
| |
| UINT8 | PchSkyCamPortACtleEnable |
| | Offset 0x0303 - Enable SkyCam PortA Ctle Enable/disable PortA Ctle. More...
|
| |
| UINT8 | PchSkyCamPortBCtleEnable |
| | Offset 0x0304 - Enable SkyCam PortB Ctle Enable/disable PortB Ctle. More...
|
| |
| UINT8 | PchSkyCamPortCDCtleEnable |
| | Offset 0x0305 - Enable SkyCam PortCD Ctle Enable/disable PortCD Ctle. More...
|
| |
|
UINT8 | PchSkyCamPortACtleCapValue |
| | Offset 0x0306 - Enable SkyCam PortA Ctle Cap Value Enable/disable PortA Ctle Cap Value.
|
| |
|
UINT8 | PchSkyCamPortBCtleCapValue |
| | Offset 0x0307 - Enable SkyCam PortB Ctle Cap Value Enable/disable PortB Ctle Cap Value.
|
| |
|
UINT8 | PchSkyCamPortCDCtleCapValue |
| | Offset 0x0308 - Enable SkyCam PortCD Ctle Cap Value Enable/disable PortCD Ctle Cap Value.
|
| |
|
UINT8 | PchSkyCamPortACtleResValue |
| | Offset 0x0309 - Enable SkyCam PortA Ctle Res Value Enable/disable PortA Ctle Res Value.
|
| |
|
UINT8 | PchSkyCamPortBCtleResValue |
| | Offset 0x030A - Enable SkyCam PortB Ctle Res Value Enable/disable PortB Ctle Res Value.
|
| |
|
UINT8 | PchSkyCamPortCDCtleResValue |
| | Offset 0x030B - Enable SkyCam PortCD Ctle Res Value Enable/disable PortCD Ctle Res Value.
|
| |
|
UINT8 | PchSkyCamPortAClkTrimValue |
| | Offset 0x030C - Enable SkyCam PortA Clk Trim Value Enable/disable PortA Clk Trim Value.
|
| |
|
UINT8 | PchSkyCamPortBClkTrimValue |
| | Offset 0x030D - Enable SkyCam PortB Clk Trim Value Enable/disable PortB Clk Trim Value.
|
| |
|
UINT8 | PchSkyCamPortCClkTrimValue |
| | Offset 0x030E - Enable SkyCam PortC Clk Trim Value Enable/disable PortC Clk Trim Value.
|
| |
|
UINT8 | PchSkyCamPortDClkTrimValue |
| | Offset 0x030F - Enable SkyCam PortD Clk Trim Value Enable/disable PortD Clk Trim Value.
|
| |
|
UINT16 | PchSkyCamPortADataTrimValue |
| | Offset 0x0310 - Enable SkyCam Port A Data Trim Value Enable/disable Port A Data Trim Value.
|
| |
|
UINT16 | PchSkyCamPortBDataTrimValue |
| | Offset 0x0312 - Enable SkyCam Port B Data Trim Value Enable/disable Port B Data Trim Value.
|
| |
|
UINT16 | PchSkyCamPortCDDataTrimValue |
| | Offset 0x0314 - Enable SkyCam C/D Data Trim Value Enable/disable C/D Data Trim Value.
|
| |
| UINT8 | PchDmiAspm |
| | Offset 0x0316 - Enable DMI ASPM ASPM on PCH side of the DMI Link. More...
|
| |
| UINT8 | PchPwrOptEnable |
| | Offset 0x0317 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. More...
|
| |
|
UINT8 | PchWriteProtectionEnable [5] |
| | Offset 0x0318 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware.
|
| |
|
UINT8 | PchReadProtectionEnable [5] |
| | Offset 0x031D - PCH Flash Protection Ranges Read Enble Read is blocked by hardware.
|
| |
|
UINT16 | PchProtectedRangeLimit [5] |
| | Offset 0x0322 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison.
|
| |
|
UINT16 | PchProtectedRangeBase [5] |
| | Offset 0x032C - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
|
| |
| UINT8 | PchHdaPme |
| | Offset 0x0336 - Enable Pme Enable Azalia wake-on-ring. More...
|
| |
|
UINT8 | PchHdaIoBufferVoltage |
| | Offset 0x0337 - IO Buffer Voltage I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V.
|
| |
|
UINT8 | PchHdaVcType |
| | Offset 0x0338 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1.
|
| |
|
UINT8 | PchHdaLinkFrequency |
| | Offset 0x0339 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz.
|
| |
|
UINT8 | PchHdaIDispLinkFrequency |
| | Offset 0x033A - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
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UINT8 | PchHdaIDispLinkTmode |
| | Offset 0x033B - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
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| UINT8 | PchHdaDspUaaCompliance |
| | Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). More...
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| UINT8 | PchHdaIDispCodecDisconnect |
| | Offset 0x033D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. More...
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UINT8 | PchHdaDspEndpointDmic |
| | Offset 0x033E - DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum) 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array.
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| UINT8 | PchHdaDspEndpointBluetooth |
| | Offset 0x033F - DSP Bluetooth enablement 0: Disable; 1: Enable. More...
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| UINT32 | PchHdaDspFeatureMask |
| | Offset 0x0340 - Bitmask of supported DSP features [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6]. More...
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UINT32 | PchHdaDspPpModuleMask |
| | Offset 0x0344 - Bitmask of supported DSP Pre/Post-Processing Modules Deprecated: Specific pre/post-processing module bit position must be coherent with the ACPI implementation: _SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Support.
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| UINT8 | PchHdaDspEndpointI2s |
| | Offset 0x0348 - DSP I2S enablement 0: Disable; 1: Enable. More...
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| UINT8 | PchIoApicBdfValid |
| | Offset 0x0349 - Enable PCH Io Apic Set to 1 if BDF value is valid. More...
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| UINT8 | PchIoApicBusNumber |
| | Offset 0x034A - PCH Io Apic Bus Number Bus/Device/Function used as Requestor / Completer ID. More...
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| UINT8 | PchIoApicDeviceNumber |
| | Offset 0x034B - PCH Io Apic Device Number Bus/Device/Function used as Requestor / Completer ID. More...
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| UINT8 | PchIoApicFunctionNumber |
| | Offset 0x034C - PCH Io Apic Function Number Bus/Device/Function used as Requestor / Completer ID. More...
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| UINT8 | PchIoApicEntry24_119 |
| | Offset 0x034D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. More...
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| UINT8 | PchIoApicId |
| | Offset 0x034E - PCH Io Apic ID This member determines IOAPIC ID. More...
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| UINT8 | PchIoApicRangeSelect |
| | Offset 0x034F - PCH Io Apic Range Select Define address bits 19:12 for the IOxAPIC range. More...
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| UINT8 | PchIshSpiGpioAssign |
| | Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshUart0GpioAssign |
| | Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshUart1GpioAssign |
| | Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshI2c0GpioAssign |
| | Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshI2c1GpioAssign |
| | Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshI2c2GpioAssign |
| | Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshGp0GpioAssign |
| | Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshGp1GpioAssign |
| | Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshGp2GpioAssign |
| | Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshGp3GpioAssign |
| | Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshGp4GpioAssign |
| | Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshGp5GpioAssign |
| | Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshGp6GpioAssign |
| | Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshGp7GpioAssign |
| | Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable. More...
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| UINT8 | PchIshPdtUnlock |
| | Offset 0x035E - PCH ISH PDT Unlock Msg 0: False; 1: True. More...
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| UINT8 | PchLanLtrEnable |
| | Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. More...
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| UINT8 | PchLanK1OffEnable |
| | Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management 0: Disable; 1: Enable. More...
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| UINT8 | PchLanClkReqSupported |
| | Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported 0: Disable; 1: Enable. More...
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UINT8 | PchLanClkReqNumber |
| | Offset 0x0362 - CLKREQ# used by GbE Valid if ClkReqSupported is TRUE.
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| UINT8 | PchLockDownBiosLock |
| | Offset 0x0363 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. More...
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| UINT8 | PchLockDownSpiEiss |
| | Offset 0x0364 - Enable LOCKDOWN SPI Eiss Enable InSMM.STS (EISS) in SPI. More...
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| UINT8 | PchCrid |
| | Offset 0x0365 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. More...
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| UINT16 | PchSubSystemVendorId |
| | Offset 0x0366 - PCH Sub system vendor ID Default Subsystem Vendor ID of the PCH devices. More...
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| UINT16 | PchSubSystemId |
| | Offset 0x0368 - PCH Sub system ID Default Subsystem ID of the PCH devices. More...
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UINT8 | PchLegacyIoLowLatency |
| | Offset 0x036A - PCH Legacy IO Low Latency Enable todo $EN_DIS.
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UINT8 | UnusedUpdSpace15 [5] |
| | Offset 0x036B.
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UINT8 | PcieRpHotPlug [24] |
| | Offset 0x0370 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available.
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UINT8 | PcieRpPmSci [24] |
| | Offset 0x0388 - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled.
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UINT8 | PcieRpExtSync [24] |
| | Offset 0x03A0 - Enable PCIE RP Ext Sync Indicate whether the extended synch is enabled.
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UINT8 | PcieRpTransmitterHalfSwing [24] |
| | Offset 0x03B8 - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled.
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UINT8 | PcieRpClkReqDetect [24] |
| | Offset 0x03D0 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management.
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UINT8 | PcieRpAdvancedErrorReporting [24] |
| | Offset 0x03E8 - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled.
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UINT8 | PcieRpUnsupportedRequestReport [24] |
| | Offset 0x0400 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled.
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UINT8 | PcieRpFatalErrorReport [24] |
| | Offset 0x0418 - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled.
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UINT8 | PcieRpNoFatalErrorReport [24] |
| | Offset 0x0430 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled.
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UINT8 | PcieRpCorrectableErrorReport [24] |
| | Offset 0x0448 - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled.
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UINT8 | PcieRpSystemErrorOnFatalError [24] |
| | Offset 0x0460 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled.
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UINT8 | PcieRpSystemErrorOnNonFatalError [24] |
| | Offset 0x0478 - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled.
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UINT8 | PcieRpSystemErrorOnCorrectableError [24] |
| | Offset 0x0490 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled.
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UINT8 | PcieRpMaxPayload [24] |
| | Offset 0x04A8 - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
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UINT8 | PcieRpDeviceResetPadActiveHigh [24] |
| | Offset 0x04C0 - PCIE RP Device Reset Pad Active High Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad.
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| UINT8 | PcieRpPcieSpeed [24] |
| | Offset 0x04D8 - PCIE RP Pcie Speed Determines each PCIE Port speed capability. More...
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| UINT8 | PcieRpGen3EqPh3Method [24] |
| | Offset 0x04F0 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). More...
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| |
| UINT8 | PcieRpPhysicalSlotNumber [24] |
| | Offset 0x0508 - PCIE RP Physical Slot Number Indicates the slot number for the root port. More...
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| |
| UINT8 | PcieRpCompletionTimeout [24] |
| | Offset 0x0520 - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). More...
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| |
| UINT32 | PcieRpDeviceResetPad [24] |
| | Offset 0x0538 - PCIE RP Device Reset Pad The PCH pin assigned to device PERST# signal if available, zero otherwise. More...
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| |
| UINT8 | PcieRpAspm [24] |
| | Offset 0x0598 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). More...
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| |
| UINT8 | PcieRpL1Substates [24] |
| | Offset 0x05B0 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). More...
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UINT8 | PcieRpLtrEnable [24] |
| | Offset 0x05C8 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism.
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UINT8 | PcieRpLtrConfigLock [24] |
| | Offset 0x05E0 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable.
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| UINT8 | PcieEqPh3LaneParamCm [24] |
| | Offset 0x05F8 - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM. More...
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| |
| UINT8 | PcieEqPh3LaneParamCp [24] |
| | Offset 0x0610 - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM. More...
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| |
| UINT8 | PcieSwEqCoeffListCm [5] |
| | Offset 0x0628 - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM. More...
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| |
| UINT8 | PcieSwEqCoeffListCp [5] |
| | Offset 0x062D - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM. More...
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| |
| UINT8 | PcieDisableRootPortClockGating |
| | Offset 0x0632 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. More...
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| |
| UINT8 | PcieEnablePeerMemoryWrite |
| | Offset 0x0633 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. More...
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| UINT8 | PcieAllowNoLtrIccPllShutdown |
| | Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable or leaving untouched. More...
|
| |
| UINT8 | PcieComplianceTestMode |
| | Offset 0x0635 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. More...
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| |
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UINT16 | PcieDetectTimeoutMs |
| | Offset 0x0636 - PCIE Rp Detect Timeout Ms Will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.
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| |
| UINT8 | PcieRpFunctionSwap |
| | Offset 0x0638 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. More...
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| UINT8 | PchPmPmeB0S5Dis |
| | Offset 0x0639 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. More...
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| |
| UINT8 | PchPmSlpS0VmEnable |
| | Offset 0x063A - PCH Pm Slp S0 Voltage Margining Enable Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state. More...
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UINT8 | UnusedUpdSpace16 [5] |
| | Offset 0x063B.
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| UINT8 | PchPmWolEnableOverride |
| | Offset 0x0640 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. More...
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| |
| UINT8 | PchPmPcieWakeFromDeepSx |
| | Offset 0x0641 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. More...
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| |
| UINT8 | PchPmWoWlanEnable |
| | Offset 0x0642 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. More...
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| |
| UINT8 | PchPmWoWlanDeepSxEnable |
| | Offset 0x0643 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. More...
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| |
| UINT8 | PchPmLanWakeFromDeepSx |
| | Offset 0x0644 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. More...
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| |
| UINT8 | PchPmDeepSxPol |
| | Offset 0x0645 - PCH Pm Deep Sx Pol Deep Sx Policy. More...
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| UINT8 | PchPmSlpS3MinAssert |
| | Offset 0x0646 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. More...
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| UINT8 | PchPmSlpS4MinAssert |
| | Offset 0x0647 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. More...
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| UINT8 | PchPmSlpSusMinAssert |
| | Offset 0x0648 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. More...
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| UINT8 | PchPmSlpAMinAssert |
| | Offset 0x0649 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. More...
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UINT8 | UnusedUpdSpace17 [6] |
| | Offset 0x064A.
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| UINT8 | PchPmLpcClockRun |
| | Offset 0x0650 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled. More...
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| UINT8 | PchPmSlpStrchSusUp |
| | Offset 0x0651 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. More...
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| |
| UINT8 | PchPmSlpLanLowDc |
| | Offset 0x0652 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. More...
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| |
| UINT8 | PchPmPwrBtnOverridePeriod |
| | Offset 0x0653 - PCH Pm Pwr Btn Override Period PCH power button override period. More...
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| UINT8 | PchPmDisableDsxAcPresentPulldown |
| | Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. More...
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| |
| UINT8 | PchPmCapsuleResetType |
| | Offset 0x0655 - PCH Pm Capsule Reset Type Deprecated: Determines type of reset issued during UpdateCapsule(). More...
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| |
| UINT8 | PchPmDisableNativePowerButton |
| | Offset 0x0656 - PCH Pm Disable Native Power Button Power button native mode disable. More...
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| |
| UINT8 | PchPmSlpS0Enable |
| | Offset 0x0657 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. More...
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| |
| UINT8 | PchPmMeWakeSts |
| | Offset 0x0658 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. More...
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| |
| UINT8 | PchPmWolOvrWkSts |
| | Offset 0x0659 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. More...
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| |
| UINT8 | PchPmPwrCycDur |
| | Offset 0x065A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. More...
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UINT8 | UnusedUpdSpace18 |
| | Offset 0x065B.
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| |
| UINT8 | PchPort61hEnable |
| | Offset 0x065C - PCH Port 61h Config Enable/Disable Used for the emulation feature for Port61h read. More...
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| |
| UINT8 | SataPwrOptEnable |
| | Offset 0x065D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. More...
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| |
| UINT8 | EsataSpeedLimit |
| | Offset 0x065E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. More...
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UINT8 | SataSpeedLimit |
| | Offset 0x065F - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
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UINT8 | SataPortsHotPlug [8] |
| | Offset 0x0660 - Enable SATA Port HotPlug Enable SATA Port HotPlug.
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| |
|
UINT8 | SataPortsInterlockSw [8] |
| | Offset 0x0668 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw.
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| |
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UINT8 | SataPortsExternal [8] |
| | Offset 0x0670 - Enable SATA Port External Enable SATA Port External.
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| |
|
UINT8 | SataPortsSpinUp [8] |
| | Offset 0x0678 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device.
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| |
|
UINT8 | SataPortsSolidStateDrive [8] |
| | Offset 0x0680 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD.
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| |
|
UINT8 | SataPortsEnableDitoConfig [8] |
| | Offset 0x0688 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
|
| |
| UINT8 | SataPortsDmVal [8] |
| | Offset 0x0690 - Enable SATA Port DmVal DITO multiplier. More...
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| |
|
UINT16 | SataPortsDitoVal [8] |
| | Offset 0x0698 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625.
|
| |
|
UINT8 | SataPortsZpOdd [8] |
| | Offset 0x06A8 - Enable SATA Port ZpOdd Support zero power ODD.
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| |
| UINT8 | SataRstRaidAlternateId |
| | Offset 0x06B0 - PCH Sata Rst Raid Alternate Id Enable RAID Alternate ID. More...
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| |
| UINT8 | SataRstRaid0 |
| | Offset 0x06B1 - PCH Sata Rst Raid0 RAID0. More...
|
| |
| UINT8 | SataRstRaid1 |
| | Offset 0x06B2 - PCH Sata Rst Raid1 RAID1. More...
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| |
| UINT8 | SataRstRaid10 |
| | Offset 0x06B3 - PCH Sata Rst Raid10 RAID10. More...
|
| |
| UINT8 | SataRstRaid5 |
| | Offset 0x06B4 - PCH Sata Rst Raid5 RAID5. More...
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| |
| UINT8 | SataRstIrrt |
| | Offset 0x06B5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology. More...
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| |
| UINT8 | SataRstOromUiBanner |
| | Offset 0x06B6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. More...
|
| |
|
UINT8 | SataRstOromUiDelay |
| | Offset 0x06B7 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
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| UINT8 | SataRstHddUnlock |
| | Offset 0x06B8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. More...
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| |
| UINT8 | SataRstLedLocate |
| | Offset 0x06B9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. More...
|
| |
| UINT8 | SataRstIrrtOnly |
| | Offset 0x06BA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. More...
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| |
| UINT8 | SataRstSmartStorage |
| | Offset 0x06BB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. More...
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UINT8 | SataRstPcieEnable [3] |
| | Offset 0x06BC - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping.
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UINT8 | SataRstPcieStoragePort [3] |
| | Offset 0x06BF - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
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| |
| UINT8 | SataRstPcieDeviceResetDelay [3] |
| | Offset 0x06C2 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. More...
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| |
| UINT8 | PchScsEmmcHs400TuningRequired |
| | Offset 0x06C5 - Enable eMMC HS400 Training Determine if HS400 Training is required. More...
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| |
| UINT8 | PchScsEmmcHs400DllDataValid |
| | Offset 0x06C6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid. More...
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| |
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UINT8 | PchScsEmmcHs400RxStrobeDll1 |
| | Offset 0x06C7 - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
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| |
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UINT8 | PchScsEmmcHs400TxDataDll |
| | Offset 0x06C8 - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
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| |
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UINT8 | PchScsEmmcHs400DriverStrength |
| | Offset 0x06C9 - I/O Driver Strength I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm.
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| |
| UINT8 | SerialIoGpio |
| | Offset 0x06CA - Enable Pch Serial IO GPIO Determines if enable Serial IO GPIO. More...
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| |
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UINT8 | SerialIoI2cVoltage [6] |
| | Offset 0x06CB - IO voltage for I2C controllers Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V.
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| |
|
UINT8 | SerialIoSpiCsPolarity [2] |
| | Offset 0x06D1 - SPI ChipSelect signal polarity Selects SPI ChipSelect signal polarity.
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| |
|
UINT8 | SerialIoUartHwFlowCtrl [3] |
| | Offset 0x06D3 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS linesh.
|
| |
| UINT8 | SerialIoDebugUartNumber |
| | Offset 0x06D6 - UART Number For Debug Purpose UART number for debug purpose. More...
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| |
|
UINT8 | SerialIoEnableDebugUartAfterPost |
| | Offset 0x06D7 - Enable Debug UART Controller Enable debug UART controller after post.
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| UINT8 | PchSirqEnable |
| | Offset 0x06D8 - Enable Serial IRQ Determines if enable Serial IRQ. More...
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| UINT8 | PchSirqMode |
| | Offset 0x06D9 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. More...
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UINT8 | PchStartFramePulse |
| | Offset 0x06DA - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
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| UINT8 | PchThermalDeviceEnable |
| | Offset 0x06DB - Enable Thermal Device Enable Thermal Device. More...
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UINT16 | PchT0Level |
| | Offset 0x06DC - Thermal Throttling Custimized T0Level Value Custimized T0Level value.
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UINT16 | PchT1Level |
| | Offset 0x06DE - Thermal Throttling Custimized T1Level Value Custimized T1Level value.
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UINT16 | PchT2Level |
| | Offset 0x06E0 - Thermal Throttling Custimized T2Level Value Custimized T2Level value.
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| UINT8 | PchTsmicLock |
| | Offset 0x06E2 - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip. More...
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| UINT8 | PchTTEnable |
| | Offset 0x06E3 - Enable The Thermal Throttle Enable the thermal throttle function. More...
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| UINT8 | PchTTState13Enable |
| | Offset 0x06E4 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. More...
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| UINT8 | PchTTLock |
| | Offset 0x06E5 - Thermal Throttle Lock Thermal Throttle Lock. More...
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| UINT8 | TTSuggestedSetting |
| | Offset 0x06E6 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. More...
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UINT8 | TTCrossThrottling |
| | Offset 0x06E7 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS.
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| UINT8 | PchDmiTsawEn |
| | Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. More...
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| UINT8 | DmiSuggestedSetting |
| | Offset 0x06E9 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. More...
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UINT8 | DmiTS0TW |
| | Offset 0x06EA - Thermal Sensor 0 Target Width Thermal Sensor 0 Target Width.
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UINT8 | DmiTS1TW |
| | Offset 0x06EB - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width.
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UINT8 | DmiTS2TW |
| | Offset 0x06EC - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width.
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UINT8 | DmiTS3TW |
| | Offset 0x06ED - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width.
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UINT8 | SataP0T1M |
| | Offset 0x06EE - Port 0 T1 Multipler Port 0 T1 Multipler.
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UINT8 | SataP0T2M |
| | Offset 0x06EF - Port 0 T2 Multipler Port 0 T2 Multipler.
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|
UINT8 | SataP0T3M |
| | Offset 0x06F0 - Port 0 T3 Multipler Port 0 T3 Multipler.
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| |
|
UINT8 | SataP0TDisp |
| | Offset 0x06F1 - Port 0 Tdispatch Port 0 Tdispatch.
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UINT8 | SataP1T1M |
| | Offset 0x06F2 - Port 1 T1 Multipler Port 1 T1 Multipler.
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UINT8 | SataP1T2M |
| | Offset 0x06F3 - Port 1 T2 Multipler Port 1 T2 Multipler.
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UINT8 | SataP1T3M |
| | Offset 0x06F4 - Port 1 T3 Multipler Port 1 T3 Multipler.
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UINT8 | SataP1TDisp |
| | Offset 0x06F5 - Port 1 Tdispatch Port 1 Tdispatch.
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|
UINT8 | SataP0Tinact |
| | Offset 0x06F6 - Port 0 Tinactive Port 0 Tinactive.
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| UINT8 | SataP0TDispFinit |
| | Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. More...
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UINT8 | SataP1Tinact |
| | Offset 0x06F8 - Port 1 Tinactive Port 1 Tinactive.
|
| |
| UINT8 | SataP1TDispFinit |
| | Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. More...
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| |
| UINT8 | SataThermalSuggestedSetting |
| | Offset 0x06FA - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. More...
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| |
| UINT8 | PchMemoryThrottlingEnable |
| | Offset 0x06FB - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. More...
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| |
|
UINT8 | PchMemoryPmsyncEnable [2] |
| | Offset 0x06FC - Memory Thermal Throttling Enable Memory Thermal Throttling.
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|
UINT8 | PchMemoryC0TransmitEnable [2] |
| | Offset 0x06FE - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
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UINT8 | PchMemoryPinSelection [2] |
| | Offset 0x0700 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
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UINT16 | PchTemperatureHotLevel |
| | Offset 0x0702 - Thermal Device Temperature Decides the temperature.
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| |
| UINT8 | PchDisableComplianceMode |
| | Offset 0x0704 - Disable XHCI Compliance Mode This policy will disable XHCI compliance mode on all ports. More...
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| |
|
UINT8 | Usb2OverCurrentPin [16] |
| | Offset 0x0705 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N.
|
| |
|
UINT8 | Usb3OverCurrentPin [10] |
| | Offset 0x0715 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N.
|
| |
| UINT8 | Early8254ClockGatingEnable |
| | Offset 0x071F - Enable 8254 Static Clock Gating in early POST time Set 8254CGE=1 is required for C11 support. More...
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| |
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UINT8 | SataRstOptaneMemory |
| | Offset 0x0720 - PCH Sata Rst Optane Memory Optane Memory $EN_DIS.
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|
UINT8 | SataRstCpuAttachedStorage |
| | Offset 0x0721 - PCH SATA RST CPU attached storage RST CPU attached storage $EN_DIS.
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UINT8 | UnusedUpdSpace19 [2] |
| | Offset 0x0722.
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| UINT32 | PchPcieDeviceOverrideTablePtr |
| | Offset 0x0724 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. More...
|
| |
| UINT8 | EnableTcoTimer |
| | Offset 0x0728 - Enable TCO timer. More...
|
| |
| UINT8 | EcCmdProvisionEav |
| | Offset 0x0729 - EcCmdProvisionEav Ephemeral Authorization Value default values. More...
|
| |
| UINT8 | EcCmdLock |
| | Offset 0x072A - EcCmdLock EcCmdLock default values. More...
|
| |
|
UINT8 | UnusedUpdSpace20 [5] |
| | Offset 0x072B.
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| |
| UINT64 | SendEcCmd |
| | Offset 0x0730 - SendEcCmd SendEcCmd function pointer. More...
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| |
|
UINT64 | BgpdtHash [4] |
| | Offset 0x0738 - BgpdtHash[4] BgpdtHash values.
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| |
|
UINT64 | BiosGuardModulePtr |
| | Offset 0x0758 - BiosGuardModulePtr BiosGuardModulePtr default values.
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| |
|
UINT32 | BiosGuardAttr |
| | Offset 0x0760 - BiosGuardAttr BiosGuardAttr default values.
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UINT8 | SgxSinitNvsData |
| | Offset 0x0764 - SgxSinitNvsData SgxSinitNvsData default values.
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| |
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UINT8 | UnusedUpdSpace21 [3] |
| | Offset 0x0765.
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| |
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UINT64 | SgxEpoch0 |
| | Offset 0x0768 - SgxEpoch0 SgxEpoch0 default values.
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| |
|
UINT64 | SgxEpoch1 |
| | Offset 0x0770 - SgxEpoch1 SgxEpoch1 default values.
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UINT8 | MeUnconfigOnRtcClear |
| | Offset 0x0778 - Enable/Disable ME Unconfig on RTC clear Enable(Default): Enable ME Unconfig On Rtc Clear, Disable: Disable ME Unconfig On Rtc Clear $EN_DIS.
|
| |
| UINT8 | MeUnconfigIsValid |
| | Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear. More...
|
| |
| UINT8 | IslVrCmd |
| | Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues. More...
|
| |
|
UINT8 | ReservedFspsUpd [5] |
| | Offset 0x077B.
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| |
1.8.10