Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide: DoxygenFspIntegrationGuide.h Source File

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1 /** @file
2  This file contains doxygen KabylakeFspIntegration Guide
3 
4 @copyright
5  Copyright (c) 2015 - 2018 Intel Corporation. All rights reserved
6  This software and associated documentation (if any) is furnished
7  under a license and may only be used or copied in accordance
8  with the terms of the license. Except as permitted by such
9  license, no part of this software or documentation may be
10  reproduced, stored in a retrieval system, or transmitted in any
11  form or by any means without the express written consent of
12  Intel Corporation.
13  This file contains an 'Intel Peripheral Driver' and uniquely
14  identified as "Intel Reference Module" and is
15  licensed for Intel CPUs and chipsets under the terms of your
16  license agreement with Intel or your vendor. This file may
17  be modified by the user, subject to additional terms of the
18  license agreement
19 **/
20 
21 /** @mainpage INTRODUCTION
22 
23 # 1 Introduction
24 
25 ## 1.1 Purpose
26  The purpose of this document is to describe the steps required to integrate the Intel® Firmware
27  Support Package (FSP) into a boot loader solution. It supports Kabylake platforms with Kabylake/Skylake
28  processor and Sunrise point Platform Controller Hub (PCH).</P>
29 
30 ## 1.2 Intended Audience
31  This document is targeted at all platform and system developers who need to consume FSP binaries
32  in their boot loader solutions. This includes, but is not limited to: system BIOS developers, boot
33  loader developers, system integrators, as well as end users.</P>
34 
35 ## 1.3 Related Documents
36  - *Platform Initialization (PI) Specification v1.4* located at http://www.uefi.org/specifications
37  - *UEFI Specification v2.5* located at http://www.uefi.org/specifications
38  - *Intel&reg; Firmware Support Package: External Architecture Specification (EAS) v2.0* located at
39  http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf
40  - *Boot Setting File Specification (BSF) v1.0* https://firmware.intel.com/sites/default/files/BSF_1_0.pdf
41  - *Binary Configuration Tool for Intel&reg; Firmware Support Package* available at http://www.intel.com/fsp
42 
43 ## 1.4 Acronyms and Terminology
44 
45 Acronym | Definition
46 --------|-----------
47 BCT | Binary Configuration Tool
48 BSF | Boot Setting File
49 BSP | Boot Strap Processor
50 BWG | BIOS Writer&apos;s Guide
51 CAR | Cache As Ram
52 CRB | Customer Reference Board
53 FIT | Firmware Interface Table
54 FSP | Firmware Support Package
55 FSP API | Firmware Support Package Interface
56 FW | Firmware
57 PCH | Platform Controller Hub
58 PMC | Power Management Controller
59 SBSP | System BSP
60 SMI | System Management Interrupt
61 SMM | System Management Mode
62 SPI | Serial Peripheral Interface
63 TSEG | Memory Reserved at the Top of Memory to be used as SMRAM
64 UPD | Updatable Product Data
65 
66 **/
67 
68 /** @page fsp_overview FSP OVERVIEW
69 # FSP Overview
70 ## 2.1 Technical Overview
71  The *Intel&reg; Firmware Support Package (FSP)* provides chipset and processor initialization in a
72  format that can easily be incorporated into many existing boot loaders.
73 
74  The FSP will perform the necessary initialization steps as documented in the BWG including
75  initialization of the CPU, memory controller, chipset and certain bus interfaces, if necessary.
76 
77  FSP is not a stand-alone boot loader; therefore it needs to be integrated into a host boot loader
78  to carry out other boot loader functions, such as: initializing non-Intel components, conducting
79  bus enumeration, and discovering devices in the system and all industry standard initialization.
80 
81  The FSP binary can be integrated easily into many different boot loaders, such as Coreboot, EDKII etc.
82  and also into the embedded OS directly.
83 
84  Below are some required steps for the integration:
85 
86  - **Customizing**
87  The static FSP configuration parameters are part of the FSP binary and can be customized by external
88  tools that will be provided by Intel.
89 
90  - **Rebasing**
91  The FSP is not Position Independent Code (PIC) and the whole FSP has to be rebased if it is placed
92  at a location which is different from the preferred address during build process.
93 
94  - **Placing**
95  Once the FSP binary is ready for integration, the boot loader build process needs to be modified to
96  place this FSP binary at the specific rebasing location identified above.
97 
98  - **Interfacing**
99  The boot loader needs to add code to setup the operating environment for the FSP, call the FSP with
100  correct parameters and parse the FSP output to retrieve the necessary information returned by the FSP.
101 
102 ## 2.2 FSP Distribution Package
103  - The FSP distribution package contains the following:
104  - FSP Binary
105  - FSP Integration Guide
106  - BSF Configuration File
107  - Data Structure Header File
108 
109  - The FSP configuration utility called BCT is available as a separate package.
110  It can be downloaded from link mentioned in Section 1.3.
111 
112 ### 2.2.1 Package Layout
113  - **Docs (Auto generated)**
114  - Kabylake_FSP_Integration_Guide.pdf (this doc)
115  - Kabylake_FSP_Integration_Guide.chm
116 
117  - **Include**
118  - FsptUpd.h, FspmUpd.h and FspsUpd.h (FSP UPD structure and related definitions)
119  - GpioSampleDef.h (Sample enum definitions for Gpio table)
120  - KabylakeFspBinPkg.dec (EDKII declaration file for package)
121  - Fsp.bsf (BSF file for configuring the data using BCT tool)
122  - Fsp.fd (FSP Binary)
123 **/
124 
125 /** @page fsp_integration FSP INTEGRATION
126 # 3 FSP Integration
127 
128 ## 3.1 Assumptions Used in this Document
129  The FSP for the Kabylake platform is built with a preferred base address of 0xFFF40000 and so the
130  reference code provided in the document assumes that the FSP is placed at this base address during
131  the final boot loader build. Users may rebase the FSP binary at a different location with
132  Intel&apos;s Binary Configuration Tool (BCT) before integrating to the boot loader.
133 
134  For other assumptions and conventions, please refer section 8 in the FSP External Architecture
135  Specification version 2.0.
136 
137 ## 3.2 Boot Flow
138  Please refer Chapter 7 in the FSP External Architecture Specification version 2.0 for Boot flow chart.
139 
140 ## 3.3 FSP INFO Header
141  The FSP has an Information Header that provides critical information that is required by the
142  bootloader to successfully interface with the FSP. The structure of the FSP Information Header
143  is documented in the FSP External Architecture Specification version 2.0 with a HeaderRevision of 3.
144 
145 ## 3.4 FSP Image ID and Revision
146  FSP information header contains an Image ID field and an Image Revision field that provide the
147  identification and revision information of the FSP binary. It is important to verify these fields
148  while integrating the FSP as API parameters could change over different FSP IDs and revisions.
149  All the FSP FV segments(FSP-T, FSP-M and FSP-S) must have same FSP Image ID and revision number,
150  using FV segments with different revision numbers in a single FSP image is not valid. The FSP
151  API parameters documented in this integration guide are applicable for the Image ID and
152  Revision specified as below.
153 
154  The current FSP ImageId string in the FSP information header is <strong>$KBLFSP$</strong> and the
155  ImageRevision field is **0x03060000.(3.6.0.0)**.
156 
157 ## 3.5 FSP Global Data
158  FSP uses some amount of TempRam area to store FSP global data which contains some critical data like
159  pointers to FSP information headers and UPD configuration regions, FSP/Bootloader stack pointers
160  required for stack switching etc. HPET Timer register(2) 0xFED00148 is reserved to store address
161  of this global data, and hence boot loader should not use this register for any other purpose.
162  If TempRAM initialization is done by boot loader, then HPET has to be initialized to the base so
163  that access to this register will work fine.
164 
165 ## 3.6 FSP APIs
166  This release of the Kabylake FSP supports the all APIs required by the FSP External
167  Architecture Specification version 2.0.
168  The FSP information header contains the address offset for these APIs. Register usage is
169  described in the FSP External Architecture Specification version 2.0. Any usage not described
170  by the specification is described in the individual sections below.
171 
172  The below sections will highlight any changes that are specific to this FSP release.
173 
174 ### 3.6.1 TempRamInit API
175  Please refer Chapter 8.5 in the FSP External Architecture Specification version 2.0 for complete
176  details including the prototype, parameters and return value details for this API.
177 
178  TempRamInit does basic early initialization primarily setting up temporary RAM using cache. It
179  returns ECX pointing to beginning of temporary memory and EDX pointing to end of temporary memory + 1.
180  The total temporary ram currently available is from 0xFEF0_0000 to 0xFEF4_0000 out of which
181  0xFEF0_0000(ECX) to 0xFEF3_FF00(EDX) is usable area for both bootloader and FSP binary, remaining
182  0x100 bytes of space reserved by FSP for TempRamInit if temporary RAM initialization is done by FSP.
183 
184  **TempRamInit** also sets up the code caching of the region passed CodeCacheBase and CodeCacheLength,
185  which are input parameters to TempRamInitApi. if 0 is passed in for CodeCacheBase, the base used will
186  be 4 GB - 1 - length to be code cached instead of starting from CodeCacheBase.
187  @note: when programming MTRR CodeCacheLength will be reduced, if SKU LLC size is smaller than the requested.
188 
189  It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to
190  each microcode update. The microcode update is loaded for all logical processors before reset
191  vector. If more than microcode update for the CPU is present, the microcode update with the
192  latest revision is loaded.
193 
194  **FSPT_UPD.MicrocodeRegionBase** and **FSPT_UPD.MicrocodeRegionLength** are input parameters to TempRamInit API.
195  If these values are 0, FSP will not attempt to update microcode. If a region is passed, then if a newer
196  microcode update revision is in the region, it will be loaded by the FSP.
197 
198  MTRRs are programmed to the default values to have the following memory map:
199 
200  Memory range | Cache Attribute
201  ---------------------------------------|-----------------
202  0xFEF00000 - 0x00040000 | Write back
203  CodeCacheBase - CodeCacheLength | Write protect
204 
205 ### 3.6.2 FspMemoryInit API
206  Please refer to Chapter 8.6 in the FSP external Architecture Specification version 2.0 for the
207  prototype, parameters and return value details for this API.
208 
209  The **FspmUpdPtr** is pointer to **FSPM_UPD** structure which is described in header file FspmUpd.h.
210 
211  Boot Loader must pass valid CAR region for FSP stack use through **FSPM_UPD.FspmArchUpd.StackBase**
212  and **FSPM_UPD.FspmArchUpd.StackSize** UPDs.
213 
214  The minimum FSP stack size required for this revision of FSP is 160KB, stack base is 0xFEF17F00 by default.
215 
216  The base address of HECI device (Bus 0, Device 22, Function 0) is required to be initialized prior
217  to perform FspMemoryInit flow. The default address is programmed to 0xFED1A000.
218 
219  Calculate memory map determining memory regions TSEG, IED, GTT, BDSM, ME stolen, Uncore PMRR, IOT,
220  MOT, DPR, REMAP, TOLUD, TOUUD. Programming will be done at a different time.
221 
222 #### 3.6.3 TempRamExit API
223  Please refer to Chapter 8.7 in the FSP external Architecture Specification version 2.0 for the
224  prototype, parameters and return value details for this API.
225 
226  If Boot Loader initializes the Temporary RAM (CAR) and skip calling **TempRamInit API**, it is expected that
227  bootloader must skip calling this API and bootloader will tear down the temporary memory area setup in the
228  cache and bring the cache to normal mode of operation.
229 
230  This revision of FSP doesn't have any fields/structure to pass as parameter for this API.
231  Pass Null for *TempRamExitParamPtr*.
232 
233  At the end of *TempRamExit* the original code and data caching are disabled. FSP will reconfigure all MTRRs
234  as described in the table below for performance optimization.
235 
236  Memory range | Cache Attribute
237  ---------------------------------------|-----------------
238  0x00000000 - 0x0009FFFF | Write back
239  0x000C0000 - Top of Low Memory | Write back
240  0xFF800000 - 0xFFFFFFFF (Flash region) | Write protect
241  0x1000000000 - Top of High Memory | Write back
242 
243  If the boot loader wish to reconfigure the MTRRs differently, it can be overridden immediately after this API call.
244 
245 ### 3.6.4 FspSiliconInit API
246  Please refer to Chapter 8.8 in the FSP external Architecture Specification version 2.0 for the
247  prototype, parameters and return value details for this API.
248 
249  The *FspsUpdPtr* is pointer to **FSPS_UPD** structure which is described in header file FspsUpd.h.
250 
251  It is expected that boot loader will program MTRRs for SBSP as needed after **TempRamExit** but before
252  entering **FspSiliconInit**. If MTRRs are not programmed properly, the boot performance
253  might be impacted.
254 
255  The region of 0x5_8000 - 0x5_8FFF is used by FspSilicionInit for starting APs. If this data
256  is important to bootloader, then bootloader needs to preserve it before calling FspSilicionInit.
257 
258  It is a requirement for bootloader to have Firmware Interface Table (FIT), which contains pointers
259  to each microcode. The microcode is loaded for all cores before reset vector. If more than one
260  microcode update for the CPU is present, the latest revision is loaded.
261 
262  MicrocodeRegionBase and MicrocodeRegionLength are both input parameters to TempRamInit
263  and UPD for SiliconInit API. UPD has priority and will be searched for a later revision
264  than TempRamInit. If MicrocodeRegionBase and MicrocodeRegionLength values are 0, FSP will
265  not attempt to update the microcode. If a microcode region is passed, and if a later
266  revision of microcode is present in this region, FSP will load it.
267 
268  FSP initializes PCH audio including selecting HD Audio verb table and initializes Codec.
269 
270  PCH required initialization is done for the following HECI, USB, HSIO, Integrated Sensor Hub,
271  Display, Sky Cam, Camera, PCI Express, Vt-d, straps (cores, hyper-threading, BIST, ..)
272 
273  FSP initializes CPU features: XD, VMX, AES, IED, HDC, x(2)Apic, Intel&reg; Processor Trace,
274  Three strike counter, Machine check, Cache pre-fetchers, Core PMRR, Power management.
275 
276  Initializes HECI, DMI, Internal Graphics. Publish EFI_PEI_GRAPHICS_INFO_HOB during normal boot
277  but this HOB will not be published during S3 resume as FSP will not launch the PEI Graphics PEIM
278  during S3 resume.
279 
280  Programs SA Bars: MchBar, DmiBar, EpBar, GdxcBar, EDRAM (if supported). Please refer to section
281  2.8 (MemoryMap) for the corresponding Bar values. GttMmadr (0xDF000000) and GmAdr(0xC0000000)
282  are temporarily programmed and cleared after use in FSP.
283 
284  On normal boot CPU S3 Resume Data HOB is produced in this phase. This CPU S3 Resume Data HOB is described
285  in section 4.4. Unless UPD SkipMpInit is enabled, on S3 resume, this data (not the entire HOB) must be passed through
286  UPD CpuS3ResumeData, and optionally final S3 boot MTRRs is passed through UPD CpuS3ResumeMtrrData. During S3
287  resume unless SkipMpInit is enabled, GDT base and length and IDT base and length on APs are programmed
288  to that of the BSP.
289 
290 ### 3.6.5 NotifyPhase API
291  Please refer Chapter 8.9 in the FSP External Architecture Specification version 2.0 for the
292  prototype, parameters and return value details for this API.
293 
294 #### 3.6.5.1 PostPciEnumeration Notification
295  This phase *EnumInitPhaseAfterPciEnumeration* is to be called after PCI enumeration but before
296  execution of third party code such as option ROMs. Currently, nothing is done in this phase,
297  but in the future updates, programming may be done in this phase.
298 
299 #### 3.6.5.2 ReadyToBoot Notification
300  This phase *EnumInitPhaseReadyToBoot* is to be called before giving control to boot. It includes some
301  final initialization steps recommended by the BWG, including power management settings, Send ME Message
302  EOP (End of Post).
303 
304 #### 3.6.5.3 EndOfFirmware Notification
305  This phase *EnumInitEndOfFirmware* is to be called before the firmware/preboot environment transfers
306  management of all system resources to the OS or next level execution environment. It includes final locking
307  of chipset registers
308 
309 ## 3.7 Memory Map
310  Below diagram represents the memory map allocated by FSP including the FSP specific regions.
311 ![System Memory Map](KabylakeMemoryMap.jpg)
312 
313 ## 3.8 Porting recommendation
314  Here listed some notes or recommendation when porting with FSP.
315 
316 ### 3.8.1 Locking PAM register
317  FSP 2.0 introduced EndOfFirmware Notify phase callback which is a recommended place for locking PAM registers
318  so FSP by default implemented this way. If it is still too early to lock PAM registers then the PAM locking code
319  inside FSP can be disabled by UPD -> FSP_S_TEST_CONFIG -> SkipPamLock or SA policy -> _SI_PREMEM_POLICY_STRUCT
320  -> SA_MISC_PEI_CONFIG -> SkipPamLock, and platform or wrapper code should do the PAM locking right before booting
321  OS (so do it outside FSP instead) by programming one PCI config space register as below.
322 
323  This PAM locking step has to been applied in all boot paths including S3 resume.To lock PAM regsiter:
324 
325 ~~~
326  MmioOr32 (B0: D0: F0: Register 0x80, BIT0)
327 ~~~
328 
329 ### 3.8.2 Locking SMRAM register
330  Since SMRAM locking is recommended to be locked before any 3rd party OpROM execution and highly depending on platform code implementation, the FSP code by default will not lock it.
331  The platform or FSP Wrapper code should lock SMRAM by below programming step before any 3rd partiy OpRom execution (and should be locked in S3 resume right before OS waking vector).
332 ~~~
333  PciOr8 (B0: D0: F0: Register 0x88, BIT4); Note: it must be programmed by CF8/CFC Standard PCI access mechanism. (MMIO access will not work)
334 ~~~
335 
336 ### 3.8.3 Locking SMI register
337  Global SMI bit is recommended to be locked before any 3rd party OpROM execution and highly depending on platform code implementation after SMM configuration. FSP by default will not lock it.
338  Boot loader is responsible for locking below regsiters after SMM configuration.
339  Set AcpiBase + 0x30[0] to 1b to enable global SMI.
340  Set PMC PCI offset A0h[4] = 1b to lock SMI.
341 
342 ### 3.8.4 Verify below settings are correct for your platforms
343 
344  Settings | Values
345  ---------------------------------|------------------------
346  PCIEXBAR_BASE_ADDRESS | 0xE0000000 -> PciExBar
347  MCH_BASE_ADDRESS | 0xFED10000 -> MchBar
348  DMI_BASE_ADDRESS | 0xFED18000 -> DmiBar
349  EP_BASE_ADDRESS | 0xFED19000 -> EpBar
350  EDRAM_BASE_ADDRESS | 0xFED80000 -> EdramBar
351  DEFAULT_OPTION_ROM_TEMP_BAR | 0x80000000 -> OpRomScanTempMmioBar
352  DEFAULT_OPTION_ROM_TEMP_MEM_LIMIT| 0xC0000000 -> OpRomScanTempMmioLimit
353  @note:\n
354  - It is recommended that you do not change these settings as it may require significant changes to the System Agent reference code.\n
355  - Those memory regions should be reserved from any memory service functions in platform code so it will not cause any conflict when other modules or drivers allocating memory resource.
356  - Boot Loader can use different value for PCIEXBAR_BASE_ADDRESS either by modifying the UPD (under FSP-T) or by overriding the PCIEXBAR (B0:D0:F0:R60h) before calling FspMemoryInit Api.
357  - Boot Loader should avoid using conflicting address when reprogramming PCIEXBAR_BASE_ADDRESS than the recommended one.
358 
359 ### 3.8.5 FSP_STATUS_RESET_REQUIRED
360  As per FSP External Architecture Specification version 2.0, Any reset required in the FSP flow will
361  be reported as return status FSP_STATUS_RESET_REQUIREDx by the API.It is the bootloader responsibility to reset the system according to the reset type requested.
362 
363  Below table specifies the return status returned by FSP API and the requested reset type.
364 
365 FSP_STATUS_RESET_REQUIRED Code | Reset Type requested
366 -------------------------------|----------------------
367 0x40000001 | Cold Reset
368 0x40000002 | Warm Reset
369 0x40000003 | Global Reset - Puts the system to Global reset through Heci or Full Reset through PCH
370 0x40000004 | Reserved
371 0x40000005 | Reserved
372 0x40000006 | Reserved
373 0x40000007 | Reserved
374 0x40000008 | Reserved
375 **/
376 /** @page fsp_output FSP OUTPUT
377 # 4 FSP Output
378  The FSP builds a series of data structures called the Hand-Off-Blocks (HOBs) as it progresses
379  through initializing the silicon.
380  Please refer to the Platform Initialization (PI) Specification - Volume 3: Shared Architectural
381  Elements specification for PI Architectural HOBs.Please refer Chapter 9 in the FSP External Architecture
382  Specification version 2.0 for details about FSP Architectural HOBs.
383 
384  Below section describe the HOBs not covered in the above two specifications.
385 
386 ## 4.1 SMRAM Resource Descriptor HOB
387  The FSP will report the system SMRAM T-SEG range through a generic resource HOB if T-SEG is
388  enabled. The owner field of the HOB identifies the owner as T-SEG.
389 
390 ~~~
391 #define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
392 { 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }
393 ~~~
394 
395 ## 4.2 SMBIOS INFO HOB
396  The FSP will report the SMBIOS through a HOB with below GUID. This information can be consumed
397  by the bootloader to produce the SMBIOS tables. These structures are included as part of MemInfoHob.h , SmbiosCacheInfoHob.h & SmbiosProcessorInfoHob.h.
398  Note: The Smbios Cache Info Hob & Smbios Processor Info Hob won't be published on S3 boot.
399 ~~~
400 #define SI_MEMORY_INFO_DATA_HOB_GUID \
401 { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } };
402 
403 typedef struct {
404  MrcDimmStatus Status; ///< See MrcDimmStatus for the definition of this field.
405  UINT8 DimmId;
406  UINT32 DimmCapacity; ///< DIMM size in MBytes.
407  UINT16 MfgId;
408  UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
409  UINT8 RankInDimm; ///< The number of ranks in this DIMM.
410  UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
411  UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
412  UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
413  UINT8 SpdSave[MAX_SPD_SAVE_DATA]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
414 } DIMM_INFO;
415 
416 typedef struct {
417  UINT8 Status; ///< Indicates whether this channel should be used.
418  UINT8 ChannelId;
419  UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
420  MRC_CH_TIMING Timing[MAX_PROFILE]; ///< The channel timing values.
421  DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
422 } CHANNEL_INFO;
423 
424 typedef struct {
425  UINT8 Status; ///< Indicates whether this controller should be used.
426  UINT16 DeviceId; ///< The PCI device id of this memory controller.
427  UINT8 RevisionId; ///< The PCI revision id of this memory controller.
428  UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
429  CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
430 } CONTROLLER_INFO;
431 
432 typedef struct {
433  EFI_HOB_GUID_TYPE EfiHobGuidType;
434  UINT8 Revision;
435  UINT16 DataWidth;
436  /// As defined in SMBIOS 3.0 spec
437  /// Section 7.18.2 and Table 75
438  UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
439  UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.
440  /// As defined in SMBIOS 3.0 spec
441  /// Section 7.17.3 and Table 72
442  UINT8 ErrorCorrectionType;
443 
444  SiMrcVersion Version;
445  UINT32 FreqMax;
446  BOOLEAN EccSupport;
447  UINT8 MemoryProfile;
448  UINT32 TotalPhysicalMemorySize;
449  BOOLEAN XmpProfileEnable;
450  UINT8 Ratio;
451  UINT8 RefClk;
452  UINT32 VddVoltage[MAX_PROFILE];
453  CONTROLLER_INFO Controller[MAX_NODE];
454 } MEMORY_INFO_DATA_HOB;
455 
456 #define SI_MEMORY_PLATFORM_DATA_HOB \
457  { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }
458 
459 typedef struct {
460  UINT8 Revision;
461  UINT8 Reserved[3];
462  UINT32 BootMode;
463  UINT32 TsegSize;
464  UINT32 TsegBase;
465  UINT32 PrmrrSize;
466  UINT32 PrmrrBase;
467  UINT32 GttBase;
468  UINT32 MmioSize;
469  UINT32 PciEBaseAddress;
470 } MEMORY_PLATFORM_DATA;
471 
472 typedef struct {
473  EFI_HOB_GUID_TYPE EfiHobGuidType;
474  MEMORY_PLATFORM_DATA Data;
475  UINT8 *Buffer;
476 } MEMORY_PLATFORM_DATA_HOB;
477 
478 #define SMBIOS_CACHE_INFO_HOB_GUID \
479  { 0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7} }
480 
481 ///
482 /// SMBIOS Cache Info HOB Structure
483 ///
484 typedef struct {
485  UINT16 ProcessorSocketNumber;
486  UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
487  UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
488  UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36
489  UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
490  UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
491  UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
492  UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
493  UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
494  UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3
495  UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4
496  UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5
497  ///String Buffer - each string terminated by NULL "0x00"
498  ///String buffer terminated by double NULL "0x0000"
499 } SMBIOS_CACHE_INFO;
500 
501 #define SMBIOS_PROCESSOR_INFO_HOB_GUID \
502  { 0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71} }
503 ///
504 /// SMBIOS Processor Info HOB Structure
505 ///
506 typedef struct {
507  UINT16 TotalNumberOfSockets;
508  UINT16 CurrentSocketNumber;
509  UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1
510  ///This info is used for both ProcessorFamily and ProcessorFamily2 fields
511  ///See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2
512  UINT16 ProcessorFamily;
513  UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
514  UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3
515  UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
516  UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4
517  UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
518  UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
519  UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21
520  UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5
521  ///This info is used for both CoreCount & CoreCount2 fields
522  /// See detailed description in SMBIOS Spec v3.0 Section 7.5.6
523  UINT16 CoreCount;
524  ///This info is used for both CoreEnabled & CoreEnabled2 fields
525  ///See detailed description in SMBIOS Spec v3.0 Section 7.5.7
526  UINT16 EnabledCoreCount;
527  ///This info is used for both ThreadCount & ThreadCount2 fields
528  /// See detailed description in SMBIOS Spec v3.0 Section 7.5.8
529  UINT16 ThreadCount;
530  UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9
531  /// String Buffer - each string terminated by NULL "0x00"
532  /// String buffer terminated by double NULL "0x0000"
533 } SMBIOS_PROCESSOR_INFO;
534 ~~~
535 
536 ## 4.3 CHIPSETINIT INFO HOB
537  The FSP will report the ChipsetInit CRC through a HOB with below GUID. This information can be consumed
538  by the bootloader to check if ChipsetInit CRC is matched between BIOS and ME. These structures are included
539  as part of FspsUpd.h
540 
541 ~~~
542 #define CHIPSETINIT_INFO_HOB_GUID \
543 { 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }}
544 
545 ///
546 /// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
547 ///
548 typedef struct {
549  UINT8 Revision;
550  UINT8 Rsvd[3];
551  UINT16 MeChipInitCrc;
552  UINT16 BiosChipInitCrc;
553 } CHIPSET_INIT_INFO;
554 
555 ~~~
556 
557 ## 4.4 CPU S3 Resume Data HOB
558  The FSP will report the CPU S3 Resume Data through a GUIDED HOB with below GUID. This data (not the entire HOB) must be passed during S3 resume passed
559  in UPD CpuS3ResumeData except if UPD SkipMpInit is enabled.
560 
561 ~~~
562 #define CPU_S3_RESUME_DATA_HOB_GUID \
563 { 0x3972d4c1, 0xf206, 0x463f, { 0x80, 0xa4, 0xd9, 0x62, 0x79, 0x0a, 0xe5, 0x49 }}
564 ~~~
565 
566 **/
567 /** @page fsp_postcode FSP POSTCODE
568 # 5 FSP PostCode
569  The FSP outputs 16 bit postcode to indicate which API and in which module the execution is happening.
570 
571  Bit Range | Description
572  -------------------|------------
573  Bit15 - Bit12 (X) | used to indicate the phase/api under which the code is executing
574  Bit11 - Bit8 (Y) | used to indicate the module
575  Bit7 (ZZ bit 7) | reserved for error
576  Bit6 - Bit0 (ZZ) | individual codes
577 
578 ## 5.1 PostCode Info
579  Below diagram represents the 16 bit PostCode usage in FSP.
580 
581 @dot
582 digraph structs {
583  node [shape=record, width=3, height=1];
584  struct1 [style=bold,label="<f0> X|<f1> Y|<f2> ZZ"];
585  struct2 [label="<f0> FSP API - 4 BITS (one Digit)\n
586 F - Tempraminit /SEC \l
587 E - Reserved \l
588 D - MemoryInit /Pre-Memory \l
589 C - Reserved \l
590 B - Tempramexit \l
591 A - Reserved \l
592 9 - SiliconInit /Post Memory \l
593 8 - Reserved \l
594 7 - Reserved \l
595 6 - Notify / Post PCIE Enumeration \l
596 5 - Reserved \l
597 4 - Notify / Ready To Boot \l
598 3 - Reserved \l
599 2 - Notify / End Of Firmware \l
600 1-0 - Reserved\l"];
601  struct3 [label="<f0> Module - 4 BITS (one digit)\n
602 7 - Gfx PEIM \l
603 8 - FSP Common Code \l
604 9 - Silicon Common Code \l
605 A - System Agent \l
606 B - PCH \l
607 C - CPU \l
608 D - MRC \l
609 E - ME-BIOS \l
610 F - Reserved \l
611 "];
612  struct4 [label="<f0>Individual Codes\n
613 0x00 - API Entry \l
614 0x7F - API Exit \l
615 
616 (Bit7 reserved for error)\l
617  "];
618  struct1:f0 -> struct2:f0;
619  struct1:f1 -> struct3:f0;
620  struct1:f2 -> struct4:f0;
621 }
622 @enddot
623 
624 
625 ### 5.1.1 TempRamInit API Status Codes (0xFxxx)
626 
627 PostCode | Module | Description
628 ---------|--------|-----------------
629 0x0000 | FSP | TempRamInit API Entry (The change in upper byte is due to not enabling of the Port81 early in the boot)
630 0x007F | FSP | TempRamInit API Exit
631 
632 ### 5.1.2 FspMemoryInit API Status Codes (0xDxxx)
633 
634 PostCode | Module | Description
635 ---------|--------|-----------------
636 0xD800 | FSP | FspMemoryInit API Entry
637 0xD87F | FSP | FSpMemoryInit API Exit
638 0xDA00 | SA | Pre-Mem SaInit Entry
639 0xDA01 | SA | DeviceConfigurePreMem Start
640 0xDA02 | SA | OverrideDev0Did Start
641 0xDA04 | SA | OverrideDev2Did Start
642 0xDA06 | SA | Programming SA Bars
643 0xDA08 | SA | Install SA HOBs
644 0xDA0A | SA | Reporting SA PCIe code version
645 0xDA0C | SA | SaSvInit Start
646 0xDA10 | SA | Initializing DMI
647 0xDA1F | SA | Initializing DMI/OPI Max PayLoad Size
648 0xDA20 | SA | Initializing SwitchableGraphics
649 0xDA30 | SA | Initializing SA PCIe
650 0xDA3F | SA | Programming PEG credit values Start
651 0xDA40 | SA | Initializing DMI Tc/Vc mapping
652 0xDA42 | SA | CheckOffboardPcieVga
653 0xDA44 | SA | CheckAndInitializePegVga
654 0xDA50 | SA | Initializing Graphics
655 0xDA7F | SA | Pre-Mem SaInit Exit
656 0xDB00 | PCH | PCH API Entry
657 0xDC00 | CPU | Pre-Mem Entry
658 0xDC7F | CPU | Pre-Mem Exit
659 
660 ### 5.1.3 TempRamExit API Status Codes (0xBxxx)
661 
662 PostCode | Module | Description
663 ---------|--------|-----------------
664 0xB800 | FSP | TempRamExit API Entry
665 0xB87F | FSP | TempRamExit API Exit
666 
667 ### 5.1.3 FspSiliconInit API Status Codes (0x9xxx)
668 
669 PostCode | Module | Description
670 ---------|--------|-----------------
671 0x9800 | FSP | FspSiliconInit API Entry
672 0x987F | FSP | FspSiliconInit API Exit
673 0x9A00 | SA | Post-Mem SaInit Entry
674 0x9A01 | SA | DeviceConfigure Start
675 0x9A02 | SA | UpdateSaHobPostMem Start
676 0x9A03 | SA | Initializing Pei Display
677 0x9A04 | SA | PeiGraphicsNotifyCallback Entry
678 0x9A05 | SA | CallPpiAndFillFrameBuffer
679 0x9A06 | SA | GraphicsPpiInit
680 0x9A07 | SA | GraphicsPpiGetMode
681 0x9A08 | SA | FillFrameBufferAndShowLogo
682 0x9A0F | SA | PeiGraphicsNotifyCallback Exit
683 0x9A10 | SA | Initializing SA Overclocking
684 0x9A14 | SA | Initializing SA SkyCam device
685 0x9A16 | SA | Initializing SA GMM device
686 0x9A18 | SA | Internal Device and Misc Configurations
687 0x9A1A | SA | SaProgramLlcWays Start
688 0x9A20 | SA | Initializing PciExpressInitPostMem
689 0x9A30 | SA | Initializing Vtd
690 0x9A32 | SA | Initializing Pavp
691 0x9A34 | SA | PeiInstallSmmAccessPpi Start
692 0x9A36 | SA | EdramWa Start
693 0x9A4F | SA | Post-Mem SaInit Exit
694 0x9A50 | SA | SaSecurityLock Start
695 0x9A5F | SA | SaSecurityLock End
696 0x9A60 | SA | SaSResetComplete Entry
697 0x9A61 | SA | Set BIOS_RESET_CPL to indicate all configurations complete
698 0x9A62 | SA | SaSvInit2 Start
699 0x9A63 | SA | GraphicsPmInit Start
700 0x9A64 | SA | SaPeiPolicyDump Start
701 0x9A6F | SA | SaSResetComplete Exit
702 0x9A70 | SA | SaS3ResumeAtEndOfPei Callback Entry
703 0x9A7F | SA | SaS3ResumeAtEndOfPei Callback Exit
704 0x9B7F | PCH | Post-Mem ScInit Entry
705 0x9B01 | PCH | Post-Mem Program HSIO ModPHY settings
706 0x9B02 | PCH | Post-Mem SMBus configuration
707 0x9B03 | PCH | Post-Mem LPC configuration
708 0x9B04 | PCH | Post-Mem SATA initizalization
709 0x9B05 | PCH | Post-Mem PCIe initizalization
710 0x9B06 | PCH | Post-Mem xHCI initizalization
711 0x9B07 | PCH | Post-Mem xDCI initizalization
712 0x9B08 | PCH | Post-Mem HD Audio initizalization
713 0x9B09 | PCH | Post-Mem GMM configuration
714 0x9B0A | PCH | Post-Mem LPSS initizalization
715 0x9B0B | PCH | Post-Mem SCS initizalization
716 0x9B0C | PCH | Post-Mem ISH initizalization
717 0x9B0D | PCH | Post-Mem ITSS configuration
718 0x9B40 | PCH | Post-Mem OnEndOfPEI Entry
719 0x9B4F | PCH | Post-Mem OnEndOfPEI Exit
720 0x9B7F | PCH | Post-Mem ScInit Exit
721 0x9C00 | CPU | Post-Mem Entry
722 0x9C7F | CPU | Post-Mem Exit
723 
724 ### 5.1.4 NotifyPhase API Status Codes (0x6xxx)
725 
726 PostCode | Module | Description
727 ---------|--------|-----------------
728 0x6800 | FSP | NotifyPhase API Entry
729 0x687F | FSP | NotifyPhase API Exit
730 
731 **/
Generated on Thu Jun 28 2018 21:44:49 for Kabylake Intel(R) Firmware Support Package (FSP) Integration Guide by   doxygen 1.8.10
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