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GD32F10x USB-Device
V1.0.0
GD32F10x USB-Device
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Macros | |
| #define | CTLR_STIE (0x8000) |
| CTLR control register bits definitions. More... | |
| #define | CTLR_PMOUIE (0x4000) |
| #define | CTLR_ERRIE (0x2000) |
| #define | CTLR_WKUPIE (0x1000) |
| #define | CTLR_SPSIE (0x0800) |
| #define | CTLR_RSTIE (0x0400) |
| #define | CTLR_SOFIE (0x0200) |
| #define | CTLR_ESOFIE (0x0100) |
| #define | CTLR_RSREQ (0x0010) |
| #define | CTLR_SETSPS (0x0008) |
| #define | CTLR_LOWM (0x0004) |
| #define | CTLR_CLOSE (0x0002) |
| #define | CTLR_SETRST (0x0001) |
| #define | IFR_STIF (0x8000) |
| IFR interrupt events bits definitions. More... | |
| #define | IFR_PMOUIF (0x4000) |
| #define | IFR_ERRIF (0x2000) |
| #define | IFR_WKUPIF (0x1000) |
| #define | IFR_SPSIF (0x0800) |
| #define | IFR_RSTIF (0x0400) |
| #define | IFR_SOFIF (0x0200) |
| #define | IFR_ESOFIF (0x0100) |
| #define | IFR_DIR (0x0010) |
| #define | IFR_EPNUM (0x000F) |
| #define | CLR_STIF (~IFR_STIF) |
| #define | CLR_PMOUIF (~IFR_PMOUIF) |
| #define | CLR_ERRIF (~IFR_ERRIF) |
| #define | CLR_WKUPIF (~IFR_WKUPIF) |
| #define | CLR_SPSIF (~IFR_SPSIF) |
| #define | CLR_RSTIF (~IFR_RSTIF) |
| #define | CLR_SOFIF (~IFR_SOFIF) |
| #define | CLR_ESOFIF (~IFR_ESOFIF) |
| #define | SR_RXDP (0x8000) |
| SR status register bit definitions. More... | |
| #define | SR_RXDM (0x4000) |
| #define | SR_LOCK (0x2000) |
| #define | SR_SOFLN (0x1800) |
| #define | SR_FCNT (0x07FF) |
| #define | AR_USBEN (0x80) |
| AR device address register bit definitions. More... | |
| #define | AR_USBADDR (0x7F) |
| #define | EPRX_ST (0x8000) |
| EPCSR endpoint control and status register bit definitions. More... | |
| #define | EPRX_DTG (0x4000) |
| #define | EPRX_STA (0x3000) |
| #define | EP_SETUP (0x0800) |
| #define | EP_CTL (0x0600) |
| #define | EP_KCTL (0x0100) |
| #define | EPTX_ST (0x0080) |
| #define | EPTX_DTG (0x0040) |
| #define | EPTX_STA (0x0030) |
| #define | EP_AR (0x000F) |
| #define | EPCSR_MASK (EPRX_ST|EP_SETUP|EP_CTL|EP_KCTL|EPTX_ST|EP_AR) |
| Endpoint control and status register mask (no toggle fields) | |
| #define | EP_BULK (0x0000) |
| EP_CTL[1:0] endpoint type control. More... | |
| #define | EP_CONTROL (0x0200) |
| #define | EP_ISO (0x0400) |
| #define | EP_INTERRUPT (0x0600) |
| #define | EP_CTL_MASK (~EP_CTL & EPCSR_MASK) |
| #define | EPKCTL_MASK (~EP_KCTL & EPCSR_MASK) |
| Endpoint kind control mask. | |
| #define | EPTX_DISABLED (0x0000) |
| TX_STA[1:0] status for Tx transfer. More... | |
| #define | EPTX_STALL (0x0010) |
| #define | EPTX_NAK (0x0020) |
| #define | EPTX_VALID (0x0030) |
| #define | EPTX_DTGMASK (EPTX_STA | EPCSR_MASK) |
| #define | EPRX_DISABLED (0x0000) |
| RX_STA[1:0] status for Rx transfer. More... | |
| #define | EPRX_STALL (0x1000) |
| #define | EPRX_NAK (0x2000) |
| #define | EPRX_VALID (0x3000) |
| #define | EPRX_DTGMASK (EPRX_STA | EPCSR_MASK) |
| #define | EPRXCNTR_BLKSIZ (0x8000) |
| Endpoint receive/transmission counter register bit definitions. | |
| #define | EPRXCNTR_BLKNUM (0x7C00) |
| #define | EPRXCNTR_CNT (0x03FF) |
| #define | EPTXCNTR_CNT (0x03FF) |
| #define | BLKSIZE_OFFSET (0x01) |
| Endpoint receive/transmission counter register bit offset. | |
| #define | BLKNUM_OFFSET (0x05) |
| #define | RXCNT_OFFSET (0x0A) |
| #define | TXCNT_OFFSET (0x0A) |
| #define | BLKSIZE32_MASK (0x1f) |
| #define | BLKSIZE2_MASK (0x01) |
| #define | BLKSIZE32_OFFSETMASK (0x05) |
| #define | BLKSIZE2_OFFSETMASK (0x01) |
Detailed Description
Macro Definition Documentation
| #define AR_USBADDR (0x7F) |
USB device address
Definition at line 191 of file usb_regs.h.
| #define AR_USBEN (0x80) |
AR device address register bit definitions.
USB module enable
Definition at line 190 of file usb_regs.h.
| #define CLR_ERRIF (~IFR_ERRIF) |
Clear Error flag
Definition at line 171 of file usb_regs.h.
| #define CLR_ESOFIF (~IFR_ESOFIF) |
Clear Expected start of frame flag
Definition at line 176 of file usb_regs.h.
| #define CLR_PMOUIF (~IFR_PMOUIF) |
Clear Packet memory overrun/underrun flag
Definition at line 170 of file usb_regs.h.
| #define CLR_RSTIF (~IFR_RSTIF) |
Clear Reset flag
Definition at line 174 of file usb_regs.h.
| #define CLR_SOFIF (~IFR_SOFIF) |
Clear Start of frame flag
Definition at line 175 of file usb_regs.h.
| #define CLR_SPSIF (~IFR_SPSIF) |
Clear Suspend state flag
Definition at line 173 of file usb_regs.h.
| #define CLR_STIF (~IFR_STIF) |
Clear Successful transfer flag
Definition at line 169 of file usb_regs.h.
| #define CLR_WKUPIF (~IFR_WKUPIF) |
Clear Wake up flag
Definition at line 172 of file usb_regs.h.
| #define CTLR_CLOSE (0x0002) |
Goes to close state
Definition at line 152 of file usb_regs.h.
| #define CTLR_ERRIE (0x2000) |
Error interrupt enable Mask
Definition at line 143 of file usb_regs.h.
| #define CTLR_ESOFIE (0x0100) |
Expected start of frame interrupt enable Mask
Definition at line 148 of file usb_regs.h.
| #define CTLR_LOWM (0x0004) |
Low-power mode at suspend state
Definition at line 151 of file usb_regs.h.
| #define CTLR_PMOUIE (0x4000) |
Packet memory overrun/underrun interrupt enable Mask
Definition at line 142 of file usb_regs.h.
| #define CTLR_RSREQ (0x0010) |
Resume request
Definition at line 149 of file usb_regs.h.
| #define CTLR_RSTIE (0x0400) |
Reset interrupt enable Mask
Definition at line 146 of file usb_regs.h.
| #define CTLR_SETRST (0x0001) |
Set USB reset
Definition at line 153 of file usb_regs.h.
| #define CTLR_SETSPS (0x0008) |
Set suspend state
Definition at line 150 of file usb_regs.h.
| #define CTLR_SOFIE (0x0200) |
Start of frame interrupt enable Mask
Definition at line 147 of file usb_regs.h.
| #define CTLR_SPSIE (0x0800) |
Suspend state interrupt enable Mask
Definition at line 145 of file usb_regs.h.
| #define CTLR_STIE (0x8000) |
CTLR control register bits definitions.
Successful transfer interrupt enable Mask
Definition at line 141 of file usb_regs.h.
| #define CTLR_WKUPIE (0x1000) |
Wakeup interrupt enable Mask
Definition at line 144 of file usb_regs.h.
| #define EP_AR (0x000F) |
EndPoint address
Definition at line 205 of file usb_regs.h.
| #define EP_BULK (0x0000) |
| #define EP_CONTROL (0x0200) |
CONTROL endpoint
Definition at line 216 of file usb_regs.h.
| #define EP_CTL (0x0600) |
EndPoint type control
Definition at line 200 of file usb_regs.h.
| #define EP_INTERRUPT (0x0600) |
INTERRUPT endpoint
Definition at line 218 of file usb_regs.h.
| #define EP_ISO (0x0400) |
ISOCHRONOUS endpoint
Definition at line 217 of file usb_regs.h.
| #define EP_KCTL (0x0100) |
EndPoint kind control
Definition at line 201 of file usb_regs.h.
| #define EP_SETUP (0x0800) |
EndPoint setup transaction completed
Definition at line 199 of file usb_regs.h.
| #define EPRX_DISABLED (0x0000) |
RX_STA[1:0] status for Rx transfer.
Ignore all reception requests of this endpoint
Definition at line 238 of file usb_regs.h.
| #define EPRX_DTG (0x4000) |
EndPoint reception data PID toggle
Definition at line 197 of file usb_regs.h.
| #define EPRX_NAK (0x2000) |
NAK handshake status
Definition at line 240 of file usb_regs.h.
| #define EPRX_ST (0x8000) |
EPCSR endpoint control and status register bit definitions.
EndPoint reception successful transferred
Definition at line 196 of file usb_regs.h.
| #define EPRX_STA (0x3000) |
EndPoint reception status bits
Definition at line 198 of file usb_regs.h.
| #define EPRX_STALL (0x1000) |
STALL handshake status
Definition at line 239 of file usb_regs.h.
| #define EPRX_VALID (0x3000) |
Enable endpoint for reception
Definition at line 241 of file usb_regs.h.
| #define EPTX_DISABLED (0x0000) |
TX_STA[1:0] status for Tx transfer.
Ignore all transmission request of this endpoint
Definition at line 229 of file usb_regs.h.
| #define EPTX_DTG (0x0040) |
EndPoint transmission data toggle
Definition at line 203 of file usb_regs.h.
| #define EPTX_NAK (0x0020) |
NAK handshake status
Definition at line 231 of file usb_regs.h.
| #define EPTX_ST (0x0080) |
EndPoint transmission successful transfer
Definition at line 202 of file usb_regs.h.
| #define EPTX_STA (0x0030) |
EndPoint transmission transfers status bits
Definition at line 204 of file usb_regs.h.
| #define EPTX_STALL (0x0010) |
STALL handshake status
Definition at line 230 of file usb_regs.h.
| #define EPTX_VALID (0x0030) |
Enable this endpoint for transmission
Definition at line 232 of file usb_regs.h.
| #define IFR_DIR (0x0010) |
Direction of transaction (read-only bit)
Definition at line 166 of file usb_regs.h.
| #define IFR_EPNUM (0x000F) |
Endpoint number (read-only bit)
Definition at line 167 of file usb_regs.h.
| #define IFR_ERRIF (0x2000) |
Error interrupt flag (clear-only bit)
Definition at line 160 of file usb_regs.h.
| #define IFR_ESOFIF (0x0100) |
Expected start of frame interrupt flag(clear-only bit)
Definition at line 165 of file usb_regs.h.
| #define IFR_PMOUIF (0x4000) |
Packet memory overrun/underrun interrupt flag (clear-only bit)
Definition at line 159 of file usb_regs.h.
| #define IFR_RSTIF (0x0400) |
Reset interrupt flag (clear-only bit)
Definition at line 163 of file usb_regs.h.
| #define IFR_SOFIF (0x0200) |
Start of frame interrupt flag (clear-only bit)
Definition at line 164 of file usb_regs.h.
| #define IFR_SPSIF (0x0800) |
Suspend state interrupt flag (clear-only bit)
Definition at line 162 of file usb_regs.h.
| #define IFR_STIF (0x8000) |
IFR interrupt events bits definitions.
Successful transfer interrupt flag (read only bit)
Definition at line 158 of file usb_regs.h.
| #define IFR_WKUPIF (0x1000) |
Wakeup interrupt flag (clear-only bit)
Definition at line 161 of file usb_regs.h.
| #define SR_FCNT (0x07FF) |
Frame number count
Definition at line 185 of file usb_regs.h.
| #define SR_LOCK (0x2000) |
Locked the USB
Definition at line 183 of file usb_regs.h.
| #define SR_RXDM (0x4000) |
Receive data - line status
Definition at line 182 of file usb_regs.h.
| #define SR_RXDP (0x8000) |
SR status register bit definitions.
Receive data + line status
Definition at line 181 of file usb_regs.h.
| #define SR_SOFLN (0x1800) |
SOF lost number
Definition at line 184 of file usb_regs.h.
Generated on Fri Feb 6 2015 14:56:36 for GD32F10x USB-Device by
1.8.8