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STM32F0xx Standard Peripherals Firmware Library
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STM32F0xx_StdPeriph_Templates/system_stm32f0xx.c
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00001 /** 00002 ****************************************************************************** 00003 * @file system_stm32f0xx.c 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 05-December-2014 00007 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. 00008 * This file contains the system clock configuration for STM32F0xx devices, 00009 * and is generated by the clock configuration tool 00010 * STM32F0xx_Clock_Configuration_V1.0.1.xls 00011 * 00012 * 1. This file provides two functions and one global variable to be called from 00013 * user application: 00014 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 00015 * and Divider factors, AHB/APBx prescalers and Flash settings), 00016 * depending on the configuration made in the clock xls tool. 00017 * This function is called at startup just after reset and 00018 * before branch to main program. This call is made inside 00019 * the "startup_stm32f0xx.s" file. 00020 * 00021 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 00022 * by the user application to setup the SysTick 00023 * timer or configure other parameters. 00024 * 00025 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 00026 * be called whenever the core clock is changed 00027 * during program execution. 00028 * 00029 * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. 00030 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to 00031 * configure the system clock before to branch to main program. 00032 * 00033 * 3. If the system clock source selected by user fails to startup, the SystemInit() 00034 * function will do nothing and HSI still used as system clock source. User can 00035 * add some code to deal with this issue inside the SetSysClock() function. 00036 * 00037 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define 00038 * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or 00039 * through PLL, and you are using different crystal you have to adapt the HSE 00040 * value to your own configuration. 00041 * 00042 * 5. This file configures the system clock as follows: 00043 *============================================================================= 00044 *============================================================================= 00045 * System Clock source | PLL(HSE) 00046 *----------------------------------------------------------------------------- 00047 * SYSCLK(Hz) | 48000000 00048 *----------------------------------------------------------------------------- 00049 * HCLK(Hz) | 48000000 00050 *----------------------------------------------------------------------------- 00051 * AHB Prescaler | 1 00052 *----------------------------------------------------------------------------- 00053 * APB Prescaler | 1 00054 *----------------------------------------------------------------------------- 00055 * HSE Frequency(Hz) | 8000000 00056 *---------------------------------------------------------------------------- 00057 * PLLMUL | 6 00058 *----------------------------------------------------------------------------- 00059 * PREDIV | 1 00060 *----------------------------------------------------------------------------- 00061 * Flash Latency(WS) | 1 00062 *----------------------------------------------------------------------------- 00063 * Prefetch Buffer | ON 00064 *----------------------------------------------------------------------------- 00065 ****************************************************************************** 00066 * @attention 00067 * 00068 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 00069 * 00070 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00071 * You may not use this file except in compliance with the License. 00072 * You may obtain a copy of the License at: 00073 * 00074 * http://www.st.com/software_license_agreement_liberty_v2 00075 * 00076 * Unless required by applicable law or agreed to in writing, software 00077 * distributed under the License is distributed on an "AS IS" BASIS, 00078 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00079 * See the License for the specific language governing permissions and 00080 * limitations under the License. 00081 * 00082 ****************************************************************************** 00083 */ 00084 00085 /** @addtogroup CMSIS 00086 * @{ 00087 */ 00088 00089 /** @addtogroup stm32f0xx_system 00090 * @{ 00091 */ 00092 00093 /** @addtogroup STM32F0xx_System_Private_Includes 00094 * @{ 00095 */ 00096 00097 #include "stm32f0xx.h" 00098 00099 /** 00100 * @} 00101 */ 00102 00103 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions 00104 * @{ 00105 */ 00106 00107 /** 00108 * @} 00109 */ 00110 00111 /** @addtogroup STM32F0xx_System_Private_Defines 00112 * @{ 00113 */ 00114 /** 00115 * @} 00116 */ 00117 00118 /** @addtogroup STM32F0xx_System_Private_Macros 00119 * @{ 00120 */ 00121 00122 /** 00123 * @} 00124 */ 00125 00126 /** @addtogroup STM32F0xx_System_Private_Variables 00127 * @{ 00128 */ 00129 uint32_t SystemCoreClock = 48000000; 00130 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 00131 00132 /** 00133 * @} 00134 */ 00135 00136 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes 00137 * @{ 00138 */ 00139 00140 static void SetSysClock(void); 00141 00142 /** 00143 * @} 00144 */ 00145 00146 /** @addtogroup STM32F0xx_System_Private_Functions 00147 * @{ 00148 */ 00149 00150 /** 00151 * @brief Setup the microcontroller system. 00152 * Initialize the Embedded Flash Interface, the PLL and update the 00153 * SystemCoreClock variable. 00154 * @param None 00155 * @retval None 00156 */ 00157 void SystemInit (void) 00158 { 00159 /* Set HSION bit */ 00160 RCC->CR |= (uint32_t)0x00000001; 00161 00162 #if defined(STM32F051) 00163 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ 00164 RCC->CFGR &= (uint32_t)0xF8FFB80C; 00165 #else 00166 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ 00167 RCC->CFGR &= (uint32_t)0x08FFB80C; 00168 #endif /* STM32F051 */ 00169 00170 /* Reset HSEON, CSSON and PLLON bits */ 00171 RCC->CR &= (uint32_t)0xFEF6FFFF; 00172 00173 /* Reset HSEBYP bit */ 00174 RCC->CR &= (uint32_t)0xFFFBFFFF; 00175 00176 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ 00177 RCC->CFGR &= (uint32_t)0xFFC0FFFF; 00178 00179 /* Reset PREDIV1[3:0] bits */ 00180 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; 00181 00182 /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ 00183 RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; 00184 00185 /* Reset HSI14 bit */ 00186 RCC->CR2 &= (uint32_t)0xFFFFFFFE; 00187 00188 /* Disable all interrupts */ 00189 RCC->CIR = 0x00000000; 00190 00191 /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ 00192 SetSysClock(); 00193 } 00194 00195 /** 00196 * @brief Update SystemCoreClock according to Clock Register Values 00197 * The SystemCoreClock variable contains the core clock (HCLK), it can 00198 * be used by the user application to setup the SysTick timer or configure 00199 * other parameters. 00200 * 00201 * @note Each time the core clock (HCLK) changes, this function must be called 00202 * to update SystemCoreClock variable value. Otherwise, any configuration 00203 * based on this variable will be incorrect. 00204 * 00205 * @note - The system frequency computed by this function is not the real 00206 * frequency in the chip. It is calculated based on the predefined 00207 * constant and the selected clock source: 00208 * 00209 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 00210 * 00211 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 00212 * 00213 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 00214 * or HSI_VALUE(*) multiplied/divided by the PLL factors. 00215 * 00216 * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value 00217 * 8 MHz) but the real value may vary depending on the variations 00218 * in voltage and temperature. 00219 * 00220 * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value 00221 * 8 MHz), user has to ensure that HSE_VALUE is same as the real 00222 * frequency of the crystal used. Otherwise, this function may 00223 * have wrong result. 00224 * 00225 * - The result of this function could be not correct when using fractional 00226 * value for HSE crystal. 00227 * @param None 00228 * @retval None 00229 */ 00230 void SystemCoreClockUpdate (void) 00231 { 00232 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; 00233 00234 /* Get SYSCLK source -------------------------------------------------------*/ 00235 tmp = RCC->CFGR & RCC_CFGR_SWS; 00236 00237 switch (tmp) 00238 { 00239 case 0x00: /* HSI used as system clock */ 00240 SystemCoreClock = HSI_VALUE; 00241 break; 00242 case 0x04: /* HSE used as system clock */ 00243 SystemCoreClock = HSE_VALUE; 00244 break; 00245 case 0x08: /* PLL used as system clock */ 00246 /* Get PLL clock source and multiplication factor ----------------------*/ 00247 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 00248 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 00249 pllmull = ( pllmull >> 18) + 2; 00250 00251 if (pllsource == 0x00) 00252 { 00253 /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 00254 SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 00255 } 00256 else 00257 { 00258 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; 00259 /* HSE oscillator clock selected as PREDIV1 clock entry */ 00260 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 00261 } 00262 break; 00263 default: /* HSI used as system clock */ 00264 SystemCoreClock = HSI_VALUE; 00265 break; 00266 } 00267 /* Compute HCLK clock frequency ----------------*/ 00268 /* Get HCLK prescaler */ 00269 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 00270 /* HCLK clock frequency */ 00271 SystemCoreClock >>= tmp; 00272 } 00273 00274 /** 00275 * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash 00276 * settings. 00277 * @note This function should be called only once the RCC clock configuration 00278 * is reset to the default reset state (done in SystemInit() function). 00279 * @param None 00280 * @retval None 00281 */ 00282 static void SetSysClock(void) 00283 { 00284 __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 00285 00286 /******************************************************************************/ 00287 /* PLL (clocked by HSE) used as System clock source */ 00288 /******************************************************************************/ 00289 00290 /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ 00291 /* Enable HSE */ 00292 RCC->CR |= ((uint32_t)RCC_CR_HSEON); 00293 00294 /* Wait till HSE is ready and if Time out is reached exit */ 00295 do 00296 { 00297 HSEStatus = RCC->CR & RCC_CR_HSERDY; 00298 StartUpCounter++; 00299 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 00300 00301 if ((RCC->CR & RCC_CR_HSERDY) != RESET) 00302 { 00303 HSEStatus = (uint32_t)0x01; 00304 } 00305 else 00306 { 00307 HSEStatus = (uint32_t)0x00; 00308 } 00309 00310 if (HSEStatus == (uint32_t)0x01) 00311 { 00312 /* Enable Prefetch Buffer and set Flash Latency */ 00313 FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; 00314 00315 /* HCLK = SYSCLK */ 00316 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 00317 00318 /* PCLK = HCLK */ 00319 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; 00320 00321 /* PLL configuration */ 00322 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 00323 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); 00324 00325 /* Enable PLL */ 00326 RCC->CR |= RCC_CR_PLLON; 00327 00328 /* Wait till PLL is ready */ 00329 while((RCC->CR & RCC_CR_PLLRDY) == 0) 00330 { 00331 } 00332 00333 /* Select PLL as system clock source */ 00334 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 00335 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 00336 00337 /* Wait till PLL is used as system clock source */ 00338 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) 00339 { 00340 } 00341 } 00342 else 00343 { /* If HSE fails to start-up, the application will have wrong clock 00344 configuration. User can add here some code to deal with this error */ 00345 } 00346 } 00347 00348 /** 00349 * @} 00350 */ 00351 00352 /** 00353 * @} 00354 */ 00355 00356 /** 00357 * @} 00358 */ 00359 00360 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/