STM32F0xx Standard Peripherals Firmware Library: system_stm32f0xx.c File Reference

CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. This file contains the system clock configuration for STM32F0xx devices, and is generated by the clock configuration tool STM32F0xx_Clock_Configuration_V1.0.0.xls.

Author:

MCD Application Team

Version:

V1.4.0

Date:

24-July-2014 1. This file provides two functions and one global variable to be called from user application:

• SystemInit(): Setups the system clock (System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers and Flash settings), depending on the configuration made in the clock xls tool. This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f0xx.s" file.

• SystemCoreClock variable: Contains the core clock (HCLK), it can be used by the user application to setup the SysTick timer or configure other parameters.

• SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution.

2. After each device reset the HSI (8 MHz Range) is used as system clock source. Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to configure the system clock before to branch to main program.

3. If the system clock source selected by user fails to startup, the SystemInit() function will do nothing and HSI still used as system clock source. User can add some code to deal with this issue inside the SetSysClock() function.

4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define in "stm32f0xx.h" file. When HSE is used as system clock source, directly or through PLL, and you are using different crystal you have to adapt the HSE value to your own configuration.

5. This file configures the system clock as follows: ============================================================================= System Clock Configuration ============================================================================= System Clock source | PLL(HSE) ----------------------------------------------------------------------------- SYSCLK | 48000000 Hz ----------------------------------------------------------------------------- HCLK | 48000000 Hz ----------------------------------------------------------------------------- AHB Prescaler | 1 ----------------------------------------------------------------------------- APB1 Prescaler | 1 ----------------------------------------------------------------------------- APB2 Prescaler | 1 ----------------------------------------------------------------------------- HSE Frequency | 8000000 Hz ----------------------------------------------------------------------------- PLL MUL | 6 ----------------------------------------------------------------------------- VDD | 3.3 V ----------------------------------------------------------------------------- Flash Latency | 1 WS ----------------------------------------------------------------------------- =============================================================================

Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

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Definition in file STM32F0xx_StdPeriph_Examples/IWDG/IWDG_Reset/system_stm32f0xx.c.