STM32F0xx Standard Peripherals Firmware Library: system_stm32f0xx.c Source File

STM32F0xx Standard Peripherals Library

STM32F0xx_StdPeriph_Examples/USART/USART_8xUsartsOneBoard/system_stm32f0xx.c
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00001 /**
00002   ******************************************************************************
00003   * @file    system_stm32f0xx.c
00004   * @author  MCD Application Team
00005   * @version V1.4.0
00006   * @date    24-July-2014
00007   * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
00008   *          This file contains the system clock configuration for STM32F0xx devices,
00009   *          and is generated by the clock configuration tool  
00010   *          STM32F0xx_Clock_Configuration_V1.0.1.xls
00011   *
00012   * 1.  This file provides two functions and one global variable to be called from 
00013   *     user application:
00014   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
00015   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
00016   *                      depending on the configuration made in the clock xls tool.
00017   *                      This function is called at startup just after reset and 
00018   *                      before branch to main program. This call is made inside
00019   *                      the "startup_stm32f0xx.s" file.
00020   *
00021   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
00022   *                                  by the user application to setup the SysTick 
00023   *                                  timer or configure other parameters.
00024   *
00025   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
00026   *                                 be called whenever the core clock is changed
00027   *                                 during program execution.
00028   *
00029   * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
00030   *    Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
00031   *    configure the system clock before to branch to main program.
00032   *
00033   * 3. If the system clock source selected by user fails to startup, the SystemInit()
00034   *    function will do nothing and HSI still used as system clock source. User can 
00035   *    add some code to deal with this issue inside the SetSysClock() function.
00036   *
00037   * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
00038   *    in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
00039   *    through PLL, and you are using different crystal you have to adapt the HSE
00040   *    value to your own configuration.
00041   *
00042   * 5. This file configures the system clock as follows:
00043   *=============================================================================
00044   *=============================================================================
00045   *        System Clock source                    | PLL(HSE)
00046   *-----------------------------------------------------------------------------
00047   *        SYSCLK(Hz)                             | 48000000
00048   *-----------------------------------------------------------------------------
00049   *        HCLK(Hz)                               | 48000000
00050   *-----------------------------------------------------------------------------
00051   *        AHB Prescaler                          | 1
00052   *-----------------------------------------------------------------------------
00053   *        APB Prescaler                          | 1
00054   *-----------------------------------------------------------------------------
00055   *        HSE Frequency(Hz)                      | 8000000
00056   *----------------------------------------------------------------------------
00057   *        PLLMUL                                 | 6
00058   *-----------------------------------------------------------------------------
00059   *        PREDIV                                 | 1
00060   *-----------------------------------------------------------------------------
00061   *        Flash Latency(WS)                      | 1
00062   *-----------------------------------------------------------------------------
00063   *        Prefetch Buffer                        | ON
00064   *-----------------------------------------------------------------------------
00065   ******************************************************************************
00066   * @attention
00067   *
00068   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00069   *
00070   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00071   * You may not use this file except in compliance with the License.
00072   * You may obtain a copy of the License at:
00073   *
00074   *        http://www.st.com/software_license_agreement_liberty_v2
00075   *
00076   * Unless required by applicable law or agreed to in writing, software 
00077   * distributed under the License is distributed on an "AS IS" BASIS, 
00078   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00079   * See the License for the specific language governing permissions and
00080   * limitations under the License.
00081   *
00082   ******************************************************************************
00083   */
00084 
00085 /** @addtogroup CMSIS
00086   * @{
00087   */
00088 
00089 /** @addtogroup stm32f0xx_system
00090   * @{
00091   */  
00092   
00093 /** @addtogroup STM32F0xx_System_Private_Includes
00094   * @{
00095   */
00096 
00097 #include "stm32f0xx.h"
00098 
00099 /**
00100   * @}
00101   */
00102 
00103 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
00104   * @{
00105   */
00106 
00107 /**
00108   * @}
00109   */
00110 
00111 /** @addtogroup STM32F0xx_System_Private_Defines
00112   * @{
00113   */
00114 /**
00115   * @}
00116   */
00117 
00118 /** @addtogroup STM32F0xx_System_Private_Macros
00119   * @{
00120   */
00121 
00122 /**
00123   * @}
00124   */
00125 
00126 /** @addtogroup STM32F0xx_System_Private_Variables
00127   * @{
00128   */
00129 uint32_t SystemCoreClock    = 48000000;
00130 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
00131 
00132 /**
00133   * @}
00134   */
00135 
00136 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
00137   * @{
00138   */
00139 
00140 static void SetSysClock(void);
00141 
00142 /**
00143   * @}
00144   */
00145 
00146 /** @addtogroup STM32F0xx_System_Private_Functions
00147   * @{
00148   */
00149 
00150 /**
00151   * @brief  Setup the microcontroller system.
00152   *         Initialize the Embedded Flash Interface, the PLL and update the 
00153   *         SystemCoreClock variable.
00154   * @param  None
00155   * @retval None
00156   */
00157 void SystemInit (void)
00158 {    
00159   /* Set HSION bit */
00160   RCC->CR |= (uint32_t)0x00000001;
00161 
00162   /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
00163   RCC->CFGR &= (uint32_t)0xF8FFB80C;
00164   
00165   /* Reset HSEON, CSSON and PLLON bits */
00166   RCC->CR &= (uint32_t)0xFEF6FFFF;
00167 
00168   /* Reset HSEBYP bit */
00169   RCC->CR &= (uint32_t)0xFFFBFFFF;
00170 
00171   /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
00172   RCC->CFGR &= (uint32_t)0xFFC0FFFF;
00173 
00174   /* Reset PREDIV1[3:0] bits */
00175   RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
00176 
00177   /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
00178   RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
00179 
00180   /* Reset HSI14 bit */
00181   RCC->CR2 &= (uint32_t)0xFFFFFFFE;
00182 
00183   /* Disable all interrupts */
00184   RCC->CIR = 0x00000000;
00185 
00186   /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
00187   SetSysClock();
00188 }
00189 
00190 /**
00191   * @brief  Update SystemCoreClock according to Clock Register Values
00192   *         The SystemCoreClock variable contains the core clock (HCLK), it can
00193   *         be used by the user application to setup the SysTick timer or configure
00194   *         other parameters.
00195   *
00196   * @note   Each time the core clock (HCLK) changes, this function must be called
00197   *         to update SystemCoreClock variable value. Otherwise, any configuration
00198   *         based on this variable will be incorrect.         
00199   *
00200   * @note   - The system frequency computed by this function is not the real 
00201   *           frequency in the chip. It is calculated based on the predefined 
00202   *           constant and the selected clock source:
00203   *
00204   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
00205   *                                              
00206   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
00207   *                          
00208   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
00209   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
00210   *
00211   *         (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
00212   *             8 MHz) but the real value may vary depending on the variations
00213   *             in voltage and temperature.
00214   *
00215   *         (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
00216   *              8 MHz), user has to ensure that HSE_VALUE is same as the real
00217   *              frequency of the crystal used. Otherwise, this function may
00218   *              have wrong result.
00219   *
00220   *         - The result of this function could be not correct when using fractional
00221   *           value for HSE crystal.
00222   * @param  None
00223   * @retval None
00224   */
00225 void SystemCoreClockUpdate (void)
00226 {
00227   uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
00228 
00229   /* Get SYSCLK source -------------------------------------------------------*/
00230   tmp = RCC->CFGR & RCC_CFGR_SWS;
00231   
00232   switch (tmp)
00233   {
00234     case 0x00:  /* HSI used as system clock */
00235       SystemCoreClock = HSI_VALUE;
00236       break;
00237     case 0x04:  /* HSE used as system clock */
00238       SystemCoreClock = HSE_VALUE;
00239       break;
00240     case 0x08:  /* PLL used as system clock */
00241       /* Get PLL clock source and multiplication factor ----------------------*/
00242       pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
00243       pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
00244       pllmull = ( pllmull >> 18) + 2;
00245       
00246       if (pllsource == 0x00)
00247       {
00248         /* HSI oscillator clock divided by 2 selected as PLL clock entry */
00249         SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
00250       }
00251       else
00252       {
00253         prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
00254         /* HSE oscillator clock selected as PREDIV1 clock entry */
00255         SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 
00256       }      
00257       break;
00258     default: /* HSI used as system clock */
00259       SystemCoreClock = HSI_VALUE;
00260       break;
00261   }
00262   /* Compute HCLK clock frequency ----------------*/
00263   /* Get HCLK prescaler */
00264   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
00265   /* HCLK clock frequency */
00266   SystemCoreClock >>= tmp;  
00267 }
00268 
00269 /**
00270   * @brief  Configures the System clock frequency, AHB/APBx prescalers and Flash
00271   *         settings.
00272   * @note   This function should be called only once the RCC clock configuration
00273   *         is reset to the default reset state (done in SystemInit() function).
00274   * @param  None
00275   * @retval None
00276   */
00277 static void SetSysClock(void)
00278 {
00279   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
00280 
00281 /******************************************************************************/
00282 /*            PLL (clocked by HSE) used as System clock source                */
00283 /******************************************************************************/
00284   
00285   /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
00286   /* Enable HSE */    
00287   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
00288  
00289   /* Wait till HSE is ready and if Time out is reached exit */
00290   do
00291   {
00292     HSEStatus = RCC->CR & RCC_CR_HSERDY;
00293     StartUpCounter++;  
00294   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
00295 
00296   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
00297   {
00298     HSEStatus = (uint32_t)0x01;
00299   }
00300   else
00301   {
00302     HSEStatus = (uint32_t)0x00;
00303   }  
00304 
00305   if (HSEStatus == (uint32_t)0x01)
00306   {
00307     /* Enable Prefetch Buffer and set Flash Latency */
00308     FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
00309  
00310     /* HCLK = SYSCLK */
00311     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
00312       
00313     /* PCLK = HCLK */
00314     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
00315 
00316     /* PLL configuration */
00317     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
00318     RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
00319             
00320     /* Enable PLL */
00321     RCC->CR |= RCC_CR_PLLON;
00322 
00323     /* Wait till PLL is ready */
00324     while((RCC->CR & RCC_CR_PLLRDY) == 0)
00325     {
00326     }
00327 
00328     /* Select PLL as system clock source */
00329     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
00330     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;    
00331 
00332     /* Wait till PLL is used as system clock source */
00333     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
00334     {
00335     }
00336   }
00337   else
00338   { /* If HSE fails to start-up, the application will have wrong clock 
00339          configuration. User can add here some code to deal with this error */
00340   }  
00341 }
00342 
00343 /**
00344   * @}
00345   */
00346 
00347 /**
00348   * @}
00349   */
00350 
00351 /**
00352   * @}
00353   */
00354 
00355 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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