STM32F0xx Standard Peripherals Firmware Library: main.c Source File

STM32F0xx Standard Peripherals Library

STM32F0xx_StdPeriph_Examples/TIM/TIM_ComplementarySignals/main.c
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00001 /**
00002   ******************************************************************************
00003   * @file    TIM/TIM_ComplementarySignals/main.c  
00004   * @author  MCD Application Team
00005   * @version V1.4.0
00006   * @date    24-July-2014
00007   * @brief   Main program body
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software 
00020   * distributed under the License is distributed on an "AS IS" BASIS, 
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027 
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "main.h"
00030 
00031 /** @addtogroup STM32F0xx_StdPeriph_Examples
00032   * @{
00033   */
00034 
00035 /** @addtogroup TIM_ComplementarySignals
00036   * @{
00037   */
00038 
00039 /* Private typedef -----------------------------------------------------------*/
00040 /* Private define ------------------------------------------------------------*/
00041 /* Private macro -------------------------------------------------------------*/
00042 /* Private variables ---------------------------------------------------------*/
00043 uint16_t TimerPeriod = 0;
00044 uint16_t Channel1Pulse = 0, Channel2Pulse = 0, Channel3Pulse = 0;
00045 
00046 /* Private function prototypes -----------------------------------------------*/
00047 static void TIM_Config(void);
00048 
00049 /* Private functions ---------------------------------------------------------*/
00050 
00051 /**
00052   * @brief  Main program.
00053   * @param  None
00054   * @retval None
00055   */
00056 int main(void)
00057 {
00058   /*!< At this stage the microcontroller clock setting is already configured, 
00059        this is done through SystemInit() function which is called from startup
00060        file (startup_stm32f0xx.s) before to branch to application main.
00061        To reconfigure the default setting of SystemInit() function, refer to
00062        system_stm32f0xx.c file
00063      */ 
00064 
00065   /* TIM1 Configuration */
00066   TIM_Config();
00067 
00068   /* Infinite loop */
00069   while (1)
00070   {
00071   }
00072 }
00073 
00074 /**
00075   * @brief  Configure the TIM1 Pins.
00076   * @param  None
00077   * @retval None
00078   */
00079 static void TIM_Config(void)
00080 {
00081   TIM_TimeBaseInitTypeDef  TIM_TimeBaseStructure;
00082   TIM_OCInitTypeDef  TIM_OCInitStructure;
00083   TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
00084   GPIO_InitTypeDef GPIO_InitStructure;
00085 
00086   /* GPIOA and GPIOB clocks enable */
00087   RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB, ENABLE);
00088 
00089   /* TIM1 clock enable */
00090   RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
00091                          
00092   /* GPIOA Configuration:
00093       - TIM1_CH1  pin (PA.08)  
00094       - TIM1_CH1N pin (PA.07)  
00095       - TIM1_CH2  pin (PA.09)  
00096       - TIM1_CH3  pin (PA.10)  
00097        */
00098   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10;
00099   GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
00100   GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
00101   GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
00102   GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
00103   GPIO_Init(GPIOA, &GPIO_InitStructure);
00104     
00105 
00106   /* GPIOB Configuration:
00107       - TIM1_CH2N pin (PB.00)  
00108       - TIM1_CH3N pin (PB.01)
00109       - TIM1_BKIN pin (PB.12)
00110       */
00111   GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_12;
00112   GPIO_Init(GPIOB, &GPIO_InitStructure);
00113   
00114   /* Connect TIM pins to AF2 */
00115   GPIO_PinAFConfig(GPIOA, GPIO_PinSource8, GPIO_AF_2);
00116   GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_2);
00117   GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_2);
00118   GPIO_PinAFConfig(GPIOA, GPIO_PinSource6, GPIO_AF_2);
00119   GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_2);
00120   GPIO_PinAFConfig(GPIOB, GPIO_PinSource0, GPIO_AF_2); 
00121   GPIO_PinAFConfig(GPIOB, GPIO_PinSource1, GPIO_AF_2);
00122   GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_2);
00123   
00124   /* ---------------------------------------------------------------------------
00125   TIM1 Configuration:
00126 
00127   1/ Generate 3 complementary PWM signals with 3 different duty cycles:
00128   
00129     TIM1 input clock (TIM1CLK) is set to APB2 clock (PCLK2).   
00130     TIM1CLK =  PCLK2  
00131     PCLK2 = HCLK  
00132     => TIM1CLK = HCLK = SystemCoreClock
00133   
00134     TIM1CLK is fixed to SystemCoreClock, the 
00135         TIM1 Prescaler is equal to 0 so the 
00136     TIM1 counter clock used is SystemCoreClock (48MHz).
00137 
00138     The objective is to generate PWM signal at 17.57 KHz:
00139     - TIM1_Period = (SystemCoreClock / 17570) - 1
00140 
00141     The Three Duty cycles are computed as the following description: 
00142 
00143     The channel 1 duty cycle is set to 50% so channel 1N is set to 50%.
00144     The channel 2 duty cycle is set to 25% so channel 2N is set to 75%.
00145     The channel 3 duty cycle is set to 12.5% so channel 3N is set to 87.5%.
00146     
00147     The Timer pulse is calculated as follows:
00148       - ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100
00149 
00150   2/ Insert a dead time equal to (11/SystemCoreClock) ns
00151 
00152   3/ Configure the break feature, active at High level, and using the automatic 
00153      output enable feature
00154 
00155   4/ Use the Locking parameters level1. 
00156   
00157   Note: 
00158     SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f0xx.c file.
00159     Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate()
00160     function to update SystemCoreClock variable value. Otherwise, any configuration
00161     based on this variable will be incorrect. 
00162   --------------------------------------------------------------------------- */
00163 
00164   /* Compute the value to be set in ARR register to generate signal frequency at 17.57 Khz */
00165   TimerPeriod = (SystemCoreClock / 17570) - 1;
00166 
00167   /* Compute CCR1 value to generate a duty cycle at 50% for channel 1 */
00168   Channel1Pulse = (uint16_t) (((uint32_t) 5 * (TimerPeriod - 1)) / 10);
00169 
00170   /* Compute CCR2 value to generate a duty cycle at 25%  for channel 2 */
00171   Channel2Pulse = (uint16_t) (((uint32_t) 25 * (TimerPeriod - 1)) / 100);
00172 
00173   /* Compute CCR3 value to generate a duty cycle at 12.5%  for channel 3 */
00174   Channel3Pulse = (uint16_t) (((uint32_t) 125 * (TimerPeriod - 1)) / 1000);
00175 
00176   /* Time Base configuration */
00177   TIM_TimeBaseStructure.TIM_Prescaler = 0;
00178   TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
00179   TIM_TimeBaseStructure.TIM_Period = TimerPeriod;
00180   TIM_TimeBaseStructure.TIM_ClockDivision = 0;
00181   TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
00182 
00183   TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
00184 
00185   /* Channel 1, 2 and 3 Configuration in PWM mode */
00186   TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2;
00187   TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
00188   TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
00189   TIM_OCInitStructure.TIM_Pulse = Channel1Pulse;
00190   TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
00191   TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
00192   TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
00193   TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
00194 
00195   TIM_OC1Init(TIM1, &TIM_OCInitStructure);
00196 
00197   TIM_OCInitStructure.TIM_Pulse = Channel2Pulse;
00198   TIM_OC2Init(TIM1, &TIM_OCInitStructure);
00199 
00200   TIM_OCInitStructure.TIM_Pulse = Channel3Pulse;
00201   TIM_OC3Init(TIM1, &TIM_OCInitStructure);
00202 
00203   /* Automatic Output enable, Break, dead time and lock configuration*/
00204   TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable;
00205   TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSIState_Enable;
00206   TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1;
00207   TIM_BDTRInitStructure.TIM_DeadTime = 11;
00208   TIM_BDTRInitStructure.TIM_Break = TIM_Break_Enable;
00209   TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
00210   TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Enable;
00211 
00212   TIM_BDTRConfig(TIM1, &TIM_BDTRInitStructure);
00213 
00214   /* TIM1 counter enable */
00215   TIM_Cmd(TIM1, ENABLE);
00216 
00217   /* Main Output Enable */
00218   TIM_CtrlPWMOutputs(TIM1, ENABLE);
00219 }
00220 
00221 #ifdef  USE_FULL_ASSERT
00222 
00223 /**
00224   * @brief  Reports the name of the source file and the source line number
00225   *         where the assert_param error has occurred.
00226   * @param  file: pointer to the source file name
00227   * @param  line: assert_param error line source number
00228   * @retval None
00229   */
00230 void assert_failed(uint8_t* file, uint32_t line)
00231 { 
00232   /* User can add his own implementation to report the file name and line number,
00233      ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
00234 
00235   /* Infinite loop */
00236   while (1)
00237   {
00238   }
00239 }
00240 #endif
00241 
00242 /**
00243   * @}
00244   */
00245 
00246 /**
00247   * @}
00248   */
00249 
00250 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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