STM32F0xx Standard Peripherals Firmware Library: stm32f0xx_it.c Source File

00001 /**
00002   ******************************************************************************
00003   * @file    RCC/RCC_Example/stm32f0xx_it.c 
00004   * @author  MCD Application Team
00005   * @version V1.4.0
00006   * @date    24-July-2014
00007   * @brief   Main Interrupt Service Routines.
00008   *          This file provides template for all exceptions handler and 
00009   *          peripherals interrupt service routine.
00010   ******************************************************************************
00011   * @attention
00012   *
00013   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00014   *
00015   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00016   * You may not use this file except in compliance with the License.
00017   * You may obtain a copy of the License at:
00018   *
00019   *        http://www.st.com/software_license_agreement_liberty_v2
00020   *
00021   * Unless required by applicable law or agreed to in writing, software 
00022   * distributed under the License is distributed on an "AS IS" BASIS, 
00023   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00024   * See the License for the specific language governing permissions and
00025   * limitations under the License.
00026   *
00027   ******************************************************************************
00028   */
00029 
00030 /* Includes ------------------------------------------------------------------*/
00031 #include "stm32f0xx_it.h"
00032 
00033 /** @addtogroup STM32F0xx_StdPeriph_Examples
00034   * @{
00035   */
00036 
00037 /** @addtogroup RCC_Example
00038   * @{
00039   */
00040 
00041 /* Private typedef -----------------------------------------------------------*/
00042 /* Private define ------------------------------------------------------------*/
00043 /* Private macro -------------------------------------------------------------*/
00044 /* Private variables ---------------------------------------------------------*/
00045 /* Private function prototypes -----------------------------------------------*/
00046 /* Private functions ---------------------------------------------------------*/
00047 
00048 /******************************************************************************/
00049 /*            Cortex-M0 Processor Exceptions Handlers                         */
00050 /******************************************************************************/
00051 
00052 /**
00053   * @brief  This function handles NMI exception.
00054   * @param  None
00055   * @retval None
00056   */
00057 void NMI_Handler(void)
00058 {
00059   /* This interrupt is generated when HSE clock fails */
00060 
00061   if (RCC_GetITStatus(RCC_IT_CSS) != RESET)
00062   {
00063     /* At this stage: HSE, PLL are disabled (but no change on PLL config) and HSI
00064        is selected as system clock source */
00065 
00066     /* Enable HSE */
00067     RCC_HSEConfig(RCC_HSE_ON);
00068 
00069     /* Enable HSE Ready and PLL Ready interrupts */
00070     RCC_ITConfig(RCC_IT_HSERDY | RCC_IT_PLLRDY, ENABLE);
00071 
00072     /* Clear Clock Security System interrupt pending bit */
00073     RCC_ClearITPendingBit(RCC_IT_CSS);
00074 
00075     /* Once HSE clock recover, the HSERDY interrupt is generated and in the RCC ISR
00076        routine the system clock will be reconfigured to its previous state (before
00077        HSE clock failure) */
00078   }
00079 }
00080 
00081 /**
00082   * @brief  This function handles Hard Fault exception.
00083   * @param  None
00084   * @retval None
00085   */
00086 void HardFault_Handler(void)
00087 {
00088   /* Go to infinite loop when Hard Fault exception occurs */
00089   while (1)
00090   {
00091   }
00092 }
00093 
00094 /**
00095   * @brief  This function handles SVCall exception.
00096   * @param  None
00097   * @retval None
00098   */
00099 void SVC_Handler(void)
00100 {
00101 }
00102 
00103 /**
00104   * @brief  This function handles PendSVC exception.
00105   * @param  None
00106   * @retval None
00107   */
00108 void PendSV_Handler(void)
00109 {
00110 }
00111 
00112 /**
00113   * @brief  This function handles SysTick Handler.
00114   * @param  None
00115   * @retval None
00116   */
00117 void SysTick_Handler(void)
00118 {
00119 }
00120 
00121 /******************************************************************************/
00122 /*                 STM32F0xx Peripherals Interrupt Handlers                   */
00123 /*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
00124 /*  available peripheral interrupt handler's name please refer to the startup */
00125 /*  file (startup_stm32f0xx.s).                                            */
00126 /******************************************************************************/
00127 
00128 /**
00129   * @brief  This function handles PPP interrupt request.
00130   * @param  None
00131   * @retval None
00132   */
00133 /*void PPP_IRQHandler(void)
00134 {
00135 }*/
00136 
00137 /**
00138   * @brief  This function handles RCC interrupt request. 
00139   * @param  None
00140   * @retval None
00141   */
00142 #ifdef USE_STM320518_EVAL
00143 void RCC_IRQHandler(void)
00144 {
00145   if(RCC_GetITStatus(RCC_IT_HSERDY) != RESET)
00146   { 
00147     /* Clear HSERDY interrupt pending bit */
00148     RCC_ClearITPendingBit(RCC_IT_HSERDY);
00149 
00150     /* Check if the HSE clock is still available */
00151     if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
00152     { 
00153       /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */ 
00154       RCC_PLLCmd(ENABLE);     
00155     }
00156   }
00157 
00158   if(RCC_GetITStatus(RCC_IT_PLLRDY) != RESET)
00159   { 
00160     /* Clear PLLRDY interrupt pending bit */
00161     RCC_ClearITPendingBit(RCC_IT_PLLRDY);
00162 
00163     /* Check if the PLL is still locked */
00164     if (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) != RESET)
00165     { 
00166       /* Select PLL as system clock source */
00167       RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00168     }
00169   }
00170 }
00171 #else 
00172 void RCC_CRS_IRQHandler(void)
00173 {
00174   if(RCC_GetITStatus(RCC_IT_HSERDY) != RESET)
00175   { 
00176     /* Clear HSERDY interrupt pending bit */
00177     RCC_ClearITPendingBit(RCC_IT_HSERDY);
00178 
00179     /* Check if the HSE clock is still available */
00180     if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
00181     { 
00182       /* Enable PLL: once the PLL is ready the PLLRDY interrupt is generated */ 
00183       RCC_PLLCmd(ENABLE);     
00184     }
00185   }
00186 
00187   if(RCC_GetITStatus(RCC_IT_PLLRDY) != RESET)
00188   { 
00189     /* Clear PLLRDY interrupt pending bit */
00190     RCC_ClearITPendingBit(RCC_IT_PLLRDY);
00191 
00192     /* Check if the PLL is still locked */
00193     if (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) != RESET)
00194     { 
00195       /* Select PLL as system clock source */
00196       RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
00197     }
00198   }
00199 }
00200 #endif /* USE_STM320518_EVAL */
00201 
00202 
00203 /**
00204   * @}
00205   */ 
00206 
00207 /**
00208   * @}
00209   */ 
00210 
00211 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/