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STM32F0xx Standard Peripherals Firmware Library
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STM32F0xx_StdPeriph_Examples/FLASH/Flash_WriteProtection/system_stm32f0xx.c
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00001 /** 00002 ****************************************************************************** 00003 * @file FLASH/FLASH_WriteProtection/system_stm32f0xx.c 00004 * @author MCD Application Team 00005 * @version V1.4.0 00006 * @date 24-July-2014 00007 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. 00008 * This file contains the system clock configuration for STM32F0xx devices, 00009 * and is generated by the clock configuration tool 00010 * STM32F0xx_Clock_Configuration_V1.0.0.xls 00011 * 00012 * 1. This file provides two functions and one global variable to be called from 00013 * user application: 00014 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 00015 * and Divider factors, AHB/APBx prescalers and Flash settings), 00016 * depending on the configuration made in the clock xls tool. 00017 * This function is called at startup just after reset and 00018 * before branch to main program. This call is made inside 00019 * the "startup_stm32f0xx.s" file. 00020 * 00021 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 00022 * by the user application to setup the SysTick 00023 * timer or configure other parameters. 00024 * 00025 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 00026 * be called whenever the core clock is changed 00027 * during program execution. 00028 * 00029 * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. 00030 * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to 00031 * configure the system clock before to branch to main program. 00032 * 00033 * 3. If the system clock source selected by user fails to startup, the SystemInit() 00034 * function will do nothing and HSI still used as system clock source. User can 00035 * add some code to deal with this issue inside the SetSysClock() function. 00036 * 00037 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define 00038 * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or 00039 * through PLL, and you are using different crystal you have to adapt the HSE 00040 * value to your own configuration. 00041 * 00042 * 5. This file configures the system clock as follows: 00043 *============================================================================= 00044 * System Clock Configuration 00045 *============================================================================= 00046 * System Clock source | PLL(HSE) 00047 *----------------------------------------------------------------------------- 00048 * SYSCLK | 48000000 Hz 00049 *----------------------------------------------------------------------------- 00050 * HCLK | 48000000 Hz 00051 *----------------------------------------------------------------------------- 00052 * AHB Prescaler | 1 00053 *----------------------------------------------------------------------------- 00054 * APB1 Prescaler | 1 00055 *----------------------------------------------------------------------------- 00056 * APB2 Prescaler | 1 00057 *----------------------------------------------------------------------------- 00058 * HSE Frequency | 8000000 Hz 00059 *----------------------------------------------------------------------------- 00060 * PLL MUL | 6 00061 *----------------------------------------------------------------------------- 00062 * VDD | 3.3 V 00063 *----------------------------------------------------------------------------- 00064 * Flash Latency | 1 WS 00065 *----------------------------------------------------------------------------- 00066 *============================================================================= 00067 ****************************************************************************** 00068 * @attention 00069 * 00070 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 00071 * 00072 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00073 * You may not use this file except in compliance with the License. 00074 * You may obtain a copy of the License at: 00075 * 00076 * http://www.st.com/software_license_agreement_liberty_v2 00077 * 00078 * Unless required by applicable law or agreed to in writing, software 00079 * distributed under the License is distributed on an "AS IS" BASIS, 00080 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00081 * See the License for the specific language governing permissions and 00082 * limitations under the License. 00083 * 00084 ****************************************************************************** 00085 */ 00086 00087 /** @addtogroup CMSIS 00088 * @{ 00089 */ 00090 00091 /** @addtogroup stm32f0xx_system 00092 * @{ 00093 */ 00094 00095 /** @addtogroup STM32F0xx_System_Private_Includes 00096 * @{ 00097 */ 00098 00099 #include "stm32f0xx.h" 00100 00101 /** 00102 * @} 00103 */ 00104 00105 /** @addtogroup STM32F0xx_System_Private_TypesDefinitions 00106 * @{ 00107 */ 00108 00109 /** 00110 * @} 00111 */ 00112 00113 /** @addtogroup STM32F0xx_System_Private_Defines 00114 * @{ 00115 */ 00116 /** 00117 * @} 00118 */ 00119 00120 /** @addtogroup STM32F0xx_System_Private_Macros 00121 * @{ 00122 */ 00123 00124 /** 00125 * @} 00126 */ 00127 00128 /** @addtogroup STM32F0xx_System_Private_Variables 00129 * @{ 00130 */ 00131 uint32_t SystemCoreClock = 48000000; 00132 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 00133 00134 /** 00135 * @} 00136 */ 00137 00138 /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes 00139 * @{ 00140 */ 00141 00142 static void SetSysClock(void); 00143 00144 /** 00145 * @} 00146 */ 00147 00148 /** @addtogroup STM32F0xx_System_Private_Functions 00149 * @{ 00150 */ 00151 00152 /** 00153 * @brief Setup the microcontroller system. 00154 * Initialize the Embedded Flash Interface, the PLL and update the 00155 * SystemCoreClock variable. 00156 * @param None 00157 * @retval None 00158 */ 00159 void SystemInit (void) 00160 { 00161 /* Set HSION bit */ 00162 RCC->CR |= (uint32_t)0x00000001; 00163 00164 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ 00165 RCC->CFGR &= (uint32_t)0xF8FFB80C; 00166 00167 /* Reset HSEON, CSSON and PLLON bits */ 00168 RCC->CR &= (uint32_t)0xFEF6FFFF; 00169 00170 /* Reset HSEBYP bit */ 00171 RCC->CR &= (uint32_t)0xFFFBFFFF; 00172 00173 /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ 00174 RCC->CFGR &= (uint32_t)0xFFC0FFFF; 00175 00176 /* Reset PREDIV1[3:0] bits */ 00177 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; 00178 00179 /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ 00180 RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; 00181 00182 /* Reset HSI14 bit */ 00183 RCC->CR2 &= (uint32_t)0xFFFFFFFE; 00184 00185 /* Disable all interrupts */ 00186 RCC->CIR = 0x00000000; 00187 00188 /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ 00189 SetSysClock(); 00190 } 00191 00192 /** 00193 * @brief Update SystemCoreClock according to Clock Register Values 00194 * The SystemCoreClock variable contains the core clock (HCLK), it can 00195 * be used by the user application to setup the SysTick timer or configure 00196 * other parameters. 00197 * 00198 * @note Each time the core clock (HCLK) changes, this function must be called 00199 * to update SystemCoreClock variable value. Otherwise, any configuration 00200 * based on this variable will be incorrect. 00201 * 00202 * @note - The system frequency computed by this function is not the real 00203 * frequency in the chip. It is calculated based on the predefined 00204 * constant and the selected clock source: 00205 * 00206 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 00207 * 00208 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 00209 * 00210 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 00211 * or HSI_VALUE(*) multiplied/divided by the PLL factors. 00212 * 00213 * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value 00214 * 8 MHz) but the real value may vary depending on the variations 00215 * in voltage and temperature. 00216 * 00217 * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value 00218 * 8 MHz), user has to ensure that HSE_VALUE is same as the real 00219 * frequency of the crystal used. Otherwise, this function may 00220 * have wrong result. 00221 * 00222 * - The result of this function could be not correct when using fractional 00223 * value for HSE crystal. 00224 * @param None 00225 * @retval None 00226 */ 00227 void SystemCoreClockUpdate (void) 00228 { 00229 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; 00230 00231 /* Get SYSCLK source -------------------------------------------------------*/ 00232 tmp = RCC->CFGR & RCC_CFGR_SWS; 00233 00234 switch (tmp) 00235 { 00236 case 0x00: /* HSI used as system clock */ 00237 SystemCoreClock = HSI_VALUE; 00238 break; 00239 case 0x04: /* HSE used as system clock */ 00240 SystemCoreClock = HSE_VALUE; 00241 break; 00242 case 0x08: /* PLL used as system clock */ 00243 /* Get PLL clock source and multiplication factor ----------------------*/ 00244 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 00245 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 00246 pllmull = ( pllmull >> 18) + 2; 00247 00248 if (pllsource == 0x00) 00249 { 00250 /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 00251 SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 00252 } 00253 else 00254 { 00255 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; 00256 /* HSE oscillator clock selected as PREDIV1 clock entry */ 00257 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 00258 } 00259 break; 00260 default: /* HSI used as system clock */ 00261 SystemCoreClock = HSI_VALUE; 00262 break; 00263 } 00264 /* Compute HCLK clock frequency ----------------*/ 00265 /* Get HCLK prescaler */ 00266 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 00267 /* HCLK clock frequency */ 00268 SystemCoreClock >>= tmp; 00269 } 00270 00271 /** 00272 * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash 00273 * settings. 00274 * @note This function should be called only once the RCC clock configuration 00275 * is reset to the default reset state (done in SystemInit() function). 00276 * @param None 00277 * @retval None 00278 */ 00279 static void SetSysClock(void) 00280 { 00281 __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 00282 00283 /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ 00284 /* Enable HSE */ 00285 RCC->CR |= ((uint32_t)RCC_CR_HSEON); 00286 00287 /* Wait till HSE is ready and if Time out is reached exit */ 00288 do 00289 { 00290 HSEStatus = RCC->CR & RCC_CR_HSERDY; 00291 StartUpCounter++; 00292 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 00293 00294 if ((RCC->CR & RCC_CR_HSERDY) != RESET) 00295 { 00296 HSEStatus = (uint32_t)0x01; 00297 } 00298 else 00299 { 00300 HSEStatus = (uint32_t)0x00; 00301 } 00302 00303 if (HSEStatus == (uint32_t)0x01) 00304 { 00305 /* Enable Prefetch Buffer and set Flash Latency */ 00306 FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; 00307 00308 /* HCLK = SYSCLK */ 00309 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 00310 00311 /* PCLK = HCLK */ 00312 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; 00313 00314 /* PLL configuration = HSE * 6 = 48 MHz */ 00315 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 00316 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); 00317 00318 /* Enable PLL */ 00319 RCC->CR |= RCC_CR_PLLON; 00320 00321 /* Wait till PLL is ready */ 00322 while((RCC->CR & RCC_CR_PLLRDY) == 0) 00323 { 00324 } 00325 00326 /* Select PLL as system clock source */ 00327 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 00328 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 00329 00330 /* Wait till PLL is used as system clock source */ 00331 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) 00332 { 00333 } 00334 } 00335 else 00336 { /* If HSE fails to start-up, the application will have wrong clock 00337 configuration. User can add here some code to deal with this error */ 00338 } 00339 } 00340 00341 /** 00342 * @} 00343 */ 00344 00345 /** 00346 * @} 00347 */ 00348 00349 /** 00350 * @} 00351 */ 00352 00353 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/