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STM32446E_EVAL BSP User Manual
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stm32446e_eval_sdram.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32446e_eval_sdram.c 00004 * @author MCD Application Team 00005 * @version V1.1.1 00006 * @date 13-January-2016 00007 * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory 00008 * device mounted on STM32446E-EVAL evaluation board. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00013 * 00014 * Redistribution and use in source and binary forms, with or without modification, 00015 * are permitted provided that the following conditions are met: 00016 * 1. Redistributions of source code must retain the above copyright notice, 00017 * this list of conditions and the following disclaimer. 00018 * 2. Redistributions in binary form must reproduce the above copyright notice, 00019 * this list of conditions and the following disclaimer in the documentation 00020 * and/or other materials provided with the distribution. 00021 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00022 * may be used to endorse or promote products derived from this software 00023 * without specific prior written permission. 00024 * 00025 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00026 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00027 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00028 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00029 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00030 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00031 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00032 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00033 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00034 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00035 * 00036 ****************************************************************************** 00037 */ 00038 00039 /* File Info : ----------------------------------------------------------------- 00040 User NOTES 00041 1. How To use this driver: 00042 -------------------------- 00043 - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted 00044 on STM32446E-EVAL evaluation board. 00045 - This driver does not need a specific component driver for the SDRAM device 00046 to be included with. 00047 00048 2. Driver description: 00049 --------------------- 00050 + Initialization steps: 00051 o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This 00052 function includes the MSP layer hardware resources initialization and the 00053 FMC controller configuration to interface with the external SDRAM memory. 00054 o It contains the SDRAM initialization sequence to program the SDRAM external 00055 device using the function BSP_SDRAM_Initialization_sequence(). Note that this 00056 sequence is standard for all SDRAM devices, but can include some differences 00057 from a device to another. If it is the case, the right sequence should be 00058 implemented separately. 00059 00060 + SDRAM read/write operations 00061 o SDRAM external memory can be accessed with read/write operations once it is 00062 initialized. 00063 Read/write operation can be performed with AHB access using the functions 00064 BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions 00065 BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA(). 00066 o The AHB access is performed with 16-bit width transaction, the DMA transfer 00067 configuration is fixed at single (no burst) halfword transfer (see the 00068 BSP_SDRAM_MspInit() __weak function). 00069 o User can implement his own functions for read/write access with his desired 00070 configurations. 00071 o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler() 00072 is called in IRQ handler file, to serve the generated interrupt once the DMA 00073 transfer is complete. 00074 o You can send a command to the SDRAM device in runtime using the function 00075 BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between 00076 the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. 00077 00078 ------------------------------------------------------------------------------*/ 00079 00080 /* Includes ------------------------------------------------------------------*/ 00081 #include "stm32446e_eval_sdram.h" 00082 00083 /** @addtogroup BSP 00084 * @{ 00085 */ 00086 00087 /** @addtogroup STM32446E_EVAL 00088 * @{ 00089 */ 00090 00091 /** @defgroup STM32446E_EVAL_SDRAM STM32446E EVAL SDRAM 00092 * @{ 00093 */ 00094 00095 /** @defgroup STM32446E_EVAL_SDRAM_Private_Types_Definitions STM32446E EVAL SDRAM Private Types Definitions 00096 * @{ 00097 */ 00098 /** 00099 * @} 00100 */ 00101 00102 /** @defgroup STM32446E_EVAL_SDRAM_Private_Defines STM32446E EVAL SDRAM Private Defines 00103 * @{ 00104 */ 00105 /** 00106 * @} 00107 */ 00108 00109 /** @defgroup STM32446E_EVAL_SDRAM_Private_Macros STM32446E EVAL SDRAM Private Macros 00110 * @{ 00111 */ 00112 /** 00113 * @} 00114 */ 00115 00116 /** @defgroup STM32446E_EVAL_SDRAM_Private_Variables STM32446E EVAL SDRAM Private Variables 00117 * @{ 00118 */ 00119 static SDRAM_HandleTypeDef sdramHandle; 00120 static FMC_SDRAM_TimingTypeDef Timing; 00121 static FMC_SDRAM_CommandTypeDef Command; 00122 /** 00123 * @} 00124 */ 00125 00126 /** @defgroup STM32446E_EVAL_SDRAM_Private_Function_Prototypes STM32446E EVAL SDRAM Private Function Prototypes 00127 * @{ 00128 */ 00129 /** 00130 * @} 00131 */ 00132 00133 /** @defgroup STM32446E_EVAL_SDRAM_Private_Functions STM32446E EVAL SDRAM Private Functions 00134 * @{ 00135 */ 00136 00137 /** 00138 * @brief Initializes the SDRAM device. 00139 * @retval SDRAM status 00140 */ 00141 uint8_t BSP_SDRAM_Init(void) 00142 { 00143 static uint8_t sdramstatus = SDRAM_ERROR; 00144 /* SDRAM device configuration */ 00145 sdramHandle.Instance = FMC_SDRAM_DEVICE; 00146 00147 /* Timing configuration for 90Mhz as SD clock frequency (System clock is up to 180Mhz */ 00148 Timing.LoadToActiveDelay = 2; 00149 Timing.ExitSelfRefreshDelay = 7; 00150 Timing.SelfRefreshTime = 4; 00151 Timing.RowCycleDelay = 7; 00152 Timing.WriteRecoveryTime = 2; 00153 Timing.RPDelay = 2; 00154 Timing.RCDDelay = 2; 00155 00156 sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; 00157 sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; 00158 sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; 00159 sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; 00160 sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; 00161 sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2; 00162 sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; 00163 sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; 00164 sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; 00165 sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; 00166 00167 /* SDRAM controller initialization */ 00168 00169 BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the applic */ 00170 00171 if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) 00172 { 00173 sdramstatus = SDRAM_ERROR; 00174 } 00175 else 00176 { 00177 sdramstatus = SDRAM_OK; 00178 } 00179 00180 /* SDRAM initialization sequence */ 00181 BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); 00182 00183 return sdramstatus; 00184 } 00185 00186 /** 00187 * @brief DeInitializes the SDRAM device. 00188 * @retval SDRAM status 00189 */ 00190 uint8_t BSP_SDRAM_DeInit(void) 00191 { 00192 static uint8_t sdramstatus = SDRAM_ERROR; 00193 /* SDRAM device configuration */ 00194 sdramHandle.Instance = FMC_SDRAM_DEVICE; 00195 00196 if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) 00197 { 00198 sdramstatus = SDRAM_ERROR; 00199 } 00200 else 00201 { 00202 sdramstatus = SDRAM_OK; 00203 } 00204 00205 /* SDRAM controller initialization */ 00206 BSP_SDRAM_MspDeInit(&sdramHandle, NULL); 00207 00208 return sdramstatus; 00209 } 00210 00211 /** 00212 * @brief Programs the SDRAM device. 00213 * @param RefreshCount: SDRAM refresh counter value 00214 */ 00215 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) 00216 { 00217 __IO uint32_t tmpmrd = 0; 00218 00219 /* Step 1: Configure a clock configuration enable command */ 00220 Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; 00221 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00222 Command.AutoRefreshNumber = 1; 00223 Command.ModeRegisterDefinition = 0; 00224 00225 /* Send the command */ 00226 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00227 00228 /* Step 2: Insert 100 us minimum delay */ 00229 /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ 00230 HAL_Delay(1); 00231 00232 /* Step 3: Configure a PALL (precharge all) command */ 00233 Command.CommandMode = FMC_SDRAM_CMD_PALL; 00234 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00235 Command.AutoRefreshNumber = 1; 00236 Command.ModeRegisterDefinition = 0; 00237 00238 /* Send the command */ 00239 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00240 00241 /* Step 4: Configure an Auto Refresh command */ 00242 Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; 00243 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00244 Command.AutoRefreshNumber = 8; 00245 Command.ModeRegisterDefinition = 0; 00246 00247 /* Send the command */ 00248 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00249 00250 /* Step 5: Program the external memory mode register */ 00251 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ 00252 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ 00253 SDRAM_MODEREG_CAS_LATENCY_2 |\ 00254 SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ 00255 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; 00256 00257 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; 00258 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00259 Command.AutoRefreshNumber = 1; 00260 Command.ModeRegisterDefinition = tmpmrd; 00261 00262 /* Send the command */ 00263 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00264 00265 /* Step 6: Set the refresh rate counter */ 00266 /* Set the device refresh rate */ 00267 HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); 00268 } 00269 00270 /** 00271 * @brief Reads an mount of data from the SDRAM memory in polling mode. 00272 * @param uwStartAddress: Read start address 00273 * @param pData: Pointer to data to be read 00274 * @param uwDataSize: Size of read data from the memory 00275 * @retval SDRAM status 00276 */ 00277 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00278 { 00279 if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00280 { 00281 return SDRAM_ERROR; 00282 } 00283 else 00284 { 00285 return SDRAM_OK; 00286 } 00287 } 00288 00289 /** 00290 * @brief Reads an mount of data from the SDRAM memory in DMA mode. 00291 * @param uwStartAddress: Read start address 00292 * @param pData: Pointer to data to be read 00293 * @param uwDataSize: Size of read data from the memory 00294 * @retval SDRAM status 00295 */ 00296 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00297 { 00298 if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00299 { 00300 return SDRAM_ERROR; 00301 } 00302 else 00303 { 00304 return SDRAM_OK; 00305 } 00306 } 00307 00308 /** 00309 * @brief Writes an mount of data to the SDRAM memory in polling mode. 00310 * @param uwStartAddress: Write start address 00311 * @param pData: Pointer to data to be written 00312 * @param uwDataSize: Size of written data from the memory 00313 * @retval SDRAM status 00314 */ 00315 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00316 { 00317 if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00318 { 00319 return SDRAM_ERROR; 00320 } 00321 else 00322 { 00323 return SDRAM_OK; 00324 } 00325 } 00326 00327 /** 00328 * @brief Writes an mount of data to the SDRAM memory in DMA mode. 00329 * @param uwStartAddress: Write start address 00330 * @param pData: Pointer to data to be written 00331 * @param uwDataSize: Size of written data from the memory 00332 * @retval SDRAM status 00333 */ 00334 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00335 { 00336 if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00337 { 00338 return SDRAM_ERROR; 00339 } 00340 else 00341 { 00342 return SDRAM_OK; 00343 } 00344 } 00345 00346 /** 00347 * @brief Sends command to the SDRAM bank. 00348 * @param SdramCmd: Pointer to SDRAM command structure 00349 * @retval HAL status 00350 */ 00351 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) 00352 { 00353 if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) 00354 { 00355 return SDRAM_ERROR; 00356 } 00357 else 00358 { 00359 return SDRAM_OK; 00360 } 00361 } 00362 00363 /** 00364 * @brief Handles SDRAM DMA transfer interrupt request. 00365 */ 00366 void BSP_SDRAM_DMA_IRQHandler(void) 00367 { 00368 HAL_DMA_IRQHandler(sdramHandle.hdma); 00369 } 00370 00371 /** 00372 * @brief Initializes SDRAM MSP. 00373 * @param hsdram: SDRAM handle 00374 * @param Params: pointer on additional configuration parameters, can be NULL. 00375 */ 00376 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) 00377 { 00378 static DMA_HandleTypeDef dma_handle; 00379 GPIO_InitTypeDef gpio_init_structure; 00380 00381 /* Enable FMC clock */ 00382 __HAL_RCC_FMC_CLK_ENABLE(); 00383 00384 /* Enable chosen DMAx clock */ 00385 __DMAx_CLK_ENABLE(); 00386 00387 /* Enable GPIOs clock */ 00388 __HAL_RCC_GPIOA_CLK_ENABLE(); 00389 __HAL_RCC_GPIOC_CLK_ENABLE(); 00390 __HAL_RCC_GPIOD_CLK_ENABLE(); 00391 __HAL_RCC_GPIOE_CLK_ENABLE(); 00392 __HAL_RCC_GPIOF_CLK_ENABLE(); 00393 __HAL_RCC_GPIOG_CLK_ENABLE(); 00394 00395 /* Common GPIO configuration */ 00396 gpio_init_structure.Mode = GPIO_MODE_AF_PP; 00397 gpio_init_structure.Pull = GPIO_PULLUP; 00398 gpio_init_structure.Speed = GPIO_SPEED_FAST; 00399 gpio_init_structure.Alternate = GPIO_AF12_FMC; 00400 00401 /* GPIOA configuration */ 00402 gpio_init_structure.Pin = GPIO_PIN_7; 00403 HAL_GPIO_Init(GPIOA, &gpio_init_structure); 00404 00405 /* GPIOC configuration */ 00406 gpio_init_structure.Pin = GPIO_PIN_5 | GPIO_PIN_4; 00407 HAL_GPIO_Init(GPIOC, &gpio_init_structure); 00408 00409 /* GPIOD configuration */ 00410 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\ 00411 GPIO_PIN_14 | GPIO_PIN_15; 00412 00413 00414 HAL_GPIO_Init(GPIOD, &gpio_init_structure); 00415 00416 /* GPIOE configuration */ 00417 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ 00418 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ 00419 GPIO_PIN_15; 00420 00421 HAL_GPIO_Init(GPIOE, &gpio_init_structure); 00422 00423 /* GPIOF configuration */ 00424 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ 00425 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ 00426 GPIO_PIN_15; 00427 00428 HAL_GPIO_Init(GPIOF, &gpio_init_structure); 00429 00430 /* GPIOG configuration */ 00431 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ 00432 GPIO_PIN_15 | GPIO_PIN_2; 00433 HAL_GPIO_Init(GPIOG, &gpio_init_structure); 00434 00435 /* Configure common DMA parameters */ 00436 dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; 00437 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; 00438 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; 00439 dma_handle.Init.MemInc = DMA_MINC_ENABLE; 00440 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; 00441 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; 00442 dma_handle.Init.Mode = DMA_NORMAL; 00443 dma_handle.Init.Priority = DMA_PRIORITY_HIGH; 00444 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 00445 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; 00446 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; 00447 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; 00448 00449 dma_handle.Instance = SDRAM_DMAx_STREAM; 00450 00451 /* Associate the DMA handle */ 00452 __HAL_LINKDMA(hsdram, hdma, dma_handle); 00453 00454 /* Deinitialize the stream for new transfer */ 00455 HAL_DMA_DeInit(&dma_handle); 00456 00457 /* Configure the DMA stream */ 00458 HAL_DMA_Init(&dma_handle); 00459 00460 /* NVIC configuration for DMA transfer complete interrupt */ 00461 HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); 00462 HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); 00463 } 00464 00465 00466 /** 00467 * @brief DeInitializes SDRAM MSP. 00468 * @param hsdram: SDRAM handle 00469 * @param Params: pointer on additional configuration parameters, can be NULL. 00470 */ 00471 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) 00472 { 00473 static DMA_HandleTypeDef dma_handle; 00474 00475 /* Disable NVIC configuration for DMA interrupt */ 00476 HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); 00477 00478 /* Deinitialize the stream for new transfer */ 00479 dma_handle.Instance = SDRAM_DMAx_STREAM; 00480 HAL_DMA_DeInit(&dma_handle); 00481 00482 /* DeInit GPIO pins can be done in the application 00483 (by surcharging this __weak function) */ 00484 00485 /* GPIO pins clock, FMC clock and DMA clock can be shut down in the application 00486 by surcharging this __weak function */ 00487 } 00488 00489 /** 00490 * @} 00491 */ 00492 00493 /** 00494 * @} 00495 */ 00496 00497 /** 00498 * @} 00499 */ 00500 00501 /** 00502 * @} 00503 */ 00504 00505 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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