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STM8S/A Standard Peripherals Drivers
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stm8s.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8s.h 00004 * @author MCD Application Team 00005 * @version V2.2.0 00006 * @date 30-September-2014 00007 * @brief This file contains all HW registers definitions and memory mapping. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 00012 * 00013 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00014 * You may not use this file except in compliance with the License. 00015 * You may obtain a copy of the License at: 00016 * 00017 * http://www.st.com/software_license_agreement_liberty_v2 00018 * 00019 * Unless required by applicable law or agreed to in writing, software 00020 * distributed under the License is distributed on an "AS IS" BASIS, 00021 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00022 * See the License for the specific language governing permissions and 00023 * limitations under the License. 00024 * 00025 ****************************************************************************** 00026 */ 00027 00028 /* Define to prevent recursive inclusion -------------------------------------*/ 00029 #ifndef __STM8S_H 00030 #define __STM8S_H 00031 00032 /** @addtogroup STM8S_StdPeriph_Driver 00033 * @{ 00034 */ 00035 00036 /* Uncomment the line below according to the target STM8S or STM8A device used in your 00037 application. */ 00038 00039 /* #define STM8S208 */ /*!< STM8S High density devices with CAN */ 00040 /* #define STM8S207 */ /*!< STM8S High density devices without CAN */ 00041 /* #define STM8S007 */ /*!< STM8S Value Line High density devices */ 00042 /* #define STM8AF52Ax */ /*!< STM8A High density devices with CAN */ 00043 /* #define STM8AF62Ax */ /*!< STM8A High density devices without CAN */ 00044 /* #define STM8S105 */ /*!< STM8S Medium density devices */ 00045 /* #define STM8S005 */ /*!< STM8S Value Line Medium density devices */ 00046 /* #define STM8AF626x */ /*!< STM8A Medium density devices */ 00047 /* #define STM8AF622x */ /*!< STM8A Low density devices */ 00048 /* #define STM8S103 */ /*!< STM8S Low density devices */ 00049 /* #define STM8S003 */ /*!< STM8S Value Line Low density devices */ 00050 /* #define STM8S903 */ /*!< STM8S Low density devices */ 00051 00052 /* Tip: To avoid modifying this file each time you need to switch between these 00053 devices, you can define the device in your toolchain compiler preprocessor. 00054 00055 - High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax, 00056 STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory 00057 density ranges between 32 to 128 Kbytes 00058 - Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68, 00059 STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory 00060 density ranges between 8 to 32 Kbytes 00061 - High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx microcontrollers 00062 where the Flash memory density ranges between 32 to 128 Kbytes. 00063 - Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers 00064 where the Flash memory density ranges between 16 to 32-Kbytes. 00065 - Low-Density STM8A devices are the STM8AF622x microcontrollers where the Flash 00066 density is 8 Kbytes. 00067 - Low-Density STM8S devices are the STM8S103xx, STM8S003 and STM8S903xx microcontrollers 00068 where the Flash density is 8 Kbytes. */ 00069 00070 #if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \ 00071 !defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \ 00072 !defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \ 00073 !defined (STM8S003)&& !defined (STM8S005) && !defined (STM8AF622x) 00074 #error "Please select first the target STM8S/A device used in your application (in stm8s.h file)" 00075 #endif 00076 00077 /******************************************************************************/ 00078 /* Library configuration section */ 00079 /******************************************************************************/ 00080 /* Check the used compiler */ 00081 #if defined(__CSMC__) 00082 #define _COSMIC_ 00083 #elif defined(__RCST7__) 00084 #define _RAISONANCE_ 00085 #elif defined(__ICCSTM8__) 00086 #define _IAR_ 00087 #else 00088 #error "Unsupported Compiler!" /* Compiler defines not found */ 00089 #endif 00090 00091 #if !defined USE_STDPERIPH_DRIVER 00092 /* Comment the line below if you will not use the peripherals drivers. 00093 In this case, these drivers will not be included and the application code will be 00094 based on direct access to peripherals registers */ 00095 #define USE_STDPERIPH_DRIVER 00096 #endif 00097 00098 /** 00099 * @brief In the following line adjust the value of External High Speed oscillator (HSE) 00100 used in your application 00101 00102 Tip: To avoid modifying this file each time you need to use different HSE, you 00103 can define the HSE value in your toolchain compiler preprocessor. 00104 */ 00105 #if !defined HSE_Value 00106 #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \ 00107 defined (STM8AF62Ax) || defined (STM8AF622x) 00108 #define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz*/ 00109 #else 00110 #define HSE_VALUE ((uint32_t)16000000) /* Value of the External oscillator in Hz*/ 00111 #endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax || STM8AF622x */ 00112 #endif /* HSE_Value */ 00113 00114 /** 00115 * @brief Definition of Device on-chip RC oscillator frequencies 00116 */ 00117 #define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */ 00118 #define LSI_VALUE ((uint32_t)128000) /*!< Typical Value of the LSI in Hz */ 00119 00120 #ifdef _COSMIC_ 00121 #define FAR @far 00122 #define NEAR @near 00123 #define TINY @tiny 00124 #define EEPROM @eeprom 00125 #define CONST const 00126 #elif defined (_RAISONANCE_) /* __RCST7__ */ 00127 #define FAR far 00128 #define NEAR data 00129 #define TINY page0 00130 #define EEPROM eeprom 00131 #define CONST code 00132 #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \ 00133 defined (STM8AF62Ax) 00134 /*!< Used with memory Models for code higher than 64K */ 00135 #define MEMCPY fmemcpy 00136 #else /* STM8S903, STM8S103, STM8S003, STM8S105, STM8AF626x, STM8AF622x */ 00137 /*!< Used with memory Models for code less than 64K */ 00138 #define MEMCPY memcpy 00139 #endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */ 00140 #else /*_IAR_*/ 00141 #define FAR __far 00142 #define NEAR __near 00143 #define TINY __tiny 00144 #define EEPROM __eeprom 00145 #define CONST const 00146 #endif /* __CSMC__ */ 00147 00148 /* For FLASH routines, select whether pointer will be declared as near (2 bytes, 00149 to handle code smaller than 64KB) or far (3 bytes, to handle code larger 00150 than 64K) */ 00151 00152 #if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined (STM8S003) || \ 00153 defined (STM8S903) || defined (STM8AF626x) || defined (STM8AF622x) 00154 /*!< Used with memory Models for code smaller than 64K */ 00155 #define PointerAttr NEAR 00156 #define MemoryAddressCast uint16_t 00157 #else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */ 00158 /*!< Used with memory Models for code higher than 64K */ 00159 #define PointerAttr FAR 00160 #define MemoryAddressCast uint32_t 00161 #endif /* STM8S105 or STM8S103 or STM8S003 or STM8S903 or STM8AF626x or STM8AF622x */ 00162 00163 /* Uncomment the line below to enable the FLASH functions execution from RAM */ 00164 #if !defined (RAM_EXECUTION) 00165 /* #define RAM_EXECUTION (1) */ 00166 #endif /* RAM_EXECUTION */ 00167 00168 #ifdef RAM_EXECUTION 00169 #ifdef _COSMIC_ 00170 #define IN_RAM(a) a 00171 #elif defined (_RAISONANCE_) /* __RCST7__ */ 00172 #define IN_RAM(a) a inram 00173 #else /*_IAR_*/ 00174 #define IN_RAM(a) __ramfunc a 00175 #endif /* _COSMIC_ */ 00176 #else 00177 #define IN_RAM(a) a 00178 #endif /* RAM_EXECUTION */ 00179 00180 /*!< [31:16] STM8S Standard Peripheral Library main version V2.2.0*/ 00181 #define __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02) /*!< [31:24] main version */ 00182 #define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x02) /*!< [23:16] sub1 version */ 00183 #define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */ 00184 #define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */ 00185 #define __STM8S_STDPERIPH_VERSION ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\ 00186 |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\ 00187 |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\ 00188 |(__STM8S_STDPERIPH_VERSION_RC)) 00189 00190 /******************************************************************************/ 00191 00192 /* Includes ------------------------------------------------------------------*/ 00193 00194 /* Exported types and constants ----------------------------------------------*/ 00195 00196 /** @addtogroup Exported_types 00197 * @{ 00198 */ 00199 00200 /** 00201 * IO definitions 00202 * 00203 * define access restrictions to peripheral registers 00204 */ 00205 #define __I volatile const /*!< defines 'read only' permissions */ 00206 #define __O volatile /*!< defines 'write only' permissions */ 00207 #define __IO volatile /*!< defines 'read / write' permissions */ 00208 00209 /*!< Signed integer types */ 00210 typedef signed char int8_t; 00211 typedef signed short int16_t; 00212 typedef signed long int32_t; 00213 00214 /*!< Unsigned integer types */ 00215 typedef unsigned char uint8_t; 00216 typedef unsigned short uint16_t; 00217 typedef unsigned long uint32_t; 00218 00219 /*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */ 00220 00221 typedef int32_t s32; 00222 typedef int16_t s16; 00223 typedef int8_t s8; 00224 00225 typedef uint32_t u32; 00226 typedef uint16_t u16; 00227 typedef uint8_t u8; 00228 00229 00230 typedef enum {FALSE = 0, TRUE = !FALSE} bool; 00231 00232 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction; 00233 00234 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 00235 #define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 00236 00237 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 00238 00239 #define U8_MAX (255) 00240 #define S8_MAX (127) 00241 #define S8_MIN (-128) 00242 #define U16_MAX (65535u) 00243 #define S16_MAX (32767) 00244 #define S16_MIN (-32768) 00245 #define U32_MAX (4294967295uL) 00246 #define S32_MAX (2147483647) 00247 #define S32_MIN (-2147483648uL) 00248 00249 /** 00250 * @} 00251 */ 00252 00253 /** @addtogroup MAP_FILE_Exported_Types_and_Constants 00254 * @{ 00255 */ 00256 00257 /******************************************************************************/ 00258 /* IP registers structures */ 00259 /******************************************************************************/ 00260 00261 /** 00262 * @brief General Purpose I/Os (GPIO) 00263 */ 00264 typedef struct GPIO_struct 00265 { 00266 __IO uint8_t ODR; /*!< Output Data Register */ 00267 __IO uint8_t IDR; /*!< Input Data Register */ 00268 __IO uint8_t DDR; /*!< Data Direction Register */ 00269 __IO uint8_t CR1; /*!< Configuration Register 1 */ 00270 __IO uint8_t CR2; /*!< Configuration Register 2 */ 00271 } 00272 GPIO_TypeDef; 00273 00274 /** @addtogroup GPIO_Registers_Reset_Value 00275 * @{ 00276 */ 00277 00278 #define GPIO_ODR_RESET_VALUE ((uint8_t)0x00) 00279 #define GPIO_DDR_RESET_VALUE ((uint8_t)0x00) 00280 #define GPIO_CR1_RESET_VALUE ((uint8_t)0x00) 00281 #define GPIO_CR2_RESET_VALUE ((uint8_t)0x00) 00282 00283 /** 00284 * @} 00285 */ 00286 00287 /*----------------------------------------------------------------------------*/ 00288 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \ 00289 defined(STM8S903) || defined(STM8AF626x) || defined(STM8AF622x) 00290 /** 00291 * @brief Analog to Digital Converter (ADC1) 00292 */ 00293 typedef struct ADC1_struct 00294 { 00295 __IO uint8_t DB0RH; /*!< ADC1 Data Buffer Register (MSB) */ 00296 __IO uint8_t DB0RL; /*!< ADC1 Data Buffer Register (LSB) */ 00297 __IO uint8_t DB1RH; /*!< ADC1 Data Buffer Register (MSB) */ 00298 __IO uint8_t DB1RL; /*!< ADC1 Data Buffer Register (LSB) */ 00299 __IO uint8_t DB2RH; /*!< ADC1 Data Buffer Register (MSB) */ 00300 __IO uint8_t DB2RL; /*!< ADC1 Data Buffer Register (LSB) */ 00301 __IO uint8_t DB3RH; /*!< ADC1 Data Buffer Register (MSB) */ 00302 __IO uint8_t DB3RL; /*!< ADC1 Data Buffer Register (LSB) */ 00303 __IO uint8_t DB4RH; /*!< ADC1 Data Buffer Register (MSB) */ 00304 __IO uint8_t DB4RL; /*!< ADC1 Data Buffer Register (LSB) */ 00305 __IO uint8_t DB5RH; /*!< ADC1 Data Buffer Register (MSB) */ 00306 __IO uint8_t DB5RL; /*!< ADC1 Data Buffer Register (LSB) */ 00307 __IO uint8_t DB6RH; /*!< ADC1 Data Buffer Register (MSB) */ 00308 __IO uint8_t DB6RL; /*!< ADC1 Data Buffer Register (LSB) */ 00309 __IO uint8_t DB7RH; /*!< ADC1 Data Buffer Register (MSB) */ 00310 __IO uint8_t DB7RL; /*!< ADC1 Data Buffer Register (LSB) */ 00311 __IO uint8_t DB8RH; /*!< ADC1 Data Buffer Register (MSB) */ 00312 __IO uint8_t DB8RL; /*!< ADC1 Data Buffer Register (LSB) */ 00313 __IO uint8_t DB9RH; /*!< ADC1 Data Buffer Register (MSB) */ 00314 __IO uint8_t DB9RL; /*!< ADC1 Data Buffer Register (LSB) */ 00315 uint8_t RESERVED[12]; /*!< Reserved byte */ 00316 __IO uint8_t CSR; /*!< ADC1 control status register */ 00317 __IO uint8_t CR1; /*!< ADC1 configuration register 1 */ 00318 __IO uint8_t CR2; /*!< ADC1 configuration register 2 */ 00319 __IO uint8_t CR3; /*!< ADC1 configuration register 3 */ 00320 __IO uint8_t DRH; /*!< ADC1 Data high */ 00321 __IO uint8_t DRL; /*!< ADC1 Data low */ 00322 __IO uint8_t TDRH; /*!< ADC1 Schmitt trigger disable register high */ 00323 __IO uint8_t TDRL; /*!< ADC1 Schmitt trigger disable register low */ 00324 __IO uint8_t HTRH; /*!< ADC1 high threshold register High*/ 00325 __IO uint8_t HTRL; /*!< ADC1 high threshold register Low*/ 00326 __IO uint8_t LTRH; /*!< ADC1 low threshold register high */ 00327 __IO uint8_t LTRL; /*!< ADC1 low threshold register low */ 00328 __IO uint8_t AWSRH; /*!< ADC1 watchdog status register high */ 00329 __IO uint8_t AWSRL; /*!< ADC1 watchdog status register low */ 00330 __IO uint8_t AWCRH; /*!< ADC1 watchdog control register high */ 00331 __IO uint8_t AWCRL; /*!< ADC1 watchdog control register low */ 00332 } 00333 ADC1_TypeDef; 00334 00335 /** @addtogroup ADC1_Registers_Reset_Value 00336 * @{ 00337 */ 00338 #define ADC1_CSR_RESET_VALUE ((uint8_t)0x00) 00339 #define ADC1_CR1_RESET_VALUE ((uint8_t)0x00) 00340 #define ADC1_CR2_RESET_VALUE ((uint8_t)0x00) 00341 #define ADC1_CR3_RESET_VALUE ((uint8_t)0x00) 00342 #define ADC1_TDRL_RESET_VALUE ((uint8_t)0x00) 00343 #define ADC1_TDRH_RESET_VALUE ((uint8_t)0x00) 00344 #define ADC1_HTRL_RESET_VALUE ((uint8_t)0x03) 00345 #define ADC1_HTRH_RESET_VALUE ((uint8_t)0xFF) 00346 #define ADC1_LTRH_RESET_VALUE ((uint8_t)0x00) 00347 #define ADC1_LTRL_RESET_VALUE ((uint8_t)0x00) 00348 #define ADC1_AWCRH_RESET_VALUE ((uint8_t)0x00) 00349 #define ADC1_AWCRL_RESET_VALUE ((uint8_t)0x00) 00350 /** 00351 * @} 00352 */ 00353 00354 /** @addtogroup ADC1_Registers_Bits_Definition 00355 * @{ 00356 */ 00357 #define ADC1_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */ 00358 #define ADC1_CSR_AWD ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */ 00359 #define ADC1_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */ 00360 #define ADC1_CSR_AWDIE ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable mask */ 00361 #define ADC1_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */ 00362 00363 #define ADC1_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */ 00364 #define ADC1_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */ 00365 #define ADC1_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */ 00366 00367 #define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */ 00368 #define ADC1_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */ 00369 #define ADC1_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */ 00370 #define ADC1_CR2_SCAN ((uint8_t)0x02) /*!< Scan mode mask */ 00371 00372 #define ADC1_CR3_DBUF ((uint8_t)0x80) /*!< Data Buffer Enable mask */ 00373 #define ADC1_CR3_OVR ((uint8_t)0x40) /*!< Overrun Status Flag mask */ 00374 00375 #endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) || (STM8AF622x) */ 00376 /** 00377 * @} 00378 */ 00379 00380 /*----------------------------------------------------------------------------*/ 00381 /** 00382 * @brief Analog to Digital Converter (ADC2) 00383 */ 00384 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax) 00385 typedef struct ADC2_struct 00386 { 00387 __IO uint8_t CSR; /*!< ADC2 control status register */ 00388 __IO uint8_t CR1; /*!< ADC2 configuration register 1 */ 00389 __IO uint8_t CR2; /*!< ADC2 configuration register 2 */ 00390 uint8_t RESERVED; /*!< Reserved byte */ 00391 __IO uint8_t DRH; /*!< ADC2 Data high */ 00392 __IO uint8_t DRL; /*!< ADC2 Data low */ 00393 __IO uint8_t TDRH; /*!< ADC2 Schmitt trigger disable register high */ 00394 __IO uint8_t TDRL; /*!< ADC2 Schmitt trigger disable register low */ 00395 } 00396 ADC2_TypeDef; 00397 00398 /** @addtogroup ADC2_Registers_Reset_Value 00399 * @{ 00400 */ 00401 #define ADC2_CSR_RESET_VALUE ((uint8_t)0x00) 00402 #define ADC2_CR1_RESET_VALUE ((uint8_t)0x00) 00403 #define ADC2_CR2_RESET_VALUE ((uint8_t)0x00) 00404 #define ADC2_TDRL_RESET_VALUE ((uint8_t)0x00) 00405 #define ADC2_TDRH_RESET_VALUE ((uint8_t)0x00) 00406 /** 00407 * @} 00408 */ 00409 00410 /** @addtogroup ADC2_Registers_Bits_Definition 00411 * @{ 00412 */ 00413 #define ADC2_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */ 00414 #define ADC2_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */ 00415 #define ADC2_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */ 00416 00417 #define ADC2_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */ 00418 #define ADC2_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */ 00419 #define ADC2_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */ 00420 00421 #define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */ 00422 #define ADC2_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */ 00423 #define ADC2_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */ 00424 00425 #endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) || (STM8AF52Ax) */ 00426 /** 00427 * @} 00428 */ 00429 00430 /*----------------------------------------------------------------------------*/ 00431 00432 /** 00433 * @brief Auto Wake Up (AWU) peripheral registers. 00434 */ 00435 typedef struct AWU_struct 00436 { 00437 __IO uint8_t CSR; /*!< AWU Control status register */ 00438 __IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */ 00439 __IO uint8_t TBR; /*!< AWU Time base selection register */ 00440 } 00441 AWU_TypeDef; 00442 00443 /** @addtogroup AWU_Registers_Reset_Value 00444 * @{ 00445 */ 00446 #define AWU_CSR_RESET_VALUE ((uint8_t)0x00) 00447 #define AWU_APR_RESET_VALUE ((uint8_t)0x3F) 00448 #define AWU_TBR_RESET_VALUE ((uint8_t)0x00) 00449 00450 /** 00451 * @} 00452 */ 00453 00454 /** @addtogroup AWU_Registers_Bits_Definition 00455 * @{ 00456 */ 00457 00458 #define AWU_CSR_AWUF ((uint8_t)0x20) /*!< Interrupt flag mask */ 00459 #define AWU_CSR_AWUEN ((uint8_t)0x10) /*!< Auto Wake-up enable mask */ 00460 #define AWU_CSR_MSR ((uint8_t)0x01) /*!< LSI Measurement enable mask */ 00461 00462 #define AWU_APR_APR ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */ 00463 00464 #define AWU_TBR_AWUTB ((uint8_t)0x0F) /*!< Timebase selection mask */ 00465 00466 /** 00467 * @} 00468 */ 00469 00470 /*----------------------------------------------------------------------------*/ 00471 /** 00472 * @brief Beeper (BEEP) peripheral registers. 00473 */ 00474 00475 typedef struct BEEP_struct 00476 { 00477 __IO uint8_t CSR; /*!< BEEP Control status register */ 00478 } 00479 BEEP_TypeDef; 00480 00481 /** @addtogroup BEEP_Registers_Reset_Value 00482 * @{ 00483 */ 00484 #define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F) 00485 /** 00486 * @} 00487 */ 00488 00489 /** @addtogroup BEEP_Registers_Bits_Definition 00490 * @{ 00491 */ 00492 #define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */ 00493 #define BEEP_CSR_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */ 00494 #define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */ 00495 /** 00496 * @} 00497 */ 00498 00499 /*----------------------------------------------------------------------------*/ 00500 /** 00501 * @brief Clock Controller (CLK) 00502 */ 00503 typedef struct CLK_struct 00504 { 00505 __IO uint8_t ICKR; /*!< Internal Clocks Control Register */ 00506 __IO uint8_t ECKR; /*!< External Clocks Control Register */ 00507 uint8_t RESERVED; /*!< Reserved byte */ 00508 __IO uint8_t CMSR; /*!< Clock Master Status Register */ 00509 __IO uint8_t SWR; /*!< Clock Master Switch Register */ 00510 __IO uint8_t SWCR; /*!< Switch Control Register */ 00511 __IO uint8_t CKDIVR; /*!< Clock Divider Register */ 00512 __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */ 00513 __IO uint8_t CSSR; /*!< Clock Security System Register */ 00514 __IO uint8_t CCOR; /*!< Configurable Clock Output Register */ 00515 __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */ 00516 uint8_t RESERVED1; /*!< Reserved byte */ 00517 __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */ 00518 __IO uint8_t SWIMCCR; /*!< SWIM clock control register */ 00519 } 00520 CLK_TypeDef; 00521 00522 /** @addtogroup CLK_Registers_Reset_Value 00523 * @{ 00524 */ 00525 00526 #define CLK_ICKR_RESET_VALUE ((uint8_t)0x01) 00527 #define CLK_ECKR_RESET_VALUE ((uint8_t)0x00) 00528 #define CLK_CMSR_RESET_VALUE ((uint8_t)0xE1) 00529 #define CLK_SWR_RESET_VALUE ((uint8_t)0xE1) 00530 #define CLK_SWCR_RESET_VALUE ((uint8_t)0x00) 00531 #define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18) 00532 #define CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF) 00533 #define CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF) 00534 #define CLK_CSSR_RESET_VALUE ((uint8_t)0x00) 00535 #define CLK_CCOR_RESET_VALUE ((uint8_t)0x00) 00536 #define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00) 00537 #define CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00) 00538 00539 /** 00540 * @} 00541 */ 00542 00543 /** @addtogroup CLK_Registers_Bits_Definition 00544 * @{ 00545 */ 00546 #define CLK_ICKR_SWUAH ((uint8_t)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */ 00547 #define CLK_ICKR_LSIRDY ((uint8_t)0x10) /*!< Low speed internal oscillator ready */ 00548 #define CLK_ICKR_LSIEN ((uint8_t)0x08) /*!< Low speed internal RC oscillator enable */ 00549 #define CLK_ICKR_FHWU ((uint8_t)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */ 00550 #define CLK_ICKR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */ 00551 #define CLK_ICKR_HSIEN ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */ 00552 00553 #define CLK_ECKR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */ 00554 #define CLK_ECKR_HSEEN ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */ 00555 00556 #define CLK_CMSR_CKM ((uint8_t)0xFF) /*!< Clock master status bits */ 00557 00558 #define CLK_SWR_SWI ((uint8_t)0xFF) /*!< Clock master selection bits */ 00559 00560 #define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */ 00561 #define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */ 00562 #define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */ 00563 #define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy flag*/ 00564 00565 #define CLK_CKDIVR_HSIDIV ((uint8_t)0x18) /*!< High speed internal clock prescaler */ 00566 #define CLK_CKDIVR_CPUDIV ((uint8_t)0x07) /*!< CPU clock prescaler */ 00567 00568 #define CLK_PCKENR1_TIM1 ((uint8_t)0x80) /*!< Timer 1 clock enable */ 00569 #define CLK_PCKENR1_TIM3 ((uint8_t)0x40) /*!< Timer 3 clock enable */ 00570 #define CLK_PCKENR1_TIM2 ((uint8_t)0x20) /*!< Timer 2 clock enable */ 00571 #define CLK_PCKENR1_TIM5 ((uint8_t)0x20) /*!< Timer 5 clock enable */ 00572 #define CLK_PCKENR1_TIM4 ((uint8_t)0x10) /*!< Timer 4 clock enable */ 00573 #define CLK_PCKENR1_TIM6 ((uint8_t)0x10) /*!< Timer 6 clock enable */ 00574 #define CLK_PCKENR1_UART3 ((uint8_t)0x08) /*!< UART3 clock enable */ 00575 #define CLK_PCKENR1_UART2 ((uint8_t)0x08) /*!< UART2 clock enable */ 00576 #define CLK_PCKENR1_UART1 ((uint8_t)0x04) /*!< UART1 clock enable */ 00577 #define CLK_PCKENR1_SPI ((uint8_t)0x02) /*!< SPI clock enable */ 00578 #define CLK_PCKENR1_I2C ((uint8_t)0x01) /*!< I2C clock enable */ 00579 00580 #define CLK_PCKENR2_CAN ((uint8_t)0x80) /*!< CAN clock enable */ 00581 #define CLK_PCKENR2_ADC ((uint8_t)0x08) /*!< ADC clock enable */ 00582 #define CLK_PCKENR2_AWU ((uint8_t)0x04) /*!< AWU clock enable */ 00583 00584 #define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security system detection */ 00585 #define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */ 00586 #define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */ 00587 #define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */ 00588 00589 #define CLK_CCOR_CCOBSY ((uint8_t)0x40) /*!< Configurable clock output busy */ 00590 #define CLK_CCOR_CCORDY ((uint8_t)0x20) /*!< Configurable clock output ready */ 00591 #define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */ 00592 #define CLK_CCOR_CCOEN ((uint8_t)0x01) /*!< Configurable clock output enable */ 00593 00594 #define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator trimmer */ 00595 00596 #define CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */ 00597 00598 /** 00599 * @} 00600 */ 00601 00602 /*----------------------------------------------------------------------------*/ 00603 /** 00604 * @brief 16-bit timer with complementary PWM outputs (TIM1) 00605 */ 00606 00607 typedef struct TIM1_struct 00608 { 00609 __IO uint8_t CR1; /*!< control register 1 */ 00610 __IO uint8_t CR2; /*!< control register 2 */ 00611 __IO uint8_t SMCR; /*!< Synchro mode control register */ 00612 __IO uint8_t ETR; /*!< external trigger register */ 00613 __IO uint8_t IER; /*!< interrupt enable register*/ 00614 __IO uint8_t SR1; /*!< status register 1 */ 00615 __IO uint8_t SR2; /*!< status register 2 */ 00616 __IO uint8_t EGR; /*!< event generation register */ 00617 __IO uint8_t CCMR1; /*!< CC mode register 1 */ 00618 __IO uint8_t CCMR2; /*!< CC mode register 2 */ 00619 __IO uint8_t CCMR3; /*!< CC mode register 3 */ 00620 __IO uint8_t CCMR4; /*!< CC mode register 4 */ 00621 __IO uint8_t CCER1; /*!< CC enable register 1 */ 00622 __IO uint8_t CCER2; /*!< CC enable register 2 */ 00623 __IO uint8_t CNTRH; /*!< counter high */ 00624 __IO uint8_t CNTRL; /*!< counter low */ 00625 __IO uint8_t PSCRH; /*!< prescaler high */ 00626 __IO uint8_t PSCRL; /*!< prescaler low */ 00627 __IO uint8_t ARRH; /*!< auto-reload register high */ 00628 __IO uint8_t ARRL; /*!< auto-reload register low */ 00629 __IO uint8_t RCR; /*!< Repetition Counter register */ 00630 __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ 00631 __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ 00632 __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ 00633 __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ 00634 __IO uint8_t CCR3H; /*!< capture/compare register 3 high */ 00635 __IO uint8_t CCR3L; /*!< capture/compare register 3 low */ 00636 __IO uint8_t CCR4H; /*!< capture/compare register 3 high */ 00637 __IO uint8_t CCR4L; /*!< capture/compare register 3 low */ 00638 __IO uint8_t BKR; /*!< Break Register */ 00639 __IO uint8_t DTR; /*!< dead-time register */ 00640 __IO uint8_t OISR; /*!< Output idle register */ 00641 } 00642 TIM1_TypeDef; 00643 00644 /** @addtogroup TIM1_Registers_Reset_Value 00645 * @{ 00646 */ 00647 00648 #define TIM1_CR1_RESET_VALUE ((uint8_t)0x00) 00649 #define TIM1_CR2_RESET_VALUE ((uint8_t)0x00) 00650 #define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00) 00651 #define TIM1_ETR_RESET_VALUE ((uint8_t)0x00) 00652 #define TIM1_IER_RESET_VALUE ((uint8_t)0x00) 00653 #define TIM1_SR1_RESET_VALUE ((uint8_t)0x00) 00654 #define TIM1_SR2_RESET_VALUE ((uint8_t)0x00) 00655 #define TIM1_EGR_RESET_VALUE ((uint8_t)0x00) 00656 #define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00) 00657 #define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00) 00658 #define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00) 00659 #define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00) 00660 #define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00) 00661 #define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00) 00662 #define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00) 00663 #define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00) 00664 #define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00) 00665 #define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00) 00666 #define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF) 00667 #define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF) 00668 #define TIM1_RCR_RESET_VALUE ((uint8_t)0x00) 00669 #define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00) 00670 #define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00) 00671 #define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00) 00672 #define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00) 00673 #define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00) 00674 #define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00) 00675 #define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00) 00676 #define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00) 00677 #define TIM1_BKR_RESET_VALUE ((uint8_t)0x00) 00678 #define TIM1_DTR_RESET_VALUE ((uint8_t)0x00) 00679 #define TIM1_OISR_RESET_VALUE ((uint8_t)0x00) 00680 00681 /** 00682 * @} 00683 */ 00684 00685 /** @addtogroup TIM1_Registers_Bits_Definition 00686 * @{ 00687 */ 00688 /* CR1*/ 00689 #define TIM1_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 00690 #define TIM1_CR1_CMS ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */ 00691 #define TIM1_CR1_DIR ((uint8_t)0x10) /*!< Direction mask. */ 00692 #define TIM1_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 00693 #define TIM1_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 00694 #define TIM1_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 00695 #define TIM1_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 00696 /* CR2*/ 00697 #define TIM1_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection mask. */ 00698 #define TIM1_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection mask. */ 00699 #define TIM1_CR2_COMS ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */ 00700 #define TIM1_CR2_CCPC ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */ 00701 /* SMCR*/ 00702 #define TIM1_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode mask. */ 00703 #define TIM1_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection mask. */ 00704 #define TIM1_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection mask. */ 00705 /*ETR*/ 00706 #define TIM1_ETR_ETP ((uint8_t)0x80) /*!< External Trigger Polarity mask. */ 00707 #define TIM1_ETR_ECE ((uint8_t)0x40)/*!< External Clock mask. */ 00708 #define TIM1_ETR_ETPS ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */ 00709 #define TIM1_ETR_ETF ((uint8_t)0x0F) /*!< External Trigger Filter mask. */ 00710 /*IER*/ 00711 #define TIM1_IER_BIE ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */ 00712 #define TIM1_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */ 00713 #define TIM1_IER_COMIE ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/ 00714 #define TIM1_IER_CC4IE ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */ 00715 #define TIM1_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ 00716 #define TIM1_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ 00717 #define TIM1_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ 00718 #define TIM1_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 00719 /*SR1*/ 00720 #define TIM1_SR1_BIF ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */ 00721 #define TIM1_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */ 00722 #define TIM1_SR1_COMIF ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */ 00723 #define TIM1_SR1_CC4IF ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */ 00724 #define TIM1_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ 00725 #define TIM1_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ 00726 #define TIM1_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ 00727 #define TIM1_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 00728 /*SR2*/ 00729 #define TIM1_SR2_CC4OF ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */ 00730 #define TIM1_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ 00731 #define TIM1_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ 00732 #define TIM1_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ 00733 /*EGR*/ 00734 #define TIM1_EGR_BG ((uint8_t)0x80) /*!< Break Generation mask. */ 00735 #define TIM1_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */ 00736 #define TIM1_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */ 00737 #define TIM1_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */ 00738 #define TIM1_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */ 00739 #define TIM1_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ 00740 #define TIM1_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ 00741 #define TIM1_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 00742 /*CCMR*/ 00743 #define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ 00744 #define TIM1_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ 00745 #define TIM1_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ 00746 #define TIM1_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ 00747 #define TIM1_CCMR_OCxFE ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */ 00748 #define TIM1_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ 00749 00750 #define CCMR_TIxDirect_Set ((uint8_t)0x01) 00751 /*CCER1*/ 00752 #define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */ 00753 #define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */ 00754 #define TIM1_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ 00755 #define TIM1_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ 00756 #define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */ 00757 #define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */ 00758 #define TIM1_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ 00759 #define TIM1_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ 00760 /*CCER2*/ 00761 #define TIM1_CCER2_CC4P ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity mask. */ 00762 #define TIM1_CCER2_CC4E ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask. */ 00763 #define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */ 00764 #define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */ 00765 #define TIM1_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */ 00766 #define TIM1_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */ 00767 /*CNTRH*/ 00768 #define TIM1_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ 00769 /*CNTRL*/ 00770 #define TIM1_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 00771 /*PSCH*/ 00772 #define TIM1_PSCH_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ 00773 /*PSCL*/ 00774 #define TIM1_PSCL_PSC ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */ 00775 /*ARR*/ 00776 #define TIM1_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ 00777 #define TIM1_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ 00778 /*RCR*/ 00779 #define TIM1_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */ 00780 /*CCR1*/ 00781 #define TIM1_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ 00782 #define TIM1_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ 00783 /*CCR2*/ 00784 #define TIM1_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ 00785 #define TIM1_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ 00786 /*CCR3*/ 00787 #define TIM1_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ 00788 #define TIM1_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ 00789 /*CCR4*/ 00790 #define TIM1_CCR4H_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */ 00791 #define TIM1_CCR4L_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */ 00792 /*BKR*/ 00793 #define TIM1_BKR_MOE ((uint8_t)0x80) /*!< Main Output Enable mask. */ 00794 #define TIM1_BKR_AOE ((uint8_t)0x40) /*!< Automatic Output Enable mask. */ 00795 #define TIM1_BKR_BKP ((uint8_t)0x20) /*!< Break Polarity mask. */ 00796 #define TIM1_BKR_BKE ((uint8_t)0x10) /*!< Break Enable mask. */ 00797 #define TIM1_BKR_OSSR ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */ 00798 #define TIM1_BKR_OSSI ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */ 00799 #define TIM1_BKR_LOCK ((uint8_t)0x03) /*!< Lock Configuration mask. */ 00800 /*DTR*/ 00801 #define TIM1_DTR_DTG ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */ 00802 /*OISR*/ 00803 #define TIM1_OISR_OIS4 ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output) mask. */ 00804 #define TIM1_OISR_OIS3N ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */ 00805 #define TIM1_OISR_OIS3 ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */ 00806 #define TIM1_OISR_OIS2N ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */ 00807 #define TIM1_OISR_OIS2 ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */ 00808 #define TIM1_OISR_OIS1N ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */ 00809 #define TIM1_OISR_OIS1 ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */ 00810 /** 00811 * @} 00812 */ 00813 00814 /*----------------------------------------------------------------------------*/ 00815 /** 00816 * @brief 16-bit timer (TIM2) 00817 */ 00818 00819 typedef struct TIM2_struct 00820 { 00821 __IO uint8_t CR1; /*!< control register 1 */ 00822 #if defined(STM8S103) || defined(STM8S003) 00823 uint8_t RESERVED1; /*!< Reserved register */ 00824 uint8_t RESERVED2; /*!< Reserved register */ 00825 #endif 00826 __IO uint8_t IER; /*!< interrupt enable register */ 00827 __IO uint8_t SR1; /*!< status register 1 */ 00828 __IO uint8_t SR2; /*!< status register 2 */ 00829 __IO uint8_t EGR; /*!< event generation register */ 00830 __IO uint8_t CCMR1; /*!< CC mode register 1 */ 00831 __IO uint8_t CCMR2; /*!< CC mode register 2 */ 00832 __IO uint8_t CCMR3; /*!< CC mode register 3 */ 00833 __IO uint8_t CCER1; /*!< CC enable register 1 */ 00834 __IO uint8_t CCER2; /*!< CC enable register 2 */ 00835 __IO uint8_t CNTRH; /*!< counter high */ 00836 __IO uint8_t CNTRL; /*!< counter low */ 00837 __IO uint8_t PSCR; /*!< prescaler register */ 00838 __IO uint8_t ARRH; /*!< auto-reload register high */ 00839 __IO uint8_t ARRL; /*!< auto-reload register low */ 00840 __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ 00841 __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ 00842 __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ 00843 __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ 00844 __IO uint8_t CCR3H; /*!< capture/compare register 3 high */ 00845 __IO uint8_t CCR3L; /*!< capture/compare register 3 low */ 00846 } 00847 TIM2_TypeDef; 00848 00849 /** @addtogroup TIM2_Registers_Reset_Value 00850 * @{ 00851 */ 00852 00853 #define TIM2_CR1_RESET_VALUE ((uint8_t)0x00) 00854 #define TIM2_IER_RESET_VALUE ((uint8_t)0x00) 00855 #define TIM2_SR1_RESET_VALUE ((uint8_t)0x00) 00856 #define TIM2_SR2_RESET_VALUE ((uint8_t)0x00) 00857 #define TIM2_EGR_RESET_VALUE ((uint8_t)0x00) 00858 #define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00) 00859 #define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00) 00860 #define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00) 00861 #define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00) 00862 #define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00) 00863 #define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00) 00864 #define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00) 00865 #define TIM2_PSCR_RESET_VALUE ((uint8_t)0x00) 00866 #define TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF) 00867 #define TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF) 00868 #define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00) 00869 #define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00) 00870 #define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00) 00871 #define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00) 00872 #define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00) 00873 #define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00) 00874 00875 /** 00876 * @} 00877 */ 00878 00879 /** @addtogroup TIM2_Registers_Bits_Definition 00880 * @{ 00881 */ 00882 /*CR1*/ 00883 #define TIM2_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 00884 #define TIM2_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 00885 #define TIM2_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 00886 #define TIM2_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 00887 #define TIM2_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 00888 /*IER*/ 00889 #define TIM2_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ 00890 #define TIM2_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ 00891 #define TIM2_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ 00892 #define TIM2_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 00893 /*SR1*/ 00894 #define TIM2_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ 00895 #define TIM2_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ 00896 #define TIM2_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ 00897 #define TIM2_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 00898 /*SR2*/ 00899 #define TIM2_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ 00900 #define TIM2_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ 00901 #define TIM2_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ 00902 /*EGR*/ 00903 #define TIM2_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */ 00904 #define TIM2_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ 00905 #define TIM2_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ 00906 #define TIM2_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 00907 /*CCMR*/ 00908 #define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ 00909 #define TIM2_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ 00910 #define TIM2_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ 00911 #define TIM2_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ 00912 #define TIM2_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ 00913 /*CCER1*/ 00914 #define TIM2_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ 00915 #define TIM2_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ 00916 #define TIM2_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ 00917 #define TIM2_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ 00918 /*CCER2*/ 00919 #define TIM2_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */ 00920 #define TIM2_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */ 00921 /*CNTR*/ 00922 #define TIM2_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ 00923 #define TIM2_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 00924 /*PSCR*/ 00925 #define TIM2_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ 00926 /*ARR*/ 00927 #define TIM2_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ 00928 #define TIM2_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ 00929 /*CCR1*/ 00930 #define TIM2_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ 00931 #define TIM2_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ 00932 /*CCR2*/ 00933 #define TIM2_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ 00934 #define TIM2_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ 00935 /*CCR3*/ 00936 #define TIM2_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ 00937 #define TIM2_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ 00938 00939 /** 00940 * @} 00941 */ 00942 00943 /*----------------------------------------------------------------------------*/ 00944 /** 00945 * @brief 16-bit timer (TIM3) 00946 */ 00947 typedef struct TIM3_struct 00948 { 00949 __IO uint8_t CR1; /*!< control register 1 */ 00950 __IO uint8_t IER; /*!< interrupt enable register */ 00951 __IO uint8_t SR1; /*!< status register 1 */ 00952 __IO uint8_t SR2; /*!< status register 2 */ 00953 __IO uint8_t EGR; /*!< event generation register */ 00954 __IO uint8_t CCMR1; /*!< CC mode register 1 */ 00955 __IO uint8_t CCMR2; /*!< CC mode register 2 */ 00956 __IO uint8_t CCER1; /*!< CC enable register 1 */ 00957 __IO uint8_t CNTRH; /*!< counter high */ 00958 __IO uint8_t CNTRL; /*!< counter low */ 00959 __IO uint8_t PSCR; /*!< prescaler register */ 00960 __IO uint8_t ARRH; /*!< auto-reload register high */ 00961 __IO uint8_t ARRL; /*!< auto-reload register low */ 00962 __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ 00963 __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ 00964 __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ 00965 __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ 00966 } 00967 TIM3_TypeDef; 00968 00969 /** @addtogroup TIM3_Registers_Reset_Value 00970 * @{ 00971 */ 00972 00973 #define TIM3_CR1_RESET_VALUE ((uint8_t)0x00) 00974 #define TIM3_IER_RESET_VALUE ((uint8_t)0x00) 00975 #define TIM3_SR1_RESET_VALUE ((uint8_t)0x00) 00976 #define TIM3_SR2_RESET_VALUE ((uint8_t)0x00) 00977 #define TIM3_EGR_RESET_VALUE ((uint8_t)0x00) 00978 #define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00) 00979 #define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00) 00980 #define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00) 00981 #define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00) 00982 #define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00) 00983 #define TIM3_PSCR_RESET_VALUE ((uint8_t)0x00) 00984 #define TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF) 00985 #define TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF) 00986 #define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00) 00987 #define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00) 00988 #define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00) 00989 #define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00) 00990 00991 /** 00992 * @} 00993 */ 00994 00995 /** @addtogroup TIM3_Registers_Bits_Definition 00996 * @{ 00997 */ 00998 /*CR1*/ 00999 #define TIM3_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 01000 #define TIM3_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 01001 #define TIM3_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 01002 #define TIM3_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 01003 #define TIM3_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 01004 /*IER*/ 01005 #define TIM3_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ 01006 #define TIM3_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ 01007 #define TIM3_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 01008 /*SR1*/ 01009 #define TIM3_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ 01010 #define TIM3_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ 01011 #define TIM3_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 01012 /*SR2*/ 01013 #define TIM3_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ 01014 #define TIM3_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ 01015 /*EGR*/ 01016 #define TIM3_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ 01017 #define TIM3_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ 01018 #define TIM3_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 01019 /*CCMR*/ 01020 #define TIM3_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ 01021 #define TIM3_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ 01022 #define TIM3_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ 01023 #define TIM3_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ 01024 #define TIM3_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ 01025 /*CCER1*/ 01026 #define TIM3_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ 01027 #define TIM3_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ 01028 #define TIM3_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ 01029 #define TIM3_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ 01030 /*CNTR*/ 01031 #define TIM3_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ 01032 #define TIM3_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 01033 /*PSCR*/ 01034 #define TIM3_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ 01035 /*ARR*/ 01036 #define TIM3_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ 01037 #define TIM3_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ 01038 /*CCR1*/ 01039 #define TIM3_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ 01040 #define TIM3_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ 01041 /*CCR2*/ 01042 #define TIM3_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ 01043 #define TIM3_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ 01044 /** 01045 * @} 01046 */ 01047 01048 /*----------------------------------------------------------------------------*/ 01049 /** 01050 * @brief 8-bit system timer (TIM4) 01051 */ 01052 01053 typedef struct TIM4_struct 01054 { 01055 __IO uint8_t CR1; /*!< control register 1 */ 01056 #if defined(STM8S103) || defined(STM8S003) 01057 uint8_t RESERVED1; /*!< Reserved register */ 01058 uint8_t RESERVED2; /*!< Reserved register */ 01059 #endif 01060 __IO uint8_t IER; /*!< interrupt enable register */ 01061 __IO uint8_t SR1; /*!< status register 1 */ 01062 __IO uint8_t EGR; /*!< event generation register */ 01063 __IO uint8_t CNTR; /*!< counter register */ 01064 __IO uint8_t PSCR; /*!< prescaler register */ 01065 __IO uint8_t ARR; /*!< auto-reload register */ 01066 } 01067 TIM4_TypeDef; 01068 01069 /** @addtogroup TIM4_Registers_Reset_Value 01070 * @{ 01071 */ 01072 01073 #define TIM4_CR1_RESET_VALUE ((uint8_t)0x00) 01074 #define TIM4_IER_RESET_VALUE ((uint8_t)0x00) 01075 #define TIM4_SR1_RESET_VALUE ((uint8_t)0x00) 01076 #define TIM4_EGR_RESET_VALUE ((uint8_t)0x00) 01077 #define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00) 01078 #define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00) 01079 #define TIM4_ARR_RESET_VALUE ((uint8_t)0xFF) 01080 01081 /** 01082 * @} 01083 */ 01084 01085 /** @addtogroup TIM4_Registers_Bits_Definition 01086 * @{ 01087 */ 01088 /*CR1*/ 01089 #define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 01090 #define TIM4_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 01091 #define TIM4_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 01092 #define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 01093 #define TIM4_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 01094 /*IER*/ 01095 #define TIM4_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 01096 /*SR1*/ 01097 #define TIM4_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 01098 /*EGR*/ 01099 #define TIM4_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 01100 /*CNTR*/ 01101 #define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 01102 /*PSCR*/ 01103 #define TIM4_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value mask. */ 01104 /*ARR*/ 01105 #define TIM4_ARR_ARR ((uint8_t)0xFF) /*!< Autoreload Value mask. */ 01106 01107 /** 01108 * @} 01109 */ 01110 01111 /*----------------------------------------------------------------------------*/ 01112 /** 01113 * @brief 16-bit timer with synchro module (TIM5) 01114 */ 01115 01116 typedef struct TIM5_struct 01117 { 01118 __IO uint8_t CR1; /*!<TIM5 Control Register 1 */ 01119 __IO uint8_t CR2; /*!<TIM5 Control Register 2 */ 01120 __IO uint8_t SMCR; /*!<TIM5 Slave Mode Control Register */ 01121 __IO uint8_t IER; /*!<TIM5 Interrupt Enable Register */ 01122 __IO uint8_t SR1; /*!<TIM5 Status Register 1 */ 01123 __IO uint8_t SR2; /*!<TIM5 Status Register 2 */ 01124 __IO uint8_t EGR; /*!<TIM5 Event Generation Register */ 01125 __IO uint8_t CCMR1; /*!<TIM5 Capture/Compare Mode Register 1 */ 01126 __IO uint8_t CCMR2; /*!<TIM5 Capture/Compare Mode Register 2 */ 01127 __IO uint8_t CCMR3; /*!<TIM5 Capture/Compare Mode Register 3 */ 01128 __IO uint8_t CCER1; /*!<TIM5 Capture/Compare Enable Register 1 */ 01129 __IO uint8_t CCER2; /*!<TIM5 Capture/Compare Enable Register 2 */ 01130 __IO uint8_t CNTRH; /*!<TIM5 Counter High */ 01131 __IO uint8_t CNTRL; /*!<TIM5 Counter Low */ 01132 __IO uint8_t PSCR; /*!<TIM5 Prescaler Register */ 01133 __IO uint8_t ARRH; /*!<TIM5 Auto-Reload Register High */ 01134 __IO uint8_t ARRL; /*!<TIM5 Auto-Reload Register Low */ 01135 __IO uint8_t CCR1H; /*!<TIM5 Capture/Compare Register 1 High */ 01136 __IO uint8_t CCR1L; /*!<TIM5 Capture/Compare Register 1 Low */ 01137 __IO uint8_t CCR2H; /*!<TIM5 Capture/Compare Register 2 High */ 01138 __IO uint8_t CCR2L; /*!<TIM5 Capture/Compare Register 2 Low */ 01139 __IO uint8_t CCR3H; /*!<TIM5 Capture/Compare Register 3 High */ 01140 __IO uint8_t CCR3L; /*!<TIM5 Capture/Compare Register 3 Low */ 01141 }TIM5_TypeDef; 01142 01143 /** @addtogroup TIM5_Registers_Reset_Value 01144 * @{ 01145 */ 01146 01147 #define TIM5_CR1_RESET_VALUE ((uint8_t)0x00) 01148 #define TIM5_CR2_RESET_VALUE ((uint8_t)0x00) 01149 #define TIM5_SMCR_RESET_VALUE ((uint8_t)0x00) 01150 #define TIM5_IER_RESET_VALUE ((uint8_t)0x00) 01151 #define TIM5_SR1_RESET_VALUE ((uint8_t)0x00) 01152 #define TIM5_SR2_RESET_VALUE ((uint8_t)0x00) 01153 #define TIM5_EGR_RESET_VALUE ((uint8_t)0x00) 01154 #define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00) 01155 #define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00) 01156 #define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00) 01157 #define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00) 01158 #define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00) 01159 #define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00) 01160 #define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00) 01161 #define TIM5_PSCR_RESET_VALUE ((uint8_t)0x00) 01162 #define TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF) 01163 #define TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF) 01164 #define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00) 01165 #define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00) 01166 #define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00) 01167 #define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00) 01168 #define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00) 01169 #define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00) 01170 01171 /** 01172 * @} 01173 */ 01174 01175 /** @addtogroup TIM5_Registers_Bits_Definition 01176 * @{ 01177 */ 01178 /* CR1*/ 01179 #define TIM5_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 01180 #define TIM5_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 01181 #define TIM5_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 01182 #define TIM5_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 01183 #define TIM5_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 01184 /* CR2*/ 01185 #define TIM5_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection Mask. */ 01186 #define TIM5_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */ 01187 /* SMCR*/ 01188 #define TIM5_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */ 01189 #define TIM5_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */ 01190 #define TIM5_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */ 01191 /*IER*/ 01192 #define TIM5_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */ 01193 #define TIM5_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ 01194 #define TIM5_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ 01195 #define TIM5_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ 01196 #define TIM5_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 01197 /*SR1*/ 01198 #define TIM5_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */ 01199 #define TIM5_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ 01200 #define TIM5_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ 01201 #define TIM5_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ 01202 #define TIM5_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 01203 /*SR2*/ 01204 #define TIM5_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ 01205 #define TIM5_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ 01206 #define TIM5_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ 01207 /*EGR*/ 01208 #define TIM5_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */ 01209 #define TIM5_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */ 01210 #define TIM5_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ 01211 #define TIM5_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ 01212 #define TIM5_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 01213 /*CCMR*/ 01214 #define TIM5_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ 01215 #define TIM5_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ 01216 #define TIM5_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ 01217 #define TIM5_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ 01218 #define TIM5_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ 01219 /*CCER1*/ 01220 #define TIM5_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ 01221 #define TIM5_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ 01222 #define TIM5_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ 01223 #define TIM5_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ 01224 /*CCER2*/ 01225 #define TIM5_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */ 01226 #define TIM5_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */ 01227 /*CNTR*/ 01228 #define TIM5_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ 01229 #define TIM5_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 01230 /*PSCR*/ 01231 #define TIM5_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ 01232 /*ARR*/ 01233 #define TIM5_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ 01234 #define TIM5_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ 01235 /*CCR1*/ 01236 #define TIM5_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ 01237 #define TIM5_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ 01238 /*CCR2*/ 01239 #define TIM5_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ 01240 #define TIM5_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ 01241 /*CCR3*/ 01242 #define TIM5_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ 01243 #define TIM5_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ 01244 /*CCMR*/ 01245 #define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01) 01246 /** 01247 * @} 01248 */ 01249 01250 /*----------------------------------------------------------------------------*/ 01251 /** 01252 * @brief 8-bit system timer with synchro module(TIM6) 01253 */ 01254 01255 typedef struct TIM6_struct 01256 { 01257 __IO uint8_t CR1; /*!< control register 1 */ 01258 __IO uint8_t CR2; /*!< control register 2 */ 01259 __IO uint8_t SMCR; /*!< Synchro mode control register */ 01260 __IO uint8_t IER; /*!< interrupt enable register */ 01261 __IO uint8_t SR1; /*!< status register 1 */ 01262 __IO uint8_t EGR; /*!< event generation register */ 01263 __IO uint8_t CNTR; /*!< counter register */ 01264 __IO uint8_t PSCR; /*!< prescaler register */ 01265 __IO uint8_t ARR; /*!< auto-reload register */ 01266 } 01267 TIM6_TypeDef; 01268 /** @addtogroup TIM6_Registers_Reset_Value 01269 * @{ 01270 */ 01271 #define TIM6_CR1_RESET_VALUE ((uint8_t)0x00) 01272 #define TIM6_CR2_RESET_VALUE ((uint8_t)0x00) 01273 #define TIM6_SMCR_RESET_VALUE ((uint8_t)0x00) 01274 #define TIM6_IER_RESET_VALUE ((uint8_t)0x00) 01275 #define TIM6_SR1_RESET_VALUE ((uint8_t)0x00) 01276 #define TIM6_EGR_RESET_VALUE ((uint8_t)0x00) 01277 #define TIM6_CNTR_RESET_VALUE ((uint8_t)0x00) 01278 #define TIM6_PSCR_RESET_VALUE ((uint8_t)0x00) 01279 #define TIM6_ARR_RESET_VALUE ((uint8_t)0xFF) 01280 01281 /** 01282 * @} 01283 */ 01284 01285 /** @addtogroup TIM6_Registers_Bits_Definition 01286 * @{ 01287 */ 01288 /* CR1*/ 01289 #define TIM6_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */ 01290 #define TIM6_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode Mask. */ 01291 #define TIM6_CR1_URS ((uint8_t)0x04) /*!< Update Request Source Mask. */ 01292 #define TIM6_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable Mask. */ 01293 #define TIM6_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable Mask. */ 01294 /* CR2*/ 01295 #define TIM6_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */ 01296 /* SMCR*/ 01297 #define TIM6_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */ 01298 #define TIM6_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */ 01299 #define TIM6_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */ 01300 /* IER*/ 01301 #define TIM6_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */ 01302 #define TIM6_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */ 01303 /* SR1*/ 01304 #define TIM6_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */ 01305 #define TIM6_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */ 01306 /* EGR*/ 01307 #define TIM6_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */ 01308 #define TIM6_EGR_UG ((uint8_t)0x01) /*!< Update Generation Mask. */ 01309 /* CNTR*/ 01310 #define TIM6_CNTR_CNT ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */ 01311 /* PSCR*/ 01312 #define TIM6_PSCR_PSC ((uint8_t)0x07) /*!<Prescaler Value Mask. */ 01313 01314 #define TIM6_ARR_ARR ((uint8_t)0xFF) /*!<Autoreload Value Mask. */ 01315 /** 01316 * @} 01317 */ 01318 /*----------------------------------------------------------------------------*/ 01319 /** 01320 * @brief Inter-Integrated Circuit (I2C) 01321 */ 01322 01323 typedef struct I2C_struct 01324 { 01325 __IO uint8_t CR1; /*!< I2C control register 1 */ 01326 __IO uint8_t CR2; /*!< I2C control register 2 */ 01327 __IO uint8_t FREQR; /*!< I2C frequency register */ 01328 __IO uint8_t OARL; /*!< I2C own address register LSB */ 01329 __IO uint8_t OARH; /*!< I2C own address register MSB */ 01330 uint8_t RESERVED1; /*!< Reserved byte */ 01331 __IO uint8_t DR; /*!< I2C data register */ 01332 __IO uint8_t SR1; /*!< I2C status register 1 */ 01333 __IO uint8_t SR2; /*!< I2C status register 2 */ 01334 __IO uint8_t SR3; /*!< I2C status register 3 */ 01335 __IO uint8_t ITR; /*!< I2C interrupt register */ 01336 __IO uint8_t CCRL; /*!< I2C clock control register low */ 01337 __IO uint8_t CCRH; /*!< I2C clock control register high */ 01338 __IO uint8_t TRISER; /*!< I2C maximum rise time register */ 01339 uint8_t RESERVED2; /*!< Reserved byte */ 01340 } 01341 I2C_TypeDef; 01342 01343 /** @addtogroup I2C_Registers_Reset_Value 01344 * @{ 01345 */ 01346 01347 #define I2C_CR1_RESET_VALUE ((uint8_t)0x00) 01348 #define I2C_CR2_RESET_VALUE ((uint8_t)0x00) 01349 #define I2C_FREQR_RESET_VALUE ((uint8_t)0x00) 01350 #define I2C_OARL_RESET_VALUE ((uint8_t)0x00) 01351 #define I2C_OARH_RESET_VALUE ((uint8_t)0x00) 01352 #define I2C_DR_RESET_VALUE ((uint8_t)0x00) 01353 #define I2C_SR1_RESET_VALUE ((uint8_t)0x00) 01354 #define I2C_SR2_RESET_VALUE ((uint8_t)0x00) 01355 #define I2C_SR3_RESET_VALUE ((uint8_t)0x00) 01356 #define I2C_ITR_RESET_VALUE ((uint8_t)0x00) 01357 #define I2C_CCRL_RESET_VALUE ((uint8_t)0x00) 01358 #define I2C_CCRH_RESET_VALUE ((uint8_t)0x00) 01359 #define I2C_TRISER_RESET_VALUE ((uint8_t)0x02) 01360 01361 /** 01362 * @} 01363 */ 01364 01365 /** @addtogroup I2C_Registers_Bits_Definition 01366 * @{ 01367 */ 01368 01369 #define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */ 01370 #define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */ 01371 #define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */ 01372 01373 #define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */ 01374 #define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */ 01375 #define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */ 01376 #define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */ 01377 #define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */ 01378 01379 #define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */ 01380 01381 #define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ 01382 #define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */ 01383 01384 #define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */ 01385 #define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address Mode Configuration */ 01386 #define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */ 01387 01388 #define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */ 01389 01390 #define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */ 01391 #define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */ 01392 #define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */ 01393 #define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */ 01394 #define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */ 01395 #define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */ 01396 #define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */ 01397 01398 #define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */ 01399 #define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */ 01400 #define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */ 01401 #define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */ 01402 #define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */ 01403 01404 #define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */ 01405 #define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */ 01406 #define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */ 01407 #define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */ 01408 01409 #define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */ 01410 #define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */ 01411 #define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */ 01412 01413 #define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */ 01414 01415 #define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */ 01416 #define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */ 01417 #define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */ 01418 01419 #define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 01420 01421 /** 01422 * @} 01423 */ 01424 01425 /*----------------------------------------------------------------------------*/ 01426 /** 01427 * @brief Interrupt Controller (ITC) 01428 */ 01429 01430 typedef struct ITC_struct 01431 { 01432 __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */ 01433 __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */ 01434 __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */ 01435 __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */ 01436 __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */ 01437 __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */ 01438 __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */ 01439 __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */ 01440 } 01441 ITC_TypeDef; 01442 01443 /** @addtogroup ITC_Registers_Reset_Value 01444 * @{ 01445 */ 01446 01447 #define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers */ 01448 01449 /** 01450 * @} 01451 */ 01452 01453 /** @addtogroup CPU_Registers_Bits_Definition 01454 * @{ 01455 */ 01456 01457 #define CPU_CC_I1I0 ((uint8_t)0x28) /*!< Condition Code register, I1 and I0 bits mask */ 01458 01459 /** 01460 * @} 01461 */ 01462 01463 /*----------------------------------------------------------------------------*/ 01464 /** 01465 * @brief External Interrupt Controller (EXTI) 01466 */ 01467 01468 typedef struct EXTI_struct 01469 { 01470 __IO uint8_t CR1; /*!< External Interrupt Control Register for PORTA to PORTD */ 01471 __IO uint8_t CR2; /*!< External Interrupt Control Register for PORTE and TLI */ 01472 } 01473 EXTI_TypeDef; 01474 01475 /** @addtogroup EXTI_Registers_Reset_Value 01476 * @{ 01477 */ 01478 01479 #define EXTI_CR1_RESET_VALUE ((uint8_t)0x00) 01480 #define EXTI_CR2_RESET_VALUE ((uint8_t)0x00) 01481 01482 /** 01483 * @} 01484 */ 01485 01486 /** @addtogroup EXTI_Registers_Bits_Definition 01487 * @{ 01488 */ 01489 01490 #define EXTI_CR1_PDIS ((uint8_t)0xC0) /*!< PORTD external interrupt sensitivity bits mask */ 01491 #define EXTI_CR1_PCIS ((uint8_t)0x30) /*!< PORTC external interrupt sensitivity bits mask */ 01492 #define EXTI_CR1_PBIS ((uint8_t)0x0C) /*!< PORTB external interrupt sensitivity bits mask */ 01493 #define EXTI_CR1_PAIS ((uint8_t)0x03) /*!< PORTA external interrupt sensitivity bits mask */ 01494 01495 #define EXTI_CR2_TLIS ((uint8_t)0x04) /*!< Top level interrupt sensitivity bit mask */ 01496 #define EXTI_CR2_PEIS ((uint8_t)0x03) /*!< PORTE external interrupt sensitivity bits mask */ 01497 01498 /** 01499 * @} 01500 */ 01501 01502 01503 01504 /*----------------------------------------------------------------------------*/ 01505 /** 01506 * @brief FLASH program and Data memory (FLASH) 01507 */ 01508 01509 typedef struct FLASH_struct 01510 { 01511 __IO uint8_t CR1; /*!< Flash control register 1 */ 01512 __IO uint8_t CR2; /*!< Flash control register 2 */ 01513 __IO uint8_t NCR2; /*!< Flash complementary control register 2 */ 01514 __IO uint8_t FPR; /*!< Flash protection register */ 01515 __IO uint8_t NFPR; /*!< Flash complementary protection register */ 01516 __IO uint8_t IAPSR; /*!< Flash in-application programming status register */ 01517 uint8_t RESERVED1; /*!< Reserved byte */ 01518 uint8_t RESERVED2; /*!< Reserved byte */ 01519 __IO uint8_t PUKR; /*!< Flash program memory unprotection register */ 01520 uint8_t RESERVED3; /*!< Reserved byte */ 01521 __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */ 01522 } 01523 FLASH_TypeDef; 01524 01525 /** @addtogroup FLASH_Registers_Reset_Value 01526 * @{ 01527 */ 01528 01529 #define FLASH_CR1_RESET_VALUE ((uint8_t)0x00) 01530 #define FLASH_CR2_RESET_VALUE ((uint8_t)0x00) 01531 #define FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF) 01532 #define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40) 01533 #define FLASH_PUKR_RESET_VALUE ((uint8_t)0x00) 01534 #define FLASH_DUKR_RESET_VALUE ((uint8_t)0x00) 01535 01536 /** 01537 * @} 01538 */ 01539 01540 /** @addtogroup FLASH_Registers_Bits_Definition 01541 * @{ 01542 */ 01543 01544 #define FLASH_CR1_HALT ((uint8_t)0x08) /*!< Standby in Halt mode mask */ 01545 #define FLASH_CR1_AHALT ((uint8_t)0x04) /*!< Standby in Active Halt mode mask */ 01546 #define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable mask */ 01547 #define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time mask */ 01548 01549 #define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Select option byte mask */ 01550 #define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word Programming mask */ 01551 #define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block mask */ 01552 #define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode mask */ 01553 #define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block mask */ 01554 01555 #define FLASH_NCR2_NOPT ((uint8_t)0x80) /*!< Select option byte mask */ 01556 #define FLASH_NCR2_NWPRG ((uint8_t)0x40) /*!< Word Programming mask */ 01557 #define FLASH_NCR2_NERASE ((uint8_t)0x20) /*!< Erase block mask */ 01558 #define FLASH_NCR2_NFPRG ((uint8_t)0x10) /*!< Fast programming mode mask */ 01559 #define FLASH_NCR2_NPRG ((uint8_t)0x01) /*!< Program block mask */ 01560 01561 #define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag mask */ 01562 #define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag mask */ 01563 #define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag mask */ 01564 #define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Flash Program memory unlocked flag mask */ 01565 #define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page mask */ 01566 01567 #define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */ 01568 01569 #define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */ 01570 01571 /** 01572 * @} 01573 */ 01574 01575 /*----------------------------------------------------------------------------*/ 01576 /** 01577 * @brief Option Bytes (OPT) 01578 */ 01579 typedef struct OPT_struct 01580 { 01581 __IO uint8_t OPT0; /*!< Option byte 0: Read-out protection (not accessible in IAP mode) */ 01582 __IO uint8_t OPT1; /*!< Option byte 1: User boot code */ 01583 __IO uint8_t NOPT1; /*!< Complementary Option byte 1 */ 01584 __IO uint8_t OPT2; /*!< Option byte 2: Alternate function remapping */ 01585 __IO uint8_t NOPT2; /*!< Complementary Option byte 2 */ 01586 __IO uint8_t OPT3; /*!< Option byte 3: Watchdog option */ 01587 __IO uint8_t NOPT3; /*!< Complementary Option byte 3 */ 01588 __IO uint8_t OPT4; /*!< Option byte 4: Clock option */ 01589 __IO uint8_t NOPT4; /*!< Complementary Option byte 4 */ 01590 __IO uint8_t OPT5; /*!< Option byte 5: HSE clock startup */ 01591 __IO uint8_t NOPT5; /*!< Complementary Option byte 5 */ 01592 uint8_t RESERVED1; /*!< Reserved Option byte*/ 01593 uint8_t RESERVED2; /*!< Reserved Option byte*/ 01594 __IO uint8_t OPT7; /*!< Option byte 7: flash wait states */ 01595 __IO uint8_t NOPT7; /*!< Complementary Option byte 7 */ 01596 } 01597 OPT_TypeDef; 01598 01599 /*----------------------------------------------------------------------------*/ 01600 /** 01601 * @brief Independent Watchdog (IWDG) 01602 */ 01603 01604 typedef struct IWDG_struct 01605 { 01606 __IO uint8_t KR; /*!< Key Register */ 01607 __IO uint8_t PR; /*!< Prescaler Register */ 01608 __IO uint8_t RLR; /*!< Reload Register */ 01609 } 01610 IWDG_TypeDef; 01611 01612 /** @addtogroup IWDG_Registers_Reset_Value 01613 * @{ 01614 */ 01615 01616 #define IWDG_PR_RESET_VALUE ((uint8_t)0x00) 01617 #define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF) 01618 01619 /** 01620 * @} 01621 */ 01622 01623 /*----------------------------------------------------------------------------*/ 01624 /** 01625 * @brief Window Watchdog (WWDG) 01626 */ 01627 01628 typedef struct WWDG_struct 01629 { 01630 __IO uint8_t CR; /*!< Control Register */ 01631 __IO uint8_t WR; /*!< Window Register */ 01632 } 01633 WWDG_TypeDef; 01634 01635 /** @addtogroup WWDG_Registers_Reset_Value 01636 * @{ 01637 */ 01638 01639 #define WWDG_CR_RESET_VALUE ((uint8_t)0x7F) 01640 #define WWDG_WR_RESET_VALUE ((uint8_t)0x7F) 01641 01642 /** 01643 * @} 01644 */ 01645 01646 /** @addtogroup WWDG_Registers_Bits_Definition 01647 * @{ 01648 */ 01649 01650 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */ 01651 #define WWDG_CR_T6 ((uint8_t)0x40) /*!< T6 bit mask */ 01652 #define WWDG_CR_T ((uint8_t)0x7F) /*!< T bits mask */ 01653 01654 #define WWDG_WR_MSB ((uint8_t)0x80) /*!< MSB bit mask */ 01655 #define WWDG_WR_W ((uint8_t)0x7F) /*!< W bits mask */ 01656 01657 /** 01658 * @} 01659 */ 01660 01661 /*----------------------------------------------------------------------------*/ 01662 /** 01663 * @brief Reset Controller (RST) 01664 */ 01665 01666 typedef struct RST_struct 01667 { 01668 __IO uint8_t SR; /*!< Reset status register */ 01669 } 01670 RST_TypeDef; 01671 01672 /** @addtogroup RST_Registers_Bits_Definition 01673 * @{ 01674 */ 01675 01676 #define RST_SR_EMCF ((uint8_t)0x10) /*!< EMC reset flag bit mask */ 01677 #define RST_SR_SWIMF ((uint8_t)0x08) /*!< SWIM reset flag bit mask */ 01678 #define RST_SR_ILLOPF ((uint8_t)0x04) /*!< Illegal opcode reset flag bit mask */ 01679 #define RST_SR_IWDGF ((uint8_t)0x02) /*!< IWDG reset flag bit mask */ 01680 #define RST_SR_WWDGF ((uint8_t)0x01) /*!< WWDG reset flag bit mask */ 01681 01682 /** 01683 * @} 01684 */ 01685 01686 /*----------------------------------------------------------------------------*/ 01687 /** 01688 * @brief Serial Peripheral Interface (SPI) 01689 */ 01690 01691 typedef struct SPI_struct 01692 { 01693 __IO uint8_t CR1; /*!< SPI control register 1 */ 01694 __IO uint8_t CR2; /*!< SPI control register 2 */ 01695 __IO uint8_t ICR; /*!< SPI interrupt control register */ 01696 __IO uint8_t SR; /*!< SPI status register */ 01697 __IO uint8_t DR; /*!< SPI data I/O register */ 01698 __IO uint8_t CRCPR; /*!< SPI CRC polynomial register */ 01699 __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */ 01700 __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */ 01701 } 01702 SPI_TypeDef; 01703 01704 /** @addtogroup SPI_Registers_Reset_Value 01705 * @{ 01706 */ 01707 01708 #define SPI_CR1_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 1 reset value */ 01709 #define SPI_CR2_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 2 reset value */ 01710 #define SPI_ICR_RESET_VALUE ((uint8_t)0x00) /*!< Interrupt Control Register reset value */ 01711 #define SPI_SR_RESET_VALUE ((uint8_t)0x02) /*!< Status Register reset value */ 01712 #define SPI_DR_RESET_VALUE ((uint8_t)0x00) /*!< Data Register reset value */ 01713 #define SPI_CRCPR_RESET_VALUE ((uint8_t)0x07) /*!< Polynomial Register reset value */ 01714 #define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */ 01715 #define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */ 01716 01717 /** 01718 * @} 01719 */ 01720 01721 /** @addtogroup SPI_Registers_Bits_Definition 01722 * @{ 01723 */ 01724 01725 #define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */ 01726 #define SPI_CR1_SPE ((uint8_t)0x40) /*!< Enable bits mask */ 01727 #define SPI_CR1_BR ((uint8_t)0x38) /*!< Baud rate control mask */ 01728 #define SPI_CR1_MSTR ((uint8_t)0x04) /*!< Master Selection mask */ 01729 #define SPI_CR1_CPOL ((uint8_t)0x02) /*!< Clock Polarity mask */ 01730 #define SPI_CR1_CPHA ((uint8_t)0x01) /*!< Clock Phase mask */ 01731 01732 #define SPI_CR2_BDM ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */ 01733 #define SPI_CR2_BDOE ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */ 01734 #define SPI_CR2_CRCEN ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */ 01735 #define SPI_CR2_CRCNEXT ((uint8_t)0x10) /*!< Transmit CRC next mask */ 01736 #define SPI_CR2_RXONLY ((uint8_t)0x04) /*!< Receive only mask */ 01737 #define SPI_CR2_SSM ((uint8_t)0x02) /*!< Software slave management mask */ 01738 #define SPI_CR2_SSI ((uint8_t)0x01) /*!< Internal slave select mask */ 01739 01740 #define SPI_ICR_TXEI ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */ 01741 #define SPI_ICR_RXEI ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */ 01742 #define SPI_ICR_ERRIE ((uint8_t)0x20) /*!< Error interrupt enable mask */ 01743 #define SPI_ICR_WKIE ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */ 01744 01745 #define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ 01746 #define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ 01747 #define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ 01748 #define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC error flag */ 01749 #define SPI_SR_WKUP ((uint8_t)0x08) /*!< Wake-Up flag */ 01750 #define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer empty */ 01751 #define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer not empty */ 01752 01753 /** 01754 * @} 01755 */ 01756 01757 /*----------------------------------------------------------------------------*/ 01758 /** 01759 * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART1) 01760 */ 01761 01762 typedef struct UART1_struct 01763 { 01764 __IO uint8_t SR; /*!< UART1 status register */ 01765 __IO uint8_t DR; /*!< UART1 data register */ 01766 __IO uint8_t BRR1; /*!< UART1 baud rate register */ 01767 __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */ 01768 __IO uint8_t CR1; /*!< UART1 control register 1 */ 01769 __IO uint8_t CR2; /*!< UART1 control register 2 */ 01770 __IO uint8_t CR3; /*!< UART1 control register 3 */ 01771 __IO uint8_t CR4; /*!< UART1 control register 4 */ 01772 __IO uint8_t CR5; /*!< UART1 control register 5 */ 01773 __IO uint8_t GTR; /*!< UART1 guard time register */ 01774 __IO uint8_t PSCR; /*!< UART1 prescaler register */ 01775 } 01776 UART1_TypeDef; 01777 01778 /** @addtogroup UART1_Registers_Reset_Value 01779 * @{ 01780 */ 01781 01782 #define UART1_SR_RESET_VALUE ((uint8_t)0xC0) 01783 #define UART1_BRR1_RESET_VALUE ((uint8_t)0x00) 01784 #define UART1_BRR2_RESET_VALUE ((uint8_t)0x00) 01785 #define UART1_CR1_RESET_VALUE ((uint8_t)0x00) 01786 #define UART1_CR2_RESET_VALUE ((uint8_t)0x00) 01787 #define UART1_CR3_RESET_VALUE ((uint8_t)0x00) 01788 #define UART1_CR4_RESET_VALUE ((uint8_t)0x00) 01789 #define UART1_CR5_RESET_VALUE ((uint8_t)0x00) 01790 #define UART1_GTR_RESET_VALUE ((uint8_t)0x00) 01791 #define UART1_PSCR_RESET_VALUE ((uint8_t)0x00) 01792 01793 /** 01794 * @} 01795 */ 01796 01797 /** @addtogroup UART1_Registers_Bits_Definition 01798 * @{ 01799 */ 01800 01801 #define UART1_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */ 01802 #define UART1_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */ 01803 #define UART1_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */ 01804 #define UART1_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */ 01805 #define UART1_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */ 01806 #define UART1_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */ 01807 #define UART1_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */ 01808 #define UART1_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */ 01809 01810 #define UART1_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask */ 01811 01812 #define UART1_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask */ 01813 #define UART1_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask */ 01814 01815 #define UART1_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */ 01816 #define UART1_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */ 01817 #define UART1_CR1_UARTD ((uint8_t)0x20) /*!< UART1 Disable (for low power consumption) */ 01818 #define UART1_CR1_M ((uint8_t)0x10) /*!< Word length mask */ 01819 #define UART1_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */ 01820 #define UART1_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */ 01821 #define UART1_CR1_PS ((uint8_t)0x02) /*!< UART1 Parity Selection */ 01822 #define UART1_CR1_PIEN ((uint8_t)0x01) /*!< UART1 Parity Interrupt Enable mask */ 01823 01824 #define UART1_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */ 01825 #define UART1_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */ 01826 #define UART1_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */ 01827 #define UART1_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */ 01828 #define UART1_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */ 01829 #define UART1_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */ 01830 #define UART1_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */ 01831 #define UART1_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */ 01832 01833 #define UART1_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */ 01834 #define UART1_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */ 01835 #define UART1_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */ 01836 #define UART1_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */ 01837 #define UART1_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */ 01838 #define UART1_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */ 01839 01840 #define UART1_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */ 01841 #define UART1_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */ 01842 #define UART1_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */ 01843 #define UART1_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART1 node mask */ 01844 01845 #define UART1_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */ 01846 #define UART1_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */ 01847 #define UART1_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */ 01848 #define UART1_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */ 01849 #define UART1_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */ 01850 01851 /** 01852 * @} 01853 */ 01854 01855 /*----------------------------------------------------------------------------*/ 01856 /** 01857 * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART2) 01858 */ 01859 01860 typedef struct UART2_struct 01861 { 01862 __IO uint8_t SR; /*!< UART1 status register */ 01863 __IO uint8_t DR; /*!< UART1 data register */ 01864 __IO uint8_t BRR1; /*!< UART1 baud rate register */ 01865 __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */ 01866 __IO uint8_t CR1; /*!< UART1 control register 1 */ 01867 __IO uint8_t CR2; /*!< UART1 control register 2 */ 01868 __IO uint8_t CR3; /*!< UART1 control register 3 */ 01869 __IO uint8_t CR4; /*!< UART1 control register 4 */ 01870 __IO uint8_t CR5; /*!< UART1 control register 5 */ 01871 __IO uint8_t CR6; /*!< UART1 control register 6 */ 01872 __IO uint8_t GTR; /*!< UART1 guard time register */ 01873 __IO uint8_t PSCR; /*!< UART1 prescaler register */ 01874 } 01875 UART2_TypeDef; 01876 01877 /** @addtogroup UART2_Registers_Reset_Value 01878 * @{ 01879 */ 01880 01881 #define UART2_SR_RESET_VALUE ((uint8_t)0xC0) 01882 #define UART2_BRR1_RESET_VALUE ((uint8_t)0x00) 01883 #define UART2_BRR2_RESET_VALUE ((uint8_t)0x00) 01884 #define UART2_CR1_RESET_VALUE ((uint8_t)0x00) 01885 #define UART2_CR2_RESET_VALUE ((uint8_t)0x00) 01886 #define UART2_CR3_RESET_VALUE ((uint8_t)0x00) 01887 #define UART2_CR4_RESET_VALUE ((uint8_t)0x00) 01888 #define UART2_CR5_RESET_VALUE ((uint8_t)0x00) 01889 #define UART2_CR6_RESET_VALUE ((uint8_t)0x00) 01890 #define UART2_GTR_RESET_VALUE ((uint8_t)0x00) 01891 #define UART2_PSCR_RESET_VALUE ((uint8_t)0x00) 01892 01893 /** 01894 * @} 01895 */ 01896 01897 /** @addtogroup UART2_Registers_Bits_Definition 01898 * @{ 01899 */ 01900 01901 #define UART2_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */ 01902 #define UART2_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */ 01903 #define UART2_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */ 01904 #define UART2_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */ 01905 #define UART2_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */ 01906 #define UART2_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */ 01907 #define UART2_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */ 01908 #define UART2_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */ 01909 01910 #define UART2_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask */ 01911 01912 #define UART2_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask */ 01913 #define UART2_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask */ 01914 01915 #define UART2_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */ 01916 #define UART2_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */ 01917 #define UART2_CR1_UARTD ((uint8_t)0x20) /*!< UART2 Disable (for low power consumption) */ 01918 #define UART2_CR1_M ((uint8_t)0x10) /*!< Word length mask */ 01919 #define UART2_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */ 01920 #define UART2_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */ 01921 #define UART2_CR1_PS ((uint8_t)0x02) /*!< UART2 Parity Selection */ 01922 #define UART2_CR1_PIEN ((uint8_t)0x01) /*!< UART2 Parity Interrupt Enable mask */ 01923 01924 #define UART2_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */ 01925 #define UART2_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */ 01926 #define UART2_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */ 01927 #define UART2_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */ 01928 #define UART2_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */ 01929 #define UART2_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */ 01930 #define UART2_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */ 01931 #define UART2_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */ 01932 01933 #define UART2_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */ 01934 #define UART2_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */ 01935 #define UART2_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */ 01936 #define UART2_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */ 01937 #define UART2_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */ 01938 #define UART2_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */ 01939 01940 #define UART2_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */ 01941 #define UART2_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */ 01942 #define UART2_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */ 01943 #define UART2_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART2 node mask */ 01944 01945 #define UART2_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */ 01946 #define UART2_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */ 01947 #define UART2_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */ 01948 #define UART2_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */ 01949 01950 #define UART2_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */ 01951 #define UART2_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */ 01952 #define UART2_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */ 01953 #define UART2_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */ 01954 #define UART2_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */ 01955 #define UART2_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */ 01956 01957 /** 01958 * @} 01959 */ 01960 01961 01962 /*----------------------------------------------------------------------------*/ 01963 /** 01964 * @brief LIN Universal Asynchronous Receiver Transmitter (UART3) 01965 */ 01966 01967 typedef struct UART3_struct 01968 { 01969 __IO uint8_t SR; /*!< status register */ 01970 __IO uint8_t DR; /*!< data register */ 01971 __IO uint8_t BRR1; /*!< baud rate register */ 01972 __IO uint8_t BRR2; /*!< DIV mantissa[11:8] SCIDIV fraction */ 01973 __IO uint8_t CR1; /*!< control register 1 */ 01974 __IO uint8_t CR2; /*!< control register 2 */ 01975 __IO uint8_t CR3; /*!< control register 3 */ 01976 __IO uint8_t CR4; /*!< control register 4 */ 01977 uint8_t RESERVED; /*!< Reserved byte */ 01978 __IO uint8_t CR6; /*!< control register 5 */ 01979 } 01980 UART3_TypeDef; 01981 01982 /** @addtogroup UART3_Registers_Reset_Value 01983 * @{ 01984 */ 01985 01986 #define UART3_SR_RESET_VALUE ((uint8_t)0xC0) 01987 #define UART3_BRR1_RESET_VALUE ((uint8_t)0x00) 01988 #define UART3_BRR2_RESET_VALUE ((uint8_t)0x00) 01989 #define UART3_CR1_RESET_VALUE ((uint8_t)0x00) 01990 #define UART3_CR2_RESET_VALUE ((uint8_t)0x00) 01991 #define UART3_CR3_RESET_VALUE ((uint8_t)0x00) 01992 #define UART3_CR4_RESET_VALUE ((uint8_t)0x00) 01993 #define UART3_CR6_RESET_VALUE ((uint8_t)0x00) 01994 01995 /** 01996 * @} 01997 */ 01998 01999 /** @addtogroup UART3_Registers_Bits_Definition 02000 * @{ 02001 */ 02002 02003 #define UART3_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */ 02004 #define UART3_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */ 02005 #define UART3_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */ 02006 #define UART3_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */ 02007 #define UART3_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */ 02008 #define UART3_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */ 02009 #define UART3_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */ 02010 #define UART3_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */ 02011 02012 #define UART3_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask */ 02013 02014 #define UART3_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask */ 02015 #define UART3_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask */ 02016 02017 #define UART3_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */ 02018 #define UART3_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */ 02019 #define UART3_CR1_UARTD ((uint8_t)0x20) /*!< UART Disable (for low power consumption) */ 02020 #define UART3_CR1_M ((uint8_t)0x10) /*!< Word length mask */ 02021 #define UART3_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */ 02022 #define UART3_CR1_PCEN ((uint8_t)0x04) /*!< Parity control enable mask */ 02023 #define UART3_CR1_PS ((uint8_t)0x02) /*!< Parity selection bit mask */ 02024 #define UART3_CR1_PIEN ((uint8_t)0x01) /*!< Parity interrupt enable bit mask */ 02025 02026 #define UART3_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */ 02027 #define UART3_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */ 02028 #define UART3_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */ 02029 #define UART3_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */ 02030 #define UART3_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */ 02031 #define UART3_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */ 02032 #define UART3_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */ 02033 #define UART3_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */ 02034 02035 #define UART3_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */ 02036 #define UART3_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */ 02037 02038 #define UART3_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */ 02039 #define UART3_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */ 02040 #define UART3_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */ 02041 #define UART3_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART3 node mask */ 02042 02043 #define UART3_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */ 02044 #define UART3_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */ 02045 #define UART3_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */ 02046 #define UART3_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */ 02047 #define UART3_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */ 02048 #define UART3_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */ 02049 02050 /** 02051 * @} 02052 */ 02053 02054 /*----------------------------------------------------------------------------*/ 02055 /** 02056 * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART4) 02057 */ 02058 #if defined(STM8AF622x) 02059 typedef struct UART4_struct 02060 { 02061 __IO uint8_t SR; /*!< UART4 status register */ 02062 __IO uint8_t DR; /*!< UART4 data register */ 02063 __IO uint8_t BRR1; /*!< UART4 baud rate register */ 02064 __IO uint8_t BRR2; /*!< UART4 DIV mantissa[11:8] SCIDIV fraction */ 02065 __IO uint8_t CR1; /*!< UART4 control register 1 */ 02066 __IO uint8_t CR2; /*!< UART4 control register 2 */ 02067 __IO uint8_t CR3; /*!< UART4 control register 3 */ 02068 __IO uint8_t CR4; /*!< UART4 control register 4 */ 02069 __IO uint8_t CR5; /*!< UART4 control register 5 */ 02070 __IO uint8_t CR6; /*!< UART4 control register 6 */ 02071 __IO uint8_t GTR; /*!< UART4 guard time register */ 02072 __IO uint8_t PSCR; /*!< UART4 prescaler register */ 02073 } 02074 UART4_TypeDef; 02075 02076 /** @addtogroup UART4_Registers_Reset_Value 02077 * @{ 02078 */ 02079 02080 #define UART4_SR_RESET_VALUE ((uint8_t)0xC0) 02081 #define UART4_BRR1_RESET_VALUE ((uint8_t)0x00) 02082 #define UART4_BRR2_RESET_VALUE ((uint8_t)0x00) 02083 #define UART4_CR1_RESET_VALUE ((uint8_t)0x00) 02084 #define UART4_CR2_RESET_VALUE ((uint8_t)0x00) 02085 #define UART4_CR3_RESET_VALUE ((uint8_t)0x00) 02086 #define UART4_CR4_RESET_VALUE ((uint8_t)0x00) 02087 #define UART4_CR5_RESET_VALUE ((uint8_t)0x00) 02088 #define UART4_CR6_RESET_VALUE ((uint8_t)0x00) 02089 #define UART4_GTR_RESET_VALUE ((uint8_t)0x00) 02090 #define UART4_PSCR_RESET_VALUE ((uint8_t)0x00) 02091 02092 /** 02093 * @} 02094 */ 02095 02096 /** @addtogroup UART4_Registers_Bits_Definition 02097 * @{ 02098 */ 02099 02100 #define UART4_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */ 02101 #define UART4_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */ 02102 #define UART4_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */ 02103 #define UART4_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */ 02104 #define UART4_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */ 02105 #define UART4_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */ 02106 #define UART4_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */ 02107 #define UART4_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */ 02108 02109 #define UART4_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART4DIV [7:0] mask */ 02110 02111 #define UART4_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART4DIV [11:8] mask */ 02112 #define UART4_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART4DIV [3:0] mask */ 02113 02114 #define UART4_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */ 02115 #define UART4_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */ 02116 #define UART4_CR1_UARTD ((uint8_t)0x20) /*!< UART4 Disable (for low power consumption) */ 02117 #define UART4_CR1_M ((uint8_t)0x10) /*!< Word length mask */ 02118 #define UART4_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */ 02119 #define UART4_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */ 02120 #define UART4_CR1_PS ((uint8_t)0x02) /*!< UART4 Parity Selection */ 02121 #define UART4_CR1_PIEN ((uint8_t)0x01) /*!< UART4 Parity Interrupt Enable mask */ 02122 02123 #define UART4_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */ 02124 #define UART4_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */ 02125 #define UART4_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */ 02126 #define UART4_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */ 02127 #define UART4_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */ 02128 #define UART4_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */ 02129 #define UART4_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */ 02130 #define UART4_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */ 02131 02132 #define UART4_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */ 02133 #define UART4_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */ 02134 #define UART4_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */ 02135 #define UART4_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */ 02136 #define UART4_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */ 02137 #define UART4_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */ 02138 02139 #define UART4_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */ 02140 #define UART4_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */ 02141 #define UART4_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */ 02142 #define UART4_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART4 node mask */ 02143 02144 #define UART4_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */ 02145 #define UART4_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */ 02146 #define UART4_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */ 02147 #define UART4_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */ 02148 #define UART4_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */ 02149 02150 #define UART4_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */ 02151 #define UART4_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */ 02152 #define UART4_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */ 02153 #define UART4_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */ 02154 #define UART4_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */ 02155 #define UART4_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */ 02156 #endif /* STM8AF622x */ 02157 02158 /** 02159 * @} 02160 */ 02161 02162 /*----------------------------------------------------------------------------*/ 02163 02164 /*----------------------------------------------------------------------------*/ 02165 /** 02166 * @brief Controller Area Network (CAN) 02167 */ 02168 02169 typedef struct 02170 { 02171 __IO uint8_t MCR; /*!< CAN master control register */ 02172 __IO uint8_t MSR; /*!< CAN master status register */ 02173 __IO uint8_t TSR; /*!< CAN transmit status register */ 02174 __IO uint8_t TPR; /*!< CAN transmit priority register */ 02175 __IO uint8_t RFR; /*!< CAN receive FIFO register */ 02176 __IO uint8_t IER; /*!< CAN interrupt enable register */ 02177 __IO uint8_t DGR; /*!< CAN diagnosis register */ 02178 __IO uint8_t PSR; /*!< CAN page selection register */ 02179 02180 union 02181 { 02182 struct 02183 { 02184 __IO uint8_t MCSR; 02185 __IO uint8_t MDLCR; 02186 __IO uint8_t MIDR1; 02187 __IO uint8_t MIDR2; 02188 __IO uint8_t MIDR3; 02189 __IO uint8_t MIDR4; 02190 __IO uint8_t MDAR1; 02191 __IO uint8_t MDAR2; 02192 __IO uint8_t MDAR3; 02193 __IO uint8_t MDAR4; 02194 __IO uint8_t MDAR5; 02195 __IO uint8_t MDAR6; 02196 __IO uint8_t MDAR7; 02197 __IO uint8_t MDAR8; 02198 __IO uint8_t MTSRL; 02199 __IO uint8_t MTSRH; 02200 }TxMailbox; 02201 02202 struct 02203 { 02204 __IO uint8_t FR01; 02205 __IO uint8_t FR02; 02206 __IO uint8_t FR03; 02207 __IO uint8_t FR04; 02208 __IO uint8_t FR05; 02209 __IO uint8_t FR06; 02210 __IO uint8_t FR07; 02211 __IO uint8_t FR08; 02212 02213 __IO uint8_t FR09; 02214 __IO uint8_t FR10; 02215 __IO uint8_t FR11; 02216 __IO uint8_t FR12; 02217 __IO uint8_t FR13; 02218 __IO uint8_t FR14; 02219 __IO uint8_t FR15; 02220 __IO uint8_t FR16; 02221 }Filter; 02222 02223 struct 02224 { 02225 __IO uint8_t F0R1; 02226 __IO uint8_t F0R2; 02227 __IO uint8_t F0R3; 02228 __IO uint8_t F0R4; 02229 __IO uint8_t F0R5; 02230 __IO uint8_t F0R6; 02231 __IO uint8_t F0R7; 02232 __IO uint8_t F0R8; 02233 02234 __IO uint8_t F1R1; 02235 __IO uint8_t F1R2; 02236 __IO uint8_t F1R3; 02237 __IO uint8_t F1R4; 02238 __IO uint8_t F1R5; 02239 __IO uint8_t F1R6; 02240 __IO uint8_t F1R7; 02241 __IO uint8_t F1R8; 02242 }Filter01; 02243 02244 struct 02245 { 02246 __IO uint8_t F2R1; 02247 __IO uint8_t F2R2; 02248 __IO uint8_t F2R3; 02249 __IO uint8_t F2R4; 02250 __IO uint8_t F2R5; 02251 __IO uint8_t F2R6; 02252 __IO uint8_t F2R7; 02253 __IO uint8_t F2R8; 02254 02255 __IO uint8_t F3R1; 02256 __IO uint8_t F3R2; 02257 __IO uint8_t F3R3; 02258 __IO uint8_t F3R4; 02259 __IO uint8_t F3R5; 02260 __IO uint8_t F3R6; 02261 __IO uint8_t F3R7; 02262 __IO uint8_t F3R8; 02263 }Filter23; 02264 02265 struct 02266 { 02267 __IO uint8_t F4R1; 02268 __IO uint8_t F4R2; 02269 __IO uint8_t F4R3; 02270 __IO uint8_t F4R4; 02271 __IO uint8_t F4R5; 02272 __IO uint8_t F4R6; 02273 __IO uint8_t F4R7; 02274 __IO uint8_t F4R8; 02275 02276 __IO uint8_t F5R1; 02277 __IO uint8_t F5R2; 02278 __IO uint8_t F5R3; 02279 __IO uint8_t F5R4; 02280 __IO uint8_t F5R5; 02281 __IO uint8_t F5R6; 02282 __IO uint8_t F5R7; 02283 __IO uint8_t F5R8; 02284 } Filter45; 02285 02286 struct 02287 { 02288 __IO uint8_t ESR; 02289 __IO uint8_t EIER; 02290 __IO uint8_t TECR; 02291 __IO uint8_t RECR; 02292 __IO uint8_t BTR1; 02293 __IO uint8_t BTR2; 02294 uint8_t Reserved1[2]; 02295 __IO uint8_t FMR1; 02296 __IO uint8_t FMR2; 02297 __IO uint8_t FCR1; 02298 __IO uint8_t FCR2; 02299 __IO uint8_t FCR3; 02300 uint8_t Reserved2[3]; 02301 }Config; 02302 02303 struct 02304 { 02305 __IO uint8_t MFMI; 02306 __IO uint8_t MDLCR; 02307 __IO uint8_t MIDR1; 02308 __IO uint8_t MIDR2; 02309 __IO uint8_t MIDR3; 02310 __IO uint8_t MIDR4; 02311 __IO uint8_t MDAR1; 02312 __IO uint8_t MDAR2; 02313 __IO uint8_t MDAR3; 02314 __IO uint8_t MDAR4; 02315 __IO uint8_t MDAR5; 02316 __IO uint8_t MDAR6; 02317 __IO uint8_t MDAR7; 02318 __IO uint8_t MDAR8; 02319 __IO uint8_t MTSRL; 02320 __IO uint8_t MTSRH; 02321 }RxFIFO; 02322 }Page; 02323 } CAN_TypeDef; 02324 02325 /** @addtogroup CAN_Registers_Bits_Definition 02326 * @{ 02327 */ 02328 /******************************* Common ***************************************/ 02329 /* CAN Master Control Register bits */ 02330 #define CAN_MCR_INRQ ((uint8_t)0x01) 02331 #define CAN_MCR_SLEEP ((uint8_t)0x02) 02332 #define CAN_MCR_TXFP ((uint8_t)0x04) 02333 #define CAN_MCR_RFLM ((uint8_t)0x08) 02334 #define CAN_MCR_NART ((uint8_t)0x10) 02335 #define CAN_MCR_AWUM ((uint8_t)0x20) 02336 #define CAN_MCR_ABOM ((uint8_t)0x40) 02337 #define CAN_MCR_TTCM ((uint8_t)0x80) 02338 02339 /* CAN Master Status Register bits */ 02340 #define CAN_MSR_INAK ((uint8_t)0x01) 02341 #define CAN_MSR_SLAK ((uint8_t)0x02) 02342 #define CAN_MSR_ERRI ((uint8_t)0x04) 02343 #define CAN_MSR_WKUI ((uint8_t)0x08) 02344 #define CAN_MSR_TX ((uint8_t)0x10) 02345 #define CAN_MSR_RX ((uint8_t)0x20) 02346 02347 /* CAN Transmit Status Register bits */ 02348 #define CAN_TSR_RQCP0 ((uint8_t)0x01) 02349 #define CAN_TSR_RQCP1 ((uint8_t)0x02) 02350 #define CAN_TSR_RQCP2 ((uint8_t)0x04) 02351 #define CAN_TSR_RQCP012 ((uint8_t)0x07) 02352 #define CAN_TSR_TXOK0 ((uint8_t)0x10) 02353 #define CAN_TSR_TXOK1 ((uint8_t)0x20) 02354 #define CAN_TSR_TXOK2 ((uint8_t)0x40) 02355 02356 #define CAN_TPR_CODE0 ((uint8_t)0x01) 02357 #define CAN_TPR_TME0 ((uint8_t)0x04) 02358 #define CAN_TPR_TME1 ((uint8_t)0x08) 02359 #define CAN_TPR_TME2 ((uint8_t)0x10) 02360 #define CAN_TPR_LOW0 ((uint8_t)0x20) 02361 #define CAN_TPR_LOW1 ((uint8_t)0x40) 02362 #define CAN_TPR_LOW2 ((uint8_t)0x80) 02363 /* CAN Receive FIFO Register bits */ 02364 #define CAN_RFR_FMP01 ((uint8_t)0x03) 02365 #define CAN_RFR_FULL ((uint8_t)0x08) 02366 #define CAN_RFR_FOVR ((uint8_t)0x10) 02367 #define CAN_RFR_RFOM ((uint8_t)0x20) 02368 02369 /* CAN Interrupt Register bits */ 02370 #define CAN_IER_TMEIE ((uint8_t)0x01) 02371 #define CAN_IER_FMPIE ((uint8_t)0x02) 02372 #define CAN_IER_FFIE ((uint8_t)0x04) 02373 #define CAN_IER_FOVIE ((uint8_t)0x08) 02374 #define CAN_IER_WKUIE ((uint8_t)0x80) 02375 02376 02377 /* CAN diagnostic Register bits */ 02378 #define CAN_DGR_LBKM ((uint8_t)0x01) 02379 #define CAN_DGR_SLIM ((uint8_t)0x02) 02380 #define CAN_DGR_SAMP ((uint8_t)0x04) 02381 #define CAN_DGR_RX ((uint8_t)0x08) 02382 #define CAN_DGR_TXM2E ((uint8_t)0x10) 02383 02384 02385 /* CAN page select Register bits */ 02386 #define CAN_PSR_PS0 ((uint8_t)0x01) 02387 #define CAN_PSR_PS1 ((uint8_t)0x02) 02388 #define CAN_PSR_PS2 ((uint8_t)0x04) 02389 02390 /******************** Tx MailBox & Fifo Page common bits **********************/ 02391 #define CAN_MCSR_TXRQ ((uint8_t)0x01) 02392 #define CAN_MCSR_ABRQ ((uint8_t)0x02) 02393 #define CAN_MCSR_RQCP ((uint8_t)0x04) 02394 #define CAN_MCSR_TXOK ((uint8_t)0x08) 02395 #define CAN_MCSR_ALST ((uint8_t)0x10) 02396 #define CAN_MCSR_TERR ((uint8_t)0x20) 02397 02398 #define CAN_MDLCR_DLC ((uint8_t)0x0F) 02399 #define CAN_MDLCR_TGT ((uint8_t)0x80) 02400 02401 #define CAN_MIDR1_RTR ((uint8_t)0x20) 02402 #define CAN_MIDR1_IDE ((uint8_t)0x40) 02403 02404 02405 /************************* Filter Page ****************************************/ 02406 02407 /* CAN Error Status Register bits */ 02408 #define CAN_ESR_EWGF ((uint8_t)0x01) 02409 #define CAN_ESR_EPVF ((uint8_t)0x02) 02410 #define CAN_ESR_BOFF ((uint8_t)0x04) 02411 #define CAN_ESR_LEC0 ((uint8_t)0x10) 02412 #define CAN_ESR_LEC1 ((uint8_t)0x20) 02413 #define CAN_ESR_LEC2 ((uint8_t)0x40) 02414 #define CAN_ESR_LEC ((uint8_t)0x70) 02415 02416 /* CAN Error Status Register bits */ 02417 #define CAN_EIER_EWGIE ((uint8_t)0x01) 02418 #define CAN_EIER_EPVIE ((uint8_t)0x02) 02419 #define CAN_EIER_BOFIE ((uint8_t)0x04) 02420 #define CAN_EIER_LECIE ((uint8_t)0x10) 02421 #define CAN_EIER_ERRIE ((uint8_t)0x80) 02422 02423 /* CAN transmit error counter Register bits(CAN_TECR) */ 02424 #define CAN_TECR_TEC0 ((uint8_t)0x01) 02425 #define CAN_TECR_TEC1 ((uint8_t)0x02) 02426 #define CAN_TECR_TEC2 ((uint8_t)0x04) 02427 #define CAN_TECR_TEC3 ((uint8_t)0x08) 02428 #define CAN_TECR_TEC4 ((uint8_t)0x10) 02429 #define CAN_TECR_TEC5 ((uint8_t)0x20) 02430 #define CAN_TECR_TEC6 ((uint8_t)0x40) 02431 #define CAN_TECR_TEC7 ((uint8_t)0x80) 02432 02433 /* CAN RECEIVE error counter Register bits(CAN_TECR) */ 02434 #define CAN_RECR_REC0 ((uint8_t)0x01) 02435 #define CAN_RECR_REC1 ((uint8_t)0x02) 02436 #define CAN_RECR_REC2 ((uint8_t)0x04) 02437 #define CAN_RECR_REC3 ((uint8_t)0x08) 02438 #define CAN_RECR_REC4 ((uint8_t)0x10) 02439 #define CAN_RECR_REC5 ((uint8_t)0x20) 02440 #define CAN_RECR_REC6 ((uint8_t)0x40) 02441 #define CAN_RECR_REC7 ((uint8_t)0x80) 02442 02443 /* CAN filter mode register bits (CAN_FMR) */ 02444 #define CAN_FMR1_FML0 ((uint8_t)0x01) 02445 #define CAN_FMR1_FMH0 ((uint8_t)0x02) 02446 #define CAN_FMR1_FML1 ((uint8_t)0x04) 02447 #define CAN_FMR1_FMH1 ((uint8_t)0x08) 02448 #define CAN_FMR1_FML2 ((uint8_t)0x10) 02449 #define CAN_FMR1_FMH2 ((uint8_t)0x20) 02450 #define CAN_FMR1_FML3 ((uint8_t)0x40) 02451 #define CAN_FMR1_FMH3 ((uint8_t)0x80) 02452 02453 #define CAN_FMR2_FML4 ((uint8_t)0x01) 02454 #define CAN_FMR2_FMH4 ((uint8_t)0x02) 02455 #define CAN_FMR2_FML5 ((uint8_t)0x04) 02456 #define CAN_FMR2_FMH5 ((uint8_t)0x08) 02457 02458 /* CAN filter Config register bits (CAN_FCR) */ 02459 #define CAN_FCR1_FACT0 ((uint8_t)0x01) 02460 #define CAN_FCR1_FACT1 ((uint8_t)0x10) 02461 #define CAN_FCR2_FACT2 ((uint8_t)0x01) 02462 #define CAN_FCR2_FACT3 ((uint8_t)0x10) 02463 #define CAN_FCR3_FACT4 ((uint8_t)0x01) 02464 #define CAN_FCR3_FACT5 ((uint8_t)0x10) 02465 02466 #define CAN_FCR1_FSC00 ((uint8_t)0x02) 02467 #define CAN_FCR1_FSC01 ((uint8_t)0x04) 02468 #define CAN_FCR1_FSC10 ((uint8_t)0x20) 02469 #define CAN_FCR1_FSC11 ((uint8_t)0x40) 02470 #define CAN_FCR2_FSC20 ((uint8_t)0x02) 02471 #define CAN_FCR2_FSC21 ((uint8_t)0x04) 02472 #define CAN_FCR2_FSC30 ((uint8_t)0x20) 02473 #define CAN_FCR2_FSC31 ((uint8_t)0x40) 02474 #define CAN_FCR3_FSC40 ((uint8_t)0x02) 02475 #define CAN_FCR3_FSC41 ((uint8_t)0x04) 02476 #define CAN_FCR3_FSC50 ((uint8_t)0x20) 02477 #define CAN_FCR3_FSC51 ((uint8_t)0x40) 02478 02479 /** 02480 * @} 02481 */ 02482 02483 /** @addtogroup CAN_Registers_Reset_Value 02484 * @{ 02485 */ 02486 #define CAN_MCR_RESET_VALUE ((uint8_t)0x02) 02487 #define CAN_MSR_RESET_VALUE ((uint8_t)0x02) 02488 #define CAN_TSR_RESET_VALUE ((uint8_t)0x00) 02489 #define CAN_TPR_RESET_VALUE ((uint8_t)0x0C) 02490 #define CAN_RFR_RESET_VALUE ((uint8_t)0x00) 02491 #define CAN_IER_RESET_VALUE ((uint8_t)0x00) 02492 #define CAN_DGR_RESET_VALUE ((uint8_t)0x0C) 02493 #define CAN_PSR_RESET_VALUE ((uint8_t)0x00) 02494 02495 #define CAN_ESR_RESET_VALUE ((uint8_t)0x00) 02496 #define CAN_EIER_RESET_VALUE ((uint8_t)0x00) 02497 #define CAN_TECR_RESET_VALUE ((uint8_t)0x00) 02498 #define CAN_RECR_RESET_VALUE ((uint8_t)0x00) 02499 #define CAN_BTR1_RESET_VALUE ((uint8_t)0x40) 02500 #define CAN_BTR2_RESET_VALUE ((uint8_t)0x23) 02501 #define CAN_FMR1_RESET_VALUE ((uint8_t)0x00) 02502 #define CAN_FMR2_RESET_VALUE ((uint8_t)0x00) 02503 #define CAN_FCR_RESET_VALUE ((uint8_t)0x00) 02504 02505 #define CAN_MFMI_RESET_VALUE ((uint8_t)0x00) 02506 #define CAN_MDLC_RESET_VALUE ((uint8_t)0x00) 02507 #define CAN_MCSR_RESET_VALUE ((uint8_t)0x00) 02508 02509 /** 02510 * @} 02511 */ 02512 02513 /** 02514 * @brief Configuration Registers (CFG) 02515 */ 02516 02517 typedef struct CFG_struct 02518 { 02519 __IO uint8_t GCR; /*!< Global Configuration register */ 02520 } 02521 CFG_TypeDef; 02522 02523 /** @addtogroup CFG_Registers_Reset_Value 02524 * @{ 02525 */ 02526 02527 #define CFG_GCR_RESET_VALUE ((uint8_t)0x00) 02528 02529 /** 02530 * @} 02531 */ 02532 02533 /** @addtogroup CFG_Registers_Bits_Definition 02534 * @{ 02535 */ 02536 02537 #define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */ 02538 #define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */ 02539 02540 /** 02541 * @} 02542 */ 02543 02544 /** 02545 * @} 02546 */ 02547 02548 /******************************************************************************/ 02549 /* Peripherals Base Address */ 02550 /******************************************************************************/ 02551 02552 /** @addtogroup MAP_FILE_Base_Addresses 02553 * @{ 02554 */ 02555 #define OPT_BaseAddress 0x4800 02556 #define GPIOA_BaseAddress 0x5000 02557 #define GPIOB_BaseAddress 0x5005 02558 #define GPIOC_BaseAddress 0x500A 02559 #define GPIOD_BaseAddress 0x500F 02560 #define GPIOE_BaseAddress 0x5014 02561 #define GPIOF_BaseAddress 0x5019 02562 #define GPIOG_BaseAddress 0x501E 02563 #define GPIOH_BaseAddress 0x5023 02564 #define GPIOI_BaseAddress 0x5028 02565 #define FLASH_BaseAddress 0x505A 02566 #define EXTI_BaseAddress 0x50A0 02567 #define RST_BaseAddress 0x50B3 02568 #define CLK_BaseAddress 0x50C0 02569 #define WWDG_BaseAddress 0x50D1 02570 #define IWDG_BaseAddress 0x50E0 02571 #define AWU_BaseAddress 0x50F0 02572 #define BEEP_BaseAddress 0x50F3 02573 #define SPI_BaseAddress 0x5200 02574 #define I2C_BaseAddress 0x5210 02575 #define UART1_BaseAddress 0x5230 02576 #define UART2_BaseAddress 0x5240 02577 #define UART3_BaseAddress 0x5240 02578 #define UART4_BaseAddress 0x5230 02579 #define TIM1_BaseAddress 0x5250 02580 #define TIM2_BaseAddress 0x5300 02581 #define TIM3_BaseAddress 0x5320 02582 #define TIM4_BaseAddress 0x5340 02583 #define TIM5_BaseAddress 0x5300 02584 #define TIM6_BaseAddress 0x5340 02585 #define ADC1_BaseAddress 0x53E0 02586 #define ADC2_BaseAddress 0x5400 02587 #define CAN_BaseAddress 0x5420 02588 #define CFG_BaseAddress 0x7F60 02589 #define ITC_BaseAddress 0x7F70 02590 #define DM_BaseAddress 0x7F90 02591 02592 /** 02593 * @} 02594 */ 02595 02596 /******************************************************************************/ 02597 /* Peripherals declarations */ 02598 /******************************************************************************/ 02599 02600 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \ 02601 defined(STM8S903) || defined(STM8AF626x) || defined(STM8AF622x) 02602 #define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress) 02603 #endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S903) || (STM8AF626x) || (STM8AF622x)*/ 02604 02605 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \ 02606 defined (STM8AF62Ax) 02607 #define ADC2 ((ADC2_TypeDef *) ADC2_BaseAddress) 02608 #endif /* (STM8S208) ||(STM8S207) || (STM8S007) || (STM8AF52Ax) || (STM8AF62Ax) */ 02609 02610 #define AWU ((AWU_TypeDef *) AWU_BaseAddress) 02611 02612 #define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress) 02613 02614 #if defined (STM8S208) || defined (STM8AF52Ax) 02615 #define CAN ((CAN_TypeDef *) CAN_BaseAddress) 02616 #endif /* (STM8S208) || (STM8AF52Ax) */ 02617 02618 #define CLK ((CLK_TypeDef *) CLK_BaseAddress) 02619 02620 #define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress) 02621 02622 #define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress) 02623 02624 #define OPT ((OPT_TypeDef *) OPT_BaseAddress) 02625 02626 #define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress) 02627 02628 #define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress) 02629 02630 #define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress) 02631 02632 #define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress) 02633 02634 #define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress) 02635 02636 #define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress) 02637 02638 #if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined(STM8S105) || \ 02639 defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x) 02640 #define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress) 02641 #endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x) */ 02642 02643 #if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || \ 02644 defined (STM8AF62Ax) 02645 #define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress) 02646 #define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress) 02647 #endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */ 02648 02649 #define RST ((RST_TypeDef *) RST_BaseAddress) 02650 02651 #define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress) 02652 #define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress) 02653 02654 #define SPI ((SPI_TypeDef *) SPI_BaseAddress) 02655 #define I2C ((I2C_TypeDef *) I2C_BaseAddress) 02656 02657 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \ 02658 defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax) 02659 #define UART1 ((UART1_TypeDef *) UART1_BaseAddress) 02660 #endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S903) || (STM8AF52Ax) || (STM8AF62Ax) */ 02661 02662 #if defined (STM8S105) || defined (STM8S005) || defined (STM8AF626x) 02663 #define UART2 ((UART2_TypeDef *) UART2_BaseAddress) 02664 #endif /* STM8S105 || STM8S005 || STM8AF626x */ 02665 02666 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \ 02667 defined (STM8AF62Ax) 02668 #define UART3 ((UART3_TypeDef *) UART3_BaseAddress) 02669 #endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */ 02670 02671 #if defined(STM8AF622x) 02672 #define UART4 ((UART4_TypeDef *) UART4_BaseAddress) 02673 #endif /* (STM8AF622x) */ 02674 02675 #define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress) 02676 02677 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \ 02678 defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \ 02679 defined (STM8AF62Ax) || defined (STM8AF626x) 02680 #define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress) 02681 #endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/ 02682 02683 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S105) || \ 02684 defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x) 02685 #define TIM3 ((TIM3_TypeDef *) TIM3_BaseAddress) 02686 #endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF62Ax) || (STM8AF52Ax) || (STM8AF626x)*/ 02687 02688 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \ 02689 defined(STM8S003) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \ 02690 defined (STM8AF62Ax) || defined (STM8AF626x) 02691 #define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress) 02692 #endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/ 02693 02694 #if defined (STM8S903) || defined (STM8AF622x) 02695 #define TIM5 ((TIM5_TypeDef *) TIM5_BaseAddress) 02696 #define TIM6 ((TIM6_TypeDef *) TIM6_BaseAddress) 02697 #endif /* (STM8S903) || (STM8AF622x) */ 02698 02699 #define ITC ((ITC_TypeDef *) ITC_BaseAddress) 02700 02701 #define CFG ((CFG_TypeDef *) CFG_BaseAddress) 02702 02703 #define DM ((DM_TypeDef *) DM_BaseAddress) 02704 02705 02706 #ifdef USE_STDPERIPH_DRIVER 02707 #include "stm8s_conf.h" 02708 #endif 02709 02710 /* Exported macro --------------------------------------------------------------*/ 02711 02712 /*============================== Interrupts ====================================*/ 02713 #ifdef _RAISONANCE_ 02714 #include <intrins.h> 02715 #define enableInterrupts() _rim_() /* enable interrupts */ 02716 #define disableInterrupts() _sim_() /* disable interrupts */ 02717 #define rim() _rim_() /* enable interrupts */ 02718 #define sim() _sim_() /* disable interrupts */ 02719 #define nop() _nop_() /* No Operation */ 02720 #define trap() _trap_() /* Trap (soft IT) */ 02721 #define wfi() _wfi_() /* Wait For Interrupt */ 02722 #define halt() _halt_() /* Halt */ 02723 #elif defined(_COSMIC_) 02724 #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */ 02725 #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */ 02726 #define rim() {_asm("rim\n");} /* enable interrupts */ 02727 #define sim() {_asm("sim\n");} /* disable interrupts */ 02728 #define nop() {_asm("nop\n");} /* No Operation */ 02729 #define trap() {_asm("trap\n");} /* Trap (soft IT) */ 02730 #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */ 02731 #define halt() {_asm("halt\n");} /* Halt */ 02732 #else /*_IAR_*/ 02733 #include <intrinsics.h> 02734 #define enableInterrupts() __enable_interrupt() /* enable interrupts */ 02735 #define disableInterrupts() __disable_interrupt() /* disable interrupts */ 02736 #define rim() __enable_interrupt() /* enable interrupts */ 02737 #define sim() __disable_interrupt() /* disable interrupts */ 02738 #define nop() __no_operation() /* No Operation */ 02739 #define trap() __trap() /* Trap (soft IT) */ 02740 #define wfi() __wait_for_interrupt() /* Wait For Interrupt */ 02741 #define halt() __halt() /* Halt */ 02742 #endif /*_RAISONANCE_*/ 02743 02744 /*============================== Interrupt vector Handling ========================*/ 02745 02746 #ifdef _COSMIC_ 02747 #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void) 02748 #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void) 02749 #endif /* _COSMIC_ */ 02750 02751 #ifdef _RAISONANCE_ 02752 #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b 02753 #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap 02754 #endif /* _RAISONANCE_ */ 02755 02756 #ifdef _IAR_ 02757 #define STRINGVECTOR(x) #x 02758 #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) 02759 #define INTERRUPT_HANDLER( a, b ) \ 02760 _Pragma( VECTOR_ID( (b)+2 ) ) \ 02761 __interrupt void (a)( void ) 02762 #define INTERRUPT_HANDLER_TRAP(a) \ 02763 _Pragma( VECTOR_ID( 1 ) ) \ 02764 __interrupt void (a) (void) 02765 #endif /* _IAR_ */ 02766 02767 /*============================== Interrupt Handler declaration ========================*/ 02768 #ifdef _COSMIC_ 02769 #define INTERRUPT @far @interrupt 02770 #elif defined(_IAR_) 02771 #define INTERRUPT __interrupt 02772 #endif /* _COSMIC_ */ 02773 02774 /*============================== Handling bits ====================================*/ 02775 /*----------------------------------------------------------------------------- 02776 Method : I 02777 Description : Handle the bit from the character variables. 02778 Comments : The different parameters of commands are 02779 - VAR : Name of the character variable where the bit is located. 02780 - Place : Bit position in the variable (7 6 5 4 3 2 1 0) 02781 - Value : Can be 0 (reset bit) or not 0 (set bit) 02782 The "MskBit" command allows to select some bits in a source 02783 variables and copy it in a destination var (return the value). 02784 The "ValBit" command returns the value of a bit in a char 02785 variable: the bit is reset if it returns 0 else the bit is set. 02786 This method generates not an optimised code yet. 02787 -----------------------------------------------------------------------------*/ 02788 #define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) 02789 #define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) ) 02790 02791 #define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) 02792 #define AffBit(VAR,Place,Value) ((Value) ? \ 02793 ((VAR) |= ((uint8_t)1<<(Place))) : \ 02794 ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255))) 02795 #define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) 02796 02797 #define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place))) 02798 02799 #define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */ 02800 #define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */ 02801 #define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */ 02802 #define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */ 02803 02804 /*============================== Assert Macros ====================================*/ 02805 #define IS_STATE_VALUE_OK(SensitivityValue) \ 02806 (((SensitivityValue) == ENABLE) || \ 02807 ((SensitivityValue) == DISABLE)) 02808 02809 /*----------------------------------------------------------------------------- 02810 Method : II 02811 Description : Handle directly the bit. 02812 Comments : The idea is to handle directly with the bit name. For that, it is 02813 necessary to have RAM area descriptions (example: HW register...) 02814 and the following command line for each area. 02815 This method generates the most optimized code. 02816 -----------------------------------------------------------------------------*/ 02817 02818 #define AREA 0x00 /* The area of bits begins at address 0x10. */ 02819 02820 #define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) 02821 #define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) 02822 #define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) 02823 02824 /* Exported functions ------------------------------------------------------- */ 02825 02826 #endif /* __STM8S_H */ 02827 02828 /** 02829 * @} 02830 */ 02831 02832 /** 02833 * @} 02834 */ 02835 02836 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/