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stm3210e_eval_sram.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm3210e_eval_sram.c 00004 * @author MCD Application Team 00005 * @version $VERSION$ 00006 * @date $DATE$ 00007 * @brief This file includes the SRAM driver for the IS61WV51216BLL-10M memory 00008 * device mounted on STM3210E-EVAL evaluation board. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> 00013 * 00014 * Redistribution and use in source and binary forms, with or without modification, 00015 * are permitted provided that the following conditions are met: 00016 * 1. Redistributions of source code must retain the above copyright notice, 00017 * this list of conditions and the following disclaimer. 00018 * 2. Redistributions in binary form must reproduce the above copyright notice, 00019 * this list of conditions and the following disclaimer in the documentation 00020 * and/or other materials provided with the distribution. 00021 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00022 * may be used to endorse or promote products derived from this software 00023 * without specific prior written permission. 00024 * 00025 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00026 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00027 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00028 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00029 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00030 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00031 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00032 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00033 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00034 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00035 * 00036 ****************************************************************************** 00037 */ 00038 00039 /* File Info : ----------------------------------------------------------------- 00040 User NOTES 00041 1. How To use this driver: 00042 -------------------------- 00043 - This driver is used to drive the IS61WV51216BLL-10M SRAM external memory mounted 00044 on STM3210E-EVAL evaluation board. 00045 - This driver does not need a specific component driver for the SRAM device 00046 to be included with. 00047 00048 2. Driver description: 00049 --------------------- 00050 + Initialization steps: 00051 o Initialize the SRAM external memory using the BSP_SRAM_Init() function. This 00052 function includes the MSP layer hardware resources initialization and the 00053 FSMC controller configuration to interface with the external SRAM memory. 00054 00055 + SRAM read/write operations 00056 o SRAM external memory can be accessed with read/write operations once it is 00057 initialized. 00058 Read/write operation can be performed with AHB access using the functions 00059 BSP_SRAM_ReadData()/BSP_SRAM_WriteData(), or by DMA transfer using the functions 00060 BSP_SRAM_ReadData_DMA()/BSP_SRAM_WriteData_DMA(). 00061 o The AHB access is performed with 16-bit width transaction, the DMA transfer 00062 configuration is fixed at single (no burst) halfword transfer 00063 (see the SRAM_MspInit() static function). 00064 o User can implement his own functions for read/write access with his desired 00065 configurations. 00066 o If interrupt mode is used for DMA transfer, the function BSP_SRAM_DMA_IRQHandler() 00067 is called in IRQ handler file, to serve the generated interrupt once the DMA 00068 transfer is complete. 00069 00070 ------------------------------------------------------------------------------*/ 00071 00072 /* Includes ------------------------------------------------------------------*/ 00073 #include "stm3210e_eval_sram.h" 00074 00075 /** @addtogroup BSP 00076 * @{ 00077 */ 00078 00079 /** @addtogroup STM3210E_EVAL 00080 * @{ 00081 */ 00082 00083 /** @defgroup STM3210E_EVAL_SRAM STM3210E_EVAL SRAM 00084 * @{ 00085 */ 00086 00087 /* Private typedef -----------------------------------------------------------*/ 00088 00089 /** @defgroup STM3210E_EVAL_SRAM_Private_Types_Definitions Private_Types_Definitions 00090 * @{ 00091 */ 00092 00093 /** 00094 * @} 00095 */ 00096 00097 /* Private define ------------------------------------------------------------*/ 00098 00099 /** @defgroup STM3210E_EVAL_SRAM_Private_Defines Private_Defines 00100 * @{ 00101 */ 00102 00103 /** 00104 * @} 00105 */ 00106 00107 /* Private macro -------------------------------------------------------------*/ 00108 00109 /** @defgroup STM3210E_EVAL_SRAM_Private_Macros Private_Macros 00110 * @{ 00111 */ 00112 00113 /** 00114 * @} 00115 */ 00116 00117 /* Private variables ---------------------------------------------------------*/ 00118 00119 /** @defgroup STM3210E_EVAL_SRAM_Private_Variables Private_Variables 00120 * @{ 00121 */ 00122 SRAM_HandleTypeDef sramHandle; 00123 static FSMC_NORSRAM_TimingTypeDef Timing; 00124 00125 /** 00126 * @} 00127 */ 00128 00129 /* Private function prototypes -----------------------------------------------*/ 00130 00131 /** @defgroup STM3210E_EVAL_SRAM_Private_Function_Prototypes Private_Function_Prototypes 00132 * @{ 00133 */ 00134 static void SRAM_MspInit(void); 00135 00136 /** 00137 * @} 00138 */ 00139 00140 /* Private functions ---------------------------------------------------------*/ 00141 00142 /** @defgroup STM3210E_EVAL_SRAM_Exported_Functions Exported_Functions 00143 * @{ 00144 */ 00145 00146 /** 00147 * @brief Initializes the SRAM device. 00148 * @retval SRAM status 00149 */ 00150 uint8_t BSP_SRAM_Init(void) 00151 { 00152 sramHandle.Instance = FSMC_NORSRAM_DEVICE; 00153 sramHandle.Extended = FSMC_NORSRAM_EXTENDED_DEVICE; 00154 00155 /* SRAM device configuration */ 00156 Timing.AddressSetupTime = 2; 00157 Timing.AddressHoldTime = 1; 00158 Timing.DataSetupTime = 2; 00159 Timing.BusTurnAroundDuration = 1; 00160 Timing.CLKDivision = 2; 00161 Timing.DataLatency = 2; 00162 Timing.AccessMode = FSMC_ACCESS_MODE_A; 00163 00164 sramHandle.Init.NSBank = FSMC_NORSRAM_BANK3; 00165 sramHandle.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE; 00166 sramHandle.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM; 00167 sramHandle.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH; 00168 sramHandle.Init.BurstAccessMode = SRAM_BURSTACCESS; 00169 sramHandle.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW; 00170 sramHandle.Init.WrapMode = FSMC_WRAP_MODE_DISABLE; 00171 sramHandle.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS; 00172 sramHandle.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE; 00173 sramHandle.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE; 00174 sramHandle.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE; 00175 sramHandle.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE; 00176 sramHandle.Init.WriteBurst = SRAM_WRITEBURST; 00177 00178 /* SRAM controller initialization */ 00179 SRAM_MspInit(); 00180 00181 if(HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK) 00182 { 00183 return SRAM_ERROR; 00184 } 00185 else 00186 { 00187 return SRAM_OK; 00188 } 00189 } 00190 00191 /** 00192 * @brief Reads an amount of data from the SRAM device in polling mode. 00193 * @param uwStartAddress: Read start address 00194 * @param pData: Pointer to data to be read 00195 * @param uwDataSize: Size of read data from the memory 00196 * @retval SRAM status 00197 */ 00198 uint8_t BSP_SRAM_ReadData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize) 00199 { 00200 if(HAL_SRAM_Read_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00201 { 00202 return SRAM_ERROR; 00203 } 00204 else 00205 { 00206 return SRAM_OK; 00207 } 00208 } 00209 00210 /** 00211 * @brief Reads an amount of data from the SRAM device in DMA mode. 00212 * @param uwStartAddress: Read start address 00213 * @param pData: Pointer to data to be read 00214 * @param uwDataSize: Size of read data from the memory 00215 * @retval SRAM status 00216 */ 00217 uint8_t BSP_SRAM_ReadData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize) 00218 { 00219 if(HAL_SRAM_Read_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK) 00220 { 00221 return SRAM_ERROR; 00222 } 00223 else 00224 { 00225 return SRAM_OK; 00226 } 00227 } 00228 00229 /** 00230 * @brief Writes an amount of data from the SRAM device in polling mode. 00231 * @param uwStartAddress: Write start address 00232 * @param pData: Pointer to data to be written 00233 * @param uwDataSize: Size of written data from the memory 00234 * @retval SRAM status 00235 */ 00236 uint8_t BSP_SRAM_WriteData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize) 00237 { 00238 if(HAL_SRAM_Write_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00239 { 00240 return SRAM_ERROR; 00241 } 00242 else 00243 { 00244 return SRAM_OK; 00245 } 00246 } 00247 00248 /** 00249 * @brief Writes an amount of data from the SRAM device in DMA mode. 00250 * @param uwStartAddress: Write start address 00251 * @param pData: Pointer to data to be written 00252 * @param uwDataSize: Size of written data from the memory 00253 * @retval SRAM status 00254 */ 00255 uint8_t BSP_SRAM_WriteData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize) 00256 { 00257 if(HAL_SRAM_Write_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK) 00258 { 00259 return SRAM_ERROR; 00260 } 00261 else 00262 { 00263 return SRAM_OK; 00264 } 00265 } 00266 00267 /** 00268 * @brief Handles SRAM DMA transfer interrupt request. 00269 * @retval None 00270 */ 00271 void BSP_SRAM_DMA_IRQHandler(void) 00272 { 00273 HAL_DMA_IRQHandler(sramHandle.hdma); 00274 } 00275 00276 /** 00277 * @brief Initializes SRAM MSP. 00278 * @retval None 00279 */ 00280 static void SRAM_MspInit(void) 00281 { 00282 static DMA_HandleTypeDef hdma1; 00283 GPIO_InitTypeDef gpioinitstruct = {0}; 00284 /* Enable FSMC clock */ 00285 __HAL_RCC_FSMC_CLK_ENABLE(); 00286 00287 /* Enable DMA1 and DMA2 clocks */ 00288 __HAL_RCC_DMA1_CLK_ENABLE(); 00289 00290 /* Enable GPIOs clock */ 00291 __HAL_RCC_GPIOD_CLK_ENABLE(); 00292 __HAL_RCC_GPIOE_CLK_ENABLE(); 00293 __HAL_RCC_GPIOF_CLK_ENABLE(); 00294 __HAL_RCC_GPIOG_CLK_ENABLE(); 00295 00296 /* Common GPIO configuration */ 00297 gpioinitstruct.Mode = GPIO_MODE_AF_PP; 00298 gpioinitstruct.Pull = GPIO_NOPULL; 00299 gpioinitstruct.Speed = GPIO_SPEED_HIGH; 00300 00301 /*-- GPIO Configuration ------------------------------------------------------*/ 00302 /*!< SRAM Data lines configuration */ 00303 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8 | GPIO_PIN_9 | 00304 GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15; 00305 HAL_GPIO_Init(GPIOD, &gpioinitstruct); 00306 00307 gpioinitstruct.Pin = GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | 00308 GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | 00309 GPIO_PIN_15; 00310 HAL_GPIO_Init(GPIOE, &gpioinitstruct); 00311 00312 /*!< SRAM Address lines configuration */ 00313 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | 00314 GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 | 00315 GPIO_PIN_14 | GPIO_PIN_15; 00316 HAL_GPIO_Init(GPIOF, &gpioinitstruct); 00317 00318 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | 00319 GPIO_PIN_4 | GPIO_PIN_5; 00320 HAL_GPIO_Init(GPIOG, &gpioinitstruct); 00321 00322 gpioinitstruct.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13; 00323 HAL_GPIO_Init(GPIOD, &gpioinitstruct); 00324 00325 /*!< NOE and NWE configuration */ 00326 gpioinitstruct.Pin = GPIO_PIN_4 |GPIO_PIN_5; 00327 HAL_GPIO_Init(GPIOD, &gpioinitstruct); 00328 00329 /*!< NE3 configuration */ 00330 gpioinitstruct.Pin = GPIO_PIN_10; 00331 HAL_GPIO_Init(GPIOG, &gpioinitstruct); 00332 00333 /*!< NBL0, NBL1 configuration */ 00334 gpioinitstruct.Pin = GPIO_PIN_0 | GPIO_PIN_1; 00335 HAL_GPIO_Init(GPIOE, &gpioinitstruct); 00336 00337 /* Configure common DMA parameters */ 00338 hdma1.Init.Direction = DMA_MEMORY_TO_MEMORY; 00339 hdma1.Init.PeriphInc = DMA_PINC_ENABLE; 00340 hdma1.Init.MemInc = DMA_MINC_ENABLE; 00341 hdma1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; 00342 hdma1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; 00343 hdma1.Init.Mode = DMA_NORMAL; 00344 hdma1.Init.Priority = DMA_PRIORITY_HIGH; 00345 00346 hdma1.Instance = DMA1_Channel1; 00347 00348 /* Deinitialize the Stream for new transfer */ 00349 HAL_DMA_DeInit(&hdma1); 00350 00351 /* Configure the DMA Stream */ 00352 HAL_DMA_Init(&hdma1); 00353 00354 /* Associate the DMA handle to the FSMC SRAM one */ 00355 sramHandle.hdma = &hdma1; 00356 00357 /* NVIC configuration for DMA transfer complete interrupt */ 00358 HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 00359 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 00360 00361 } 00362 /** 00363 * @} 00364 */ 00365 00366 /** 00367 * @} 00368 */ 00369 00370 /** 00371 * @} 00372 */ 00373 00374 /** 00375 * @} 00376 */ 00377 00378 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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