niFgen_AdjustSampleClockRelativeDelay
ViStatus niFgen_AdjustSampleClockRelativeDelay (ViSession vi, ViReal64 adjustmentTime);
Purpose
Delays (or phase shifts) the sample clock, which delays the generated signal. Delaying the sample clock can be useful when synchronizing the output of multiple modules or when intentionally phase shifting the output relative to a fixed reference, such as the PLL reference clock.
Adjustment time can be positive or negative, but it must be less than or equal to the sample clock period. The delay takes effect immediately after this function is called. To delay an external sample clock, use the NIFGEN_ATTR_SAMPLE_CLOCK_ABSOLUTE_DELAY attribute.
Parameters
| Input | ||
| Name | Type | Description |
| vi | ViSession | Identifies your instrument session. vi is obtained from the niFgen_init or the niFgen_InitWithOptions functions and identifies a particular instrument session. |
| adjustmentTime | ViReal64 | Specifies the amount of time to adjust the sample clock delay in seconds.
Default Value: 0 |
Return Value
| Name | Type | Description | ||||||||
| Status | ViStatus | Returns the status code of this operation. The status code either indicates success or describes an error or warning condition. You can examine the status code from each call to an NI-FGEN function to determine if an error occurred.
To obtain a text description of the status code, call the niFgen_error_message function. To obtain additional information about the error condition, call the niFgen_GetError function. To clear the error information from NI-FGEN, call the niFgen_ClearError function. The general meaning of the status code is as follows:
|