Signals for Synchronizing DSA Devices

For a sample clock timebase synchronized DSA system, the Sample Clock Timebase, Sync Pulse, and Start Trigger signals must be shared between the master and slave devices. The master device is the source of all three signals.

Note  If you are developing a synchronized DSA application using PXI devices, and if you are using sample clock timebase synchronization, the master DSA device must reside in slot 2 of the PXI chassis.

For a reference clock synchronized DSA system, the Sync Pulse and Start Trigger signals must be shared between the master and the slave devices, and all devices must specify PXI_Clk10 as the reference clock source. The master device is the source of the Sync Pulse and Start Trigger.

Sample Clock Timebase

In a PXI system, the master device exports the Sample Clock Timebase to one or more PXI_Star lines. For PCI DSA devices, the Sample Clock Timebase can only be exported or imported on RTSI 8. Other devices, such as E Series devices, cannot access this signal. The frequency of the Sample Clock Timebase depends on the desired sampling rate and on the DSA device, but in every case, this signal is many times faster than the desired sampling rate. The slave DSA devices individually divide the Sample Clock Timebase signal internally to produce their sample clocks. You can access the Sample Clock Timebase signal with the Sample Clock Source attribute/property.

Sync Pulse

The Sync Pulse simultaneously resets the internal clock dividers and converters on each DSA device in the system. This eliminates any phase difference on the Sample Clock Timebase dividers on each device to guarantee tight phase matching across input and output channels in the system. In NI PXI 447X devices, this signal must be routed along PXI_Trig5. In NI PCI 447X devices, the Sync Pulse must be routed along RTSI 9. In NI 446X devices, you can use any RTSI or PXI_Trig line from RTSI0::6 or PXI_Trig0::6. You can program the Sync Pulse routing with the SyncPulse.Src attribute/property.

The Sync Pulse is not sent until you commit the master task. Starting a task also commits it. The slave task must be committed before the master task. If doing analog output, the Write function/VI commits the task. You must call this function/VI on the slave task before the master. The converter reset operation that follows the Sync Pulse requires some time, from several milliseconds to several seconds, depending on the sampling rate and specific DSA devices in the system. This reset time must elapse before the acquisition begins. The reset delay is not present in single-device DSA systems. In general, the delay is noticeable only at sampling rates below about 10 kS/s.

Note  If you set the Sync Pulse source on a task to its own Sync Pulse signal, that task will be configured as a slave task. You must not program the SyncPulse.Src attribute/property unless you want the task to be programmed as a slave task.

Start Trigger

You should program each slave device for digital triggering using the appropriate RTSI or PXI_Trig line as the trigger source. The master device can export this signal on RTSI/PXI_Trig0::4 (NI 447X devices) or RTSI/PXI_Trig0::6 (NI 446X devices).

Reference Clock

When using reference clock synchronization, the sample clock timebase is not shared between master and slave tasks. Instead, all devices lock their onboard sample clock timebase to a shared 10 MHz signal on the PXI chassis backplane. You can program the reference clock source with the RefClk.Src attribute/property. The syntax for this is PXI Clk_10.