Writing to DMA FIFOs from Host VIs (FPGA Interface)

You can create Direct Memory Access (DMA) FIFOs to transfer data from host VIs to FPGA VIs. Some FPGA targets do not support DMA. The FPGA targets that support DMA include a fixed number of DMA channels available for transferring data between the host VI and FPGA VI. Refer to the specific FPGA target hardware documentation for information about the number of DMA channels available, if the FPGA target supports DMA.

Complete the following steps to write to a DMA FIFO in an FPGA VI.

1. Open a reference to an FPGA VI or bitfile.

   Note  The FPGA target, FPGA VI, and host VI must be in the same LabVIEW project if you want to open a reference to an FPGA VI. The host VI does not need to be in a project if you open a reference to a bitfile. If you open a reference to an FPGA VI, the project must include a DMA FIFO item under the FPGA target and the FPGA VI must include a FIFO Read function on the block diagram that reads the DMA FIFO item.

2. Place an Invoke Method function on the block diagram of the host VI in the data flow where you want the host VI to write to the DMA FIFO. Wire the FPGA VI Reference In input.
   
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3. Click the Invoke Method function and select FIFO»Write from the shortcut menu, where FIFO is the name of the FIFO item in the project. Wire the inputs and outputs as needed. The Write method returns Empty Elements Remaining when the data is written or when the Timeout period ends.
4. Place the Close FPGA VI Reference function on the block diagram.
   
    Place  Find
5. Wire the FPGA VI Reference Out output on the Invoke Node to the FPGA VI Reference In input on the Close FPGA VI Reference function.

Note  You can write DMA FIFOs using only the Invoke Method function with the Write method. If you want more control over the DMA FIFO from the host VI, you also can configure, start, and stop the DMA FIFO using the optional Configure, Start, and Stop methods with the Invoke Method function.