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GD32F1x0: USB/GD32_USB_Device_Driver/inc/usb_regs.h Source File

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usb_regs.h
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1 
11 /* Define to prevent recursive inclusion -------------------------------------*/
12 #ifndef __GD32F1X0_USB_REGS_H
13 #define __GD32F1X0_USB_REGS_H
14 
15 /* Includes ------------------------------------------------------------------*/
16 #include "usb_conf.h"
17 
37 enum USB_SPEED
38 {
39  USB_SPEED_LOW,
40  USB_SPEED_FULL
41 };
42 
46 typedef enum _DBUF_EP_DIR
47 {
48  DBUF_EP_IN,
49  DBUF_EP_OUT,
50  DBUF_EP_ERR,
51 }
52 DBUF_EP_DIR;
53 
61 #define Reg_Base (0x40005C00L)
62 #define PBA_Addr (0x40006000L)
71 #define CTLR ((__IO unsigned *)(Reg_Base + 0x40))
72 #define IFR ((__IO unsigned *)(Reg_Base + 0x44))
73 #define SR ((__IO unsigned *)(Reg_Base + 0x48))
74 #define AR ((__IO unsigned *)(Reg_Base + 0x4C))
75 #define BAR ((__IO unsigned *)(Reg_Base + 0x50))
84 #define SUB_EP0REG ((__IO unsigned *)(Reg_Base + 0x100))
85 #define LPM_CNTR ((__IO unsigned *)(Reg_Base + 0x140))
86 #define LPM_ISTR ((__IO unsigned *)(Reg_Base + 0x144))
95 #define EP0CSR ((__IO unsigned *)(Reg_Base))
108 #define EP0_OUT ((uint8_t)0x00)
109 #define EP0_IN ((uint8_t)0x80)
110 #define EP1_OUT ((uint8_t)0x01)
111 #define EP1_IN ((uint8_t)0x81)
112 #define EP2_OUT ((uint8_t)0x02)
113 #define EP2_IN ((uint8_t)0x82)
114 #define EP3_OUT ((uint8_t)0x03)
115 #define EP3_IN ((uint8_t)0x83)
116 #define EP4_OUT ((uint8_t)0x04)
117 #define EP4_IN ((uint8_t)0x84)
118 #define EP5_OUT ((uint8_t)0x05)
119 #define EP5_IN ((uint8_t)0x85)
120 #define EP6_OUT ((uint8_t)0x06)
121 #define EP6_IN ((uint8_t)0x86)
122 #define EP7_OUT ((uint8_t)0x07)
123 #define EP7_IN ((uint8_t)0x87)
124 
132 #define EP0 ((uint8_t)0)
133 #define EP1 ((uint8_t)1)
134 #define EP2 ((uint8_t)2)
135 #define EP3 ((uint8_t)3)
136 #define EP4 ((uint8_t)4)
137 #define EP5 ((uint8_t)5)
138 #define EP6 ((uint8_t)6)
139 #define EP7 ((uint8_t)7)
140 
152 #define CTLR_STIE (0x8000)
153 #define CTLR_PMOUIE (0x4000)
154 #define CTLR_ERRIE (0x2000)
155 #define CTLR_WKUPIE (0x1000)
156 #define CTLR_SPSIE (0x0800)
157 #define CTLR_RSTIE (0x0400)
158 #define CTLR_SOFIE (0x0200)
159 #define CTLR_ESOFIE (0x0100)
160 #define CTLR_RSREQ (0x0010)
161 #define CTLR_SETSPS (0x0008)
162 #define CTLR_LOWM (0x0004)
163 #define CTLR_CLOSE (0x0002)
164 #define CTLR_SETRST (0x0001)
169 #define IFR_STIF (0x8000)
170 #define IFR_PMOUIF (0x4000)
171 #define IFR_ERRIF (0x2000)
172 #define IFR_WKUPIF (0x1000)
173 #define IFR_SPSIF (0x0800)
174 #define IFR_RSTIF (0x0400)
175 #define IFR_SOFIF (0x0200)
176 #define IFR_ESOFIF (0x0100)
177 #define IFR_DIR (0x0010)
178 #define IFR_EPNUM (0x000F)
180 #define CLR_STIF (~IFR_STIF)
181 #define CLR_PMOUIF (~IFR_PMOUIF)
182 #define CLR_ERRIF (~IFR_ERRIF)
183 #define CLR_WKUPIF (~IFR_WKUPIF)
184 #define CLR_SPSIF (~IFR_SPSIF)
185 #define CLR_RSTIF (~IFR_RSTIF)
186 #define CLR_SOFIF (~IFR_SOFIF)
187 #define CLR_ESOFIF (~IFR_ESOFIF)
192 #define SR_RXDP (0x8000)
193 #define SR_RXDM (0x4000)
194 #define SR_LOCK (0x2000)
195 #define SR_SOFLN (0x1800)
196 #define SR_FCNT (0x07FF)
201 #define AR_USBEN (0x80)
202 #define AR_USBADDR (0x7F)
207 #define SUB_ST (0x8000)
208 #define SUB_STA (0x3000)
209 #define SUBPID_ATTR (0x07ff)
211 #define ATTR_BREMOTEWAKE (0x0100)
212 #define ATTR_HIRD (0x00f0)
213 #define ATTR_BLINKSTATE (0x000f)
218 #define SUBEP_DISABLE (0x0000)
219 #define SUBEP_STALL (0x1000)
220 #define SUBEP_NYET (0x2000)
221 #define SUBEP_VALID (0x3000)
226 #define LPM_STIE (0x8000)
231 #define LPM_STIF (0x8000)
232 #define LPM_CLR_STIF (~LPM_STIF)
237 #define EPRX_ST (0x8000)
238 #define EPRX_DTG (0x4000)
239 #define EPRX_STA (0x3000)
240 #define EP_SETUP (0x0800)
241 #define EP_CTL (0x0600)
242 #define EP_KCTL (0x0100)
243 #define EPTX_ST (0x0080)
244 #define EPTX_DTG (0x0040)
245 #define EPTX_STA (0x0030)
246 #define EP_AR (0x000F)
251 #define EPCSR_MASK (EPRX_ST|EP_SETUP|EP_CTL|EP_KCTL|EPTX_ST|EP_AR)
252 
256 #define EP_BULK (0x0000)
257 #define EP_CONTROL (0x0200)
258 #define EP_ISO (0x0400)
259 #define EP_INTERRUPT (0x0600)
260 #define EP_CTL_MASK (~EP_CTL & EPCSR_MASK)
261 
265 #define EPKCTL_MASK (~EP_KCTL & EPCSR_MASK)
266 
270 #define EPTX_DISABLED (0x0000)
271 #define EPTX_STALL (0x0010)
272 #define EPTX_NAK (0x0020)
273 #define EPTX_VALID (0x0030)
274 #define EPTX_DTGMASK (EPTX_STA | EPCSR_MASK)
275 
279 #define EPRX_DISABLED (0x0000)
280 #define EPRX_STALL (0x1000)
281 #define EPRX_NAK (0x2000)
282 #define EPRX_VALID (0x3000)
283 #define EPRX_DTGMASK (EPRX_STA | EPCSR_MASK)
284 
288 #define EPRXCNTR_BLKSIZ (0x8000)
289 #define EPRXCNTR_BLKNUM (0x7C00)
290 #define EPRXCNTR_CNT (0x03FF)
291 
292 #define EPTXCNTR_CNT (0x03FF)
293 
297 #define BLKSIZE_OFFSET (0x01)
298 #define BLKNUM_OFFSET (0x05)
299 #define RXCNT_OFFSET (0x0A)
300 
301 #define TXCNT_OFFSET (0x0A)
302 
303 #define BLKSIZE32_MASK (0x1f)
304 #define BLKSIZE2_MASK (0x01)
305 
306 #define BLKSIZE32_OFFSETMASK (0x05)
307 #define BLKSIZE2_OFFSETMASK (0x01)
308 
321 /* Set CTLR */
322 #define _SetCTLR(RegValue) (*CTLR = (uint16_t)RegValue)
323 
324 /* Get CTLR */
325 #define _GetCTLR() ((uint16_t) *CTLR)
326 
327 /* Set IFR */
328 #define _SetIFR(RegValue) (*IFR = (uint16_t)RegValue)
329 
330 /* Get IFR */
331 #define _GetIFR() ((uint16_t) *IFR)
332 
333 /* Set AR */
334 #define _SetAR(RegValue) (*AR = (uint16_t)RegValue)
335 
336 /* Get AR */
337 #define _GetAR() ((uint16_t) *AR)
338 
339 /* Set BAR */
340 #define _SetBAR(RegValue) (*BAR = (uint16_t)(RegValue & 0xFFF8))
341 
342 /* Get BAR */
343 #define _GetBAR() ((uint16_t) *BAR)
344 
345 /* Get SR */
346 #define _GetSR() ((uint16_t) *SR)
347 
348 /* Set EPxCSR */
349 #define _SetEPxCSR(EpID,RegValue) (*(EP0CSR + EpID) = (uint16_t)RegValue)
350 
351 /* Get EPxCSR*/
352 #define _GetEPxCSR(EpID) ((uint16_t)(*(EP0CSR + EpID)))
353 
354 /* Set LPMCNTR */
355 #define _SetLPM_CNTR(RegValue) (*LPM_CNTR = (uint16_t)RegValue)
356 
357 /* Get LPMCNTR */
358 #define _GetLPM_CNTR() ((uint16_t) *LPM_CNTR)
359 
360 /* Set LPMISTR */
361 #define _SetLPM_ISTR(RegValue) (*LPM_ISTR = (uint16_t)RegValue)
362 
363 /* Get LPMISTR */
364 #define _GetLPM_ISTR() ((uint16_t) *LPM_ISTR)
365 
366 /* Set SUBEP0R */
367 #define _SetSUBEP0R(RegValue) (*SUB_EP0REG = (uint16_t)RegValue)
368 
369 /* Get SUBEP0R */
370 #define _GetSUBEP0R() ((uint16_t)*SUB_EP0REG)
371 
391 #define _SetEPType(EpID, Type) (_SetEPxCSR(EpID, ((_GetEPxCSR(EpID) & EP_CTL_MASK) | Type)))
392 
393 #define _GetEPType(EpID) (_GetEPxCSR(EpID) & EP_CTL)
394 
395 
407 #define _SetEPTxStatus(EpID, State) {\
408  register uint16_t _RegVal; \
409  _RegVal = _GetEPxCSR(EpID) & EPTX_DTGMASK;\
410  _SetEPxCSR(EpID, (_RegVal ^ State)); \
411 }
412 
413 #define _GetEPTxStatus(EpID) ((uint16_t)_GetEPxCSR(EpID) & EPTX_STA)
414 
426 #define _SetEPRxStatus(EpID, State) {\
427  register uint16_t _RegVal; \
428  _RegVal = _GetEPxCSR(EpID) & EPRX_DTGMASK;\
429  _SetEPxCSR(EpID, (_RegVal ^ State)); \
430 }
431 
432 #define _GetEPRxStatus(EpID) ((uint16_t)_GetEPxCSR(EpID) & EPRX_STA)
433 
451 #define _SetEPRxTxStatus(EpID, StateRx, StateTx) {\
452  register uint16_t _RegVal; \
453  _RegVal = _GetEPxCSR(EpID) & (EPRX_DTGMASK | EPTX_STA) ;\
454  _SetEPxCSR(EpID, ((_RegVal ^ StateRx) ^ StateTx)); \
455 }
456 
462 #define _SetEP_KIND(EpID) (_SetEPxCSR(EpID, ((_GetEPxCSR(EpID) | EP_KCTL) & EPCSR_MASK)))
463 
464 #define _ClearEP_KIND(EpID) (_SetEPxCSR(EpID, (_GetEPxCSR(EpID) & EPKCTL_MASK)))
465 
471 #define _Set_Status_Out(EpID) _SetEP_KIND(EpID)
472 
473 #define _Clear_Status_Out(EpID) _ClearEP_KIND(EpID)
474 
480 #define _SetEPDoubleBuff(EpID) _SetEP_KIND(EpID)
481 
482 #define _ClearEPDoubleBuff(EpID) _ClearEP_KIND(EpID)
483 
489 #define _ClearEPRX_ST(EpID) (_SetEPxCSR(EpID, _GetEPxCSR(EpID) & 0x7FFF & EPCSR_MASK))
490 
491 #define _ClearEPTX_ST(EpID) (_SetEPxCSR(EpID, _GetEPxCSR(EpID) & 0xFF7F & EPCSR_MASK))
492 
498 #define _ToggleDTG_RX(EpID) (_SetEPxCSR(EpID, EPRX_DTG | (_GetEPxCSR(EpID) & EPCSR_MASK)))
499 
500 #define _ClearDTG_RX(EpID) if((_GetEPxCSR(EpID) & EPRX_DTG) != 0) _ToggleDTG_RX(EpID)
501 
507 #define _ToggleDTG_TX(EpID) (_SetEPxCSR(EpID, EPTX_DTG | (_GetEPxCSR(EpID) & EPCSR_MASK)))
508 
509 #define _ClearDTG_TX(EpID) if((_GetEPxCSR(EpID) & EPTX_DTG) != 0) _ToggleDTG_TX(EpID)
510 
516 #define _ToggleSWBUF_TX(EpID) _ToggleDTG_RX(EpID)
517 
518 #define _ToggleSWBUF_RX(EpID) _ToggleDTG_TX(EpID)
519 
526 #define _SetEPAddress(EpID,Addr) _SetEPxCSR(EpID, (_GetEPxCSR(EpID) & EPCSR_MASK) | Addr)
527 
528 #define _GetEPAddress(EpID) ((uint8_t)(_GetEPxCSR(EpID) & EP_AR))
529 
535 #define _GetEPTXARn(EpID) ((uint32_t *)((_GetBAR() + EpID * 8) * 2 + PBA_Addr))
536 
542 #define _GetEPTXCNTx(EpID) ((uint32_t *)((_GetBAR() + EpID * 8 + 2) * 2 + PBA_Addr))
543 
549 #define _GetEPRXARn(EpID) ((uint32_t *)((_GetBAR() + EpID * 8 + 4) * 2 + PBA_Addr))
550 
556 #define _GetEPRXCNTx(EpID) ((uint32_t *)((_GetBAR() + EpID * 8 + 6) * 2 + PBA_Addr))
557 
564 #define _SetEPTxAddr(EpID, Addr) (*_GetEPTXARn(EpID) = (Addr & ~((uint16_t)1)))
565 #define _SetEPRxAddr(EpID, Addr) (*_GetEPRXARn(EpID) = (Addr & ~((uint16_t)1)))
566 
572 #define _GetEPTxAddr(EpID) ((uint16_t)*_GetEPTXARn(EpID))
573 #define _GetEPRxAddr(EpID) ((uint16_t)*_GetEPRXARn(EpID))
574 
581 #define _BlocksOf32(pdwReg, Count) {\
582  register uint16_t BlockNum = Count >> BLKSIZE32_OFFSETMASK;\
583  if((Count & BLKSIZE32_MASK) == 0)\
584  BlockNum--;\
585  *pdwReg = (uint32_t)((BlockNum << RXCNT_OFFSET) | EPRXCNTR_BLKSIZ);\
586 }
587 
594 #define _BlocksOf2(pdwReg, Count) {\
595  register uint16_t BlockNum = Count >> BLKSIZE2_OFFSETMASK;\
596  if((Count & BLKSIZE2_MASK) != 0)\
597  BlockNum++;\
598  *pdwReg = (uint32_t)(BlockNum << RXCNT_OFFSET);\
599 }
600 
607 #define _SetEPRxDblBuf0Count(EpID, Count) {\
608  uint32_t *pdwReg = _GetEPTXCNTx(EpID); \
609  if(Count > 62) { _BlocksOf32(pdwReg, Count); } \
610  else { _BlocksOf32(pdwReg, Count); } \
611 }
612 
619 #define _SetEPTxCount(EpID, Count) (*_GetEPTXCNTx(EpID) = Count)
620 #define _SetEPRxCount(EpID, Count) {\
621  uint32_t *pdwReg = _GetEPRXCNTx(EpID); \
622  if(Count > 62) { _BlocksOf32(pdwReg, Count); } \
623  else { _BlocksOf2(pdwReg, Count); } \
624 }
625 
631 #define _GetEPTxCount(EpID)((uint16_t) (*_GetEPTXCNTx(EpID)) & EPTXCNTR_CNT)
632 #define _GetEPRxCount(EpID)((uint16_t) (*_GetEPRXCNTx(EpID)) & EPRXCNTR_CNT)
633 
641 #define _SetEPDblBuf0Addr(EpID, Buf0Addr) {_SetEPTxAddr(EpID, Buf0Addr);}
642 #define _SetEPDblBuf1Addr(EpID, Buf1Addr) {_SetEPRxAddr(EpID, Buf1Addr);}
643 
651 #define _SetEPDblBufAddr(EpID, Buf0Addr, Buf1Addr) { \
652  _SetEPDblBuf0Addr(EpID, Buf0Addr);\
653  _SetEPDblBuf1Addr(EpID, Buf1Addr);\
654 }
655 
661 #define _GetEPDblBuf0Addr(EpID) (_GetEPTxAddr(EpID))
662 #define _GetEPDblBuf1Addr(EpID) (_GetEPRxAddr(EpID))
663 
674 #define _SetEPDblBuf0Count(EpID, Dir, Count) { \
675  if(Dir == DBUF_EP_OUT)\
676  {_SetEPRxDblBuf0Count(EpID, Count);} \
677  else if(Dir == DBUF_EP_IN)\
678  {*_GetEPTXCNTx(EpID) = (uint32_t)Count;} \
679 }
680 
681 #define _SetEPDblBuf1Count(EpID, Dir, Count) { \
682  if(Dir == DBUF_EP_OUT)\
683  {_SetEPRxCount(EpID, Count);}\
684  else if(Dir == DBUF_EP_IN)\
685  {*_GetEPRXCNTx(EpID) = (uint32_t)Count;} \
686 }
687 
688 #define _SetEPDblBuffCount(EpID, Dir, Count) {\
689  _SetEPDblBuf0Count(EpID, Dir, Count); \
690  _SetEPDblBuf1Count(EpID, Dir, Count); \
691 }
692 
698 #define _GetEPDblBuf0Count(EpID) (_GetEPTxCount(EpID))
699 #define _GetEPDblBuf1Count(EpID) (_GetEPRxCount(EpID))
700 
710 #define _SetDouBleBuffEPStall(EpID, Dir) {\
711  if (Dir == DBUF_EP_OUT) \
712  { \
713  _SetEPxCSR(EpID, _GetEPxCSR(EpID) & ~EPRX_STALL); \
714  } \
715  else if (Dir == DBUF_EP_IN) \
716  { \
717  _SetEPxCSR(EpID, _GetEPxCSR(EpID) & ~EPTX_STALL); \
718  } \
719 }
720 
729 #endif /* __GD32F1X0_USB_REGS_H */
730 
743 /************************ (C) COPYRIGHT 2014 GIGADEVICE *****END OF FILE****/
_DBUF_EP_DIR
_DBUF_EP_DIR
USB double buffer endpoint direction.
Definition: usb_regs.h:46
USB_SPEED
USB_SPEED
USB device speed.
Definition: usb_regs.h:37
DBUF_EP_DIR
enum _DBUF_EP_DIR DBUF_EP_DIR
USB double buffer endpoint direction.
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