CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: Member List

CoffeeLake Intel Firmware

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CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide
FSP_M_CONFIG Member List

This is the complete list of members for FSP_M_CONFIG, including all inherited members.

ActEnergyCh0Dimm0FSP_M_CONFIG
ActEnergyCh0Dimm1FSP_M_CONFIG
ActEnergyCh1Dimm0FSP_M_CONFIG
ActEnergyCh1Dimm1FSP_M_CONFIG
ActiveCoreCountFSP_M_CONFIG
ALIASCHKFSP_M_CONFIG
ApertureSizeFSP_M_CONFIG
ApStartupBaseFSP_M_CONFIG
Avx2RatioOffsetFSP_M_CONFIG
Avx3RatioOffsetFSP_M_CONFIG
BclkAdaptiveVoltageFSP_M_CONFIG
BClkFrequencyFSP_M_CONFIG
BiosAcmBaseFSP_M_CONFIG
BiosAcmSizeFSP_M_CONFIG
BiosGuardFSP_M_CONFIG
BiosGuardToolsInterfaceFSP_M_CONFIG
BistOnResetFSP_M_CONFIG
BootFrequencyFSP_M_CONFIG
CaVrefConfigFSP_M_CONFIG
ChHashEnableFSP_M_CONFIG
ChHashInterleaveBitFSP_M_CONFIG
ChHashMaskFSP_M_CONFIG
CkeRankMappingFSP_M_CONFIG
CleanMemoryFSP_M_CONFIG
CMDDSEQFSP_M_CONFIG
CMDNORMFSP_M_CONFIG
CmdRanksTerminatedFSP_M_CONFIG
CMDSRFSP_M_CONFIG
CMDVCFSP_M_CONFIG
CoreMaxOcRatioFSP_M_CONFIG
CorePllVoltageOffsetFSP_M_CONFIG
CoreVoltageAdaptiveFSP_M_CONFIG
CoreVoltageModeFSP_M_CONFIG
CoreVoltageOffsetFSP_M_CONFIG
CoreVoltageOverrideFSP_M_CONFIG
CpuRatioFSP_M_CONFIG
CpuTraceHubMemReg0SizeFSP_M_CONFIG
CpuTraceHubMemReg1SizeFSP_M_CONFIG
CpuTraceHubModeFSP_M_CONFIG
DciUsb3TypecUfpDbgFSP_M_CONFIG
Ddr4DdpSharedClockFSP_M_CONFIG
Ddr4DdpSharedZqFSP_M_CONFIG
Ddr4MixedUDimm2DpcLimitFSP_M_CONFIG
DdrFreqLimitFSP_M_CONFIG
DdrThermalSensorFSP_M_CONFIG
DIMMODTTFSP_M_CONFIG
DIMMRONTFSP_M_CONFIG
DisableDimmChannel0FSP_M_CONFIG
DisableDimmChannel1FSP_M_CONFIG
DisableMtrrProgramFSP_M_CONFIG
DllBwEn0FSP_M_CONFIG
DllBwEn1FSP_M_CONFIG
DllBwEn2FSP_M_CONFIG
DllBwEn3FSP_M_CONFIG
DmiDeEmphasisFSP_M_CONFIG
DmiGen3EndPointHintFSP_M_CONFIG
DmiGen3EndPointPresetFSP_M_CONFIG
DmiGen3ProgramStaticEqFSP_M_CONFIG
DmiGen3RootPortPresetFSP_M_CONFIG
DmiGen3RxCtlePeakingFSP_M_CONFIG
DqByteMapCh0FSP_M_CONFIG
DqByteMapCh1FSP_M_CONFIG
DqPinsInterleavedFSP_M_CONFIG
DqsMapCpu2DramCh0FSP_M_CONFIG
DqsMapCpu2DramCh1FSP_M_CONFIG
DualDimmPerChannelBoardTypeFSP_M_CONFIG
EccSupportFSP_M_CONFIG
ECTFSP_M_CONFIG
EnableC6DramFSP_M_CONFIG
EnableCltmFSP_M_CONFIG
EnableExttsFSP_M_CONFIG
EnableOltmFSP_M_CONFIG
EnablePwrDnFSP_M_CONFIG
EnablePwrDnLpddrFSP_M_CONFIG
EnableSgxFSP_M_CONFIG
EnBERFSP_M_CONFIG
EnCmdRateFSP_M_CONFIG
EnergyScaleFactFSP_M_CONFIG
EnhancedInterleaveFSP_M_CONFIG
EpgEnableFSP_M_CONFIG
ERDMPRTC2DFSP_M_CONFIG
ERDTC2DFSP_M_CONFIG
EWRDSEQFSP_M_CONFIG
EWRTC2DFSP_M_CONFIG
ExitOnFailureFSP_M_CONFIG
FClkFrequencyFSP_M_CONFIG
FivrEfficiencyFSP_M_CONFIG
FivrFaultsFSP_M_CONFIG
ForceOltmOrRefresh2xFSP_M_CONFIG
FreqSaGvLowFSP_M_CONFIG
FreqSaGvMidFSP_M_CONFIG
GdxcEnableFSP_M_CONFIG
GdxcIotSizeFSP_M_CONFIG
GdxcMotSizeFSP_M_CONFIG
GmAdrFSP_M_CONFIG
GtExtraTurboVoltageFSP_M_CONFIG
GtMaxOcRatioFSP_M_CONFIG
GtPllVoltageOffsetFSP_M_CONFIG
GtPsmiSupportFSP_M_CONFIG
GttMmAdrFSP_M_CONFIG
GttSizeFSP_M_CONFIG
GtusExtraTurboVoltageFSP_M_CONFIG
GtusMaxOcRatioFSP_M_CONFIG
GtusVoltageModeFSP_M_CONFIG
GtusVoltageOffsetFSP_M_CONFIG
GtusVoltageOverrideFSP_M_CONFIG
GtVoltageModeFSP_M_CONFIG
GtVoltageOffsetFSP_M_CONFIG
GtVoltageOverrideFSP_M_CONFIG
Heci1BarAddressFSP_M_CONFIG
Heci2BarAddressFSP_M_CONFIG
Heci3BarAddressFSP_M_CONFIG
HeciTimeoutsFSP_M_CONFIG
HobBufferSizeFSP_M_CONFIG
HotBudgetCh0Dimm0FSP_M_CONFIG
HotBudgetCh0Dimm1FSP_M_CONFIG
HotBudgetCh1Dimm0FSP_M_CONFIG
HotBudgetCh1Dimm1FSP_M_CONFIG
HotThresholdCh0Dimm0FSP_M_CONFIG
HotThresholdCh0Dimm1FSP_M_CONFIG
HotThresholdCh1Dimm0FSP_M_CONFIG
HotThresholdCh1Dimm1FSP_M_CONFIG
HyperThreadingFSP_M_CONFIG
Idd3nFSP_M_CONFIG
Idd3pFSP_M_CONFIG
IdleEnergyCh0Dimm0FSP_M_CONFIG
IdleEnergyCh0Dimm1FSP_M_CONFIG
IdleEnergyCh1Dimm0FSP_M_CONFIG
IdleEnergyCh1Dimm1FSP_M_CONFIG
IedSizeFSP_M_CONFIG
IgdDvmt50PreAllocFSP_M_CONFIG
ImrRpSelectionFSP_M_CONFIG
InitPcieAspmAfterOpromFSP_M_CONFIG
InternalGfxFSP_M_CONFIG
IsTPMPresenceFSP_M_CONFIG
IsvtIoPortFSP_M_CONFIG
JtagC10PowerGateDisableFSP_M_CONFIG
JWRLFSP_M_CONFIG
LCTFSP_M_CONFIG
LpDdrDqDqsReTrainingFSP_M_CONFIG
McPllVoltageOffsetFSP_M_CONFIG
MemorySpdDataLenFSP_M_CONFIG
MemorySpdPtr00FSP_M_CONFIG
MemorySpdPtr01FSP_M_CONFIG
MemorySpdPtr10FSP_M_CONFIG
MemorySpdPtr11FSP_M_CONFIG
MemoryTraceFSP_M_CONFIG
MemTestOnWarmBootFSP_M_CONFIG
MEMTSTFSP_M_CONFIG
MmioSizeFSP_M_CONFIG
MmioSizeAdjustmentFSP_M_CONFIG
MrcFastBootFSP_M_CONFIG
MrcSafeConfigFSP_M_CONFIG
NModeSupportFSP_M_CONFIG
OcLockFSP_M_CONFIG
OcSupportFSP_M_CONFIG
OddRatioModeFSP_M_CONFIG
PcdDebugInterfaceFlagsFSP_M_CONFIG
PcdIsaSerialUartBaseFSP_M_CONFIG
PcdSerialDebugBaudRateFSP_M_CONFIG
PcdSerialDebugLevelFSP_M_CONFIG
PcdSerialIoUartNumberFSP_M_CONFIG
PchHdaEnableFSP_M_CONFIG
PchIshEnableFSP_M_CONFIG
PchLpcEnhancePort8xhDecodingFSP_M_CONFIG
PchNumRsvdSmbusAddressesFSP_M_CONFIG
PchPcieHsioRxSetCtleFSP_M_CONFIG
PchPcieHsioRxSetCtleEnableFSP_M_CONFIG
PchPcieHsioTxGen1DeEmphFSP_M_CONFIG
PchPcieHsioTxGen1DeEmphEnableFSP_M_CONFIG
PchPcieHsioTxGen1DownscaleAmpFSP_M_CONFIG
PchPcieHsioTxGen1DownscaleAmpEnableFSP_M_CONFIG
PchPcieHsioTxGen2DeEmph3p5FSP_M_CONFIG
PchPcieHsioTxGen2DeEmph3p5EnableFSP_M_CONFIG
PchPcieHsioTxGen2DeEmph6p0FSP_M_CONFIG
PchPcieHsioTxGen2DeEmph6p0EnableFSP_M_CONFIG
PchPcieHsioTxGen2DownscaleAmpFSP_M_CONFIG
PchPcieHsioTxGen2DownscaleAmpEnableFSP_M_CONFIG
PchPcieHsioTxGen3DownscaleAmpFSP_M_CONFIG
PchPcieHsioTxGen3DownscaleAmpEnableFSP_M_CONFIG
PchPort80RouteFSP_M_CONFIG
PchPreMemRsvdFSP_M_CONFIG
PchSataHsioRxGen1EqBoostMagFSP_M_CONFIG
PchSataHsioRxGen1EqBoostMagEnableFSP_M_CONFIG
PchSataHsioRxGen2EqBoostMagFSP_M_CONFIG
PchSataHsioRxGen2EqBoostMagEnableFSP_M_CONFIG
PchSataHsioRxGen3EqBoostMagFSP_M_CONFIG
PchSataHsioRxGen3EqBoostMagEnableFSP_M_CONFIG
PchSataHsioTxGen1DeEmphFSP_M_CONFIG
PchSataHsioTxGen1DeEmphEnableFSP_M_CONFIG
PchSataHsioTxGen1DownscaleAmpFSP_M_CONFIG
PchSataHsioTxGen1DownscaleAmpEnableFSP_M_CONFIG
PchSataHsioTxGen2DeEmphFSP_M_CONFIG
PchSataHsioTxGen2DeEmphEnableFSP_M_CONFIG
PchSataHsioTxGen2DownscaleAmpFSP_M_CONFIG
PchSataHsioTxGen2DownscaleAmpEnableFSP_M_CONFIG
PchSataHsioTxGen3DeEmphFSP_M_CONFIG
PchSataHsioTxGen3DeEmphEnableFSP_M_CONFIG
PchSataHsioTxGen3DownscaleAmpFSP_M_CONFIG
PchSataHsioTxGen3DownscaleAmpEnableFSP_M_CONFIG
PchSmbAlertEnableFSP_M_CONFIG
PchSmbusIoBaseFSP_M_CONFIG
PchTraceHubMemReg0SizeFSP_M_CONFIG
PchTraceHubMemReg1SizeFSP_M_CONFIG
PchTraceHubModeFSP_M_CONFIG
PcieImrEnabledFSP_M_CONFIG
PcieImrSizeFSP_M_CONFIG
PcieRpEnableMaskFSP_M_CONFIG
PdEnergyCh0Dimm0FSP_M_CONFIG
PdEnergyCh0Dimm1FSP_M_CONFIG
PdEnergyCh1Dimm0FSP_M_CONFIG
PdEnergyCh1Dimm1FSP_M_CONFIG
PeciC10ResetFSP_M_CONFIG
PeciSxResetFSP_M_CONFIG
Peg0EnableFSP_M_CONFIG
Peg0MaxLinkSpeedFSP_M_CONFIG
Peg0MaxLinkWidthFSP_M_CONFIG
Peg0PowerDownUnusedLanesFSP_M_CONFIG
Peg1EnableFSP_M_CONFIG
Peg1MaxLinkSpeedFSP_M_CONFIG
Peg1MaxLinkWidthFSP_M_CONFIG
Peg1PowerDownUnusedLanesFSP_M_CONFIG
Peg2EnableFSP_M_CONFIG
Peg2MaxLinkSpeedFSP_M_CONFIG
Peg2MaxLinkWidthFSP_M_CONFIG
Peg2PowerDownUnusedLanesFSP_M_CONFIG
Peg3EnableFSP_M_CONFIG
Peg3MaxLinkSpeedFSP_M_CONFIG
Peg3MaxLinkWidthFSP_M_CONFIG
Peg3PowerDownUnusedLanesFSP_M_CONFIG
PegDataPtrFSP_M_CONFIG
PegDisableSpreadSpectrumClockingFSP_M_CONFIG
PegGen3RxCtlePeakingFSP_M_CONFIG
PegGpioDataFSP_M_CONFIG
PegRootPortHPEFSP_M_CONFIG
PlatformDebugConsentFSP_M_CONFIG
PlatformMemorySizeFSP_M_CONFIG
PostCodeOutputPortFSP_M_CONFIG
PrimaryDisplayFSP_M_CONFIG
PrmrrSizeFSP_M_CONFIG
ProbelessTraceFSP_M_CONFIG
PsmiRegionSizeFSP_M_CONFIG
PwdwnIdleCounterFSP_M_CONFIG
RankInterleaveFSP_M_CONFIG
RaplLim1EnaFSP_M_CONFIG
RaplLim1PwrFSP_M_CONFIG
RaplLim1WindXFSP_M_CONFIG
RaplLim1WindYFSP_M_CONFIG
RaplLim2EnaFSP_M_CONFIG
RaplLim2LockFSP_M_CONFIG
RaplLim2PwrFSP_M_CONFIG
RaplLim2WindXFSP_M_CONFIG
RaplLim2WindYFSP_M_CONFIG
RaplPwrFlCh0FSP_M_CONFIG
RaplPwrFlCh1FSP_M_CONFIG
RatioFSP_M_CONFIG
RcompResistorFSP_M_CONFIG
RcompTargetFSP_M_CONFIG
RCVENC1DFSP_M_CONFIG
RCVETFSP_M_CONFIG
RDAPTFSP_M_CONFIG
RdEnergyCh0Dimm0FSP_M_CONFIG
RdEnergyCh0Dimm1FSP_M_CONFIG
RdEnergyCh1Dimm0FSP_M_CONFIG
RdEnergyCh1Dimm1FSP_M_CONFIG
RDEQTFSP_M_CONFIG
RDMPRTFSP_M_CONFIG
RDODTTFSP_M_CONFIG
RDTC1DFSP_M_CONFIG
RDTC2DFSP_M_CONFIG
RDVC2DFSP_M_CONFIG
RealtimeMemoryTimingFSP_M_CONFIG
RefClkFSP_M_CONFIG
Refresh2XFSP_M_CONFIG
RemapEnableFSP_M_CONFIG
ReservedFspmUpdFSP_M_CONFIG
ReservedFspmUpdCflFSP_M_CONFIG
ReservedPchPreMemFSP_M_CONFIG
ReservedSecurityPreMemFSP_M_CONFIG
RhActProbabilityFSP_M_CONFIG
RhPreventionFSP_M_CONFIG
RhSolutionFSP_M_CONFIG
RingDownBinFSP_M_CONFIG
RingMaxOcRatioFSP_M_CONFIG
RingPllVoltageOffsetFSP_M_CONFIG
RingVoltageAdaptiveFSP_M_CONFIG
RingVoltageModeFSP_M_CONFIG
RingVoltageOffsetFSP_M_CONFIG
RingVoltageOverrideFSP_M_CONFIG
RMCFSP_M_CONFIG
RMTFSP_M_CONFIG
RMTLoopCountFSP_M_CONFIG
RmtPerTaskFSP_M_CONFIG
RootPortIndexFSP_M_CONFIG
RsvdSmbusAddressTablePtrFSP_M_CONFIG
RTLFSP_M_CONFIG
SafeModeFSP_M_CONFIG
SaGvFSP_M_CONFIG
SaIpuEnableFSP_M_CONFIG
SaIpuImrConfigurationFSP_M_CONFIG
SaOcSupportFSP_M_CONFIG
SaPllVoltageOffsetFSP_M_CONFIG
SaPreMemProductionRsvdFSP_M_CONFIG
SaRtd3Pcie0GpioFSP_M_CONFIG
SaRtd3Pcie1GpioFSP_M_CONFIG
SaRtd3Pcie2GpioFSP_M_CONFIG
SaRtd3Pcie3GpioFSP_M_CONFIG
SaVoltageOffsetFSP_M_CONFIG
ScramblerSupportFSP_M_CONFIG
SgDelayAfterHoldResetFSP_M_CONFIG
SgDelayAfterPwrEnFSP_M_CONFIG
SinitMemorySizeFSP_M_CONFIG
SkipMpInitFSP_M_CONFIG
SkipStopPbetFSP_M_CONFIG
SmbusArpEnableFSP_M_CONFIG
SmbusEnableFSP_M_CONFIG
SmramMaskFSP_M_CONFIG
SOTFSP_M_CONFIG
SpdAddressTableFSP_M_CONFIG
SpdProfileSelectedFSP_M_CONFIG
SrefCfgEnaFSP_M_CONFIG
TATFSP_M_CONFIG
tCLFSP_M_CONFIG
tCWLFSP_M_CONFIG
tFAWFSP_M_CONFIG
TgaSizeFSP_M_CONFIG
ThrtCkeMinDefeatFSP_M_CONFIG
ThrtCkeMinDefeatLpddrFSP_M_CONFIG
ThrtCkeMinTmrFSP_M_CONFIG
ThrtCkeMinTmrLpddrFSP_M_CONFIG
TjMaxOffsetFSP_M_CONFIG
TrainTraceFSP_M_CONFIG
tRASFSP_M_CONFIG
tRCDtRPFSP_M_CONFIG
tREFIFSP_M_CONFIG
tRFCFSP_M_CONFIG
tRRDFSP_M_CONFIG
tRTPFSP_M_CONFIG
TsegSizeFSP_M_CONFIG
TsodAlarmwindowLockBitFSP_M_CONFIG
TsodCriticalEventOnlyFSP_M_CONFIG
TsodCriticaltripLockBitFSP_M_CONFIG
TsodEventModeFSP_M_CONFIG
TsodEventOutputControlFSP_M_CONFIG
TsodEventPolarityFSP_M_CONFIG
TsodManualEnableFSP_M_CONFIG
TsodShutdownModeFSP_M_CONFIG
TsodTcritMaxFSP_M_CONFIG
TsodThigMaxFSP_M_CONFIG
TvbRatioClippingFSP_M_CONFIG
TvbVoltageOptimizationFSP_M_CONFIG
tWRFSP_M_CONFIG
tWTRFSP_M_CONFIG
TxtFSP_M_CONFIG
TxtDprMemoryBaseFSP_M_CONFIG
TxtDprMemorySizeFSP_M_CONFIG
TxtHeapMemorySizeFSP_M_CONFIG
TxtImplementedFSP_M_CONFIG
TxtLcpPdBaseFSP_M_CONFIG
TxtLcpPdSizeFSP_M_CONFIG
UnusedUpdSpace0FSP_M_CONFIG
UnusedUpdSpace1FSP_M_CONFIG
UnusedUpdSpace2FSP_M_CONFIG
UnusedUpdSpace3FSP_M_CONFIG
UnusedUpdSpace4FSP_M_CONFIG
UnusedUpdSpace5FSP_M_CONFIG
UnusedUpdSpace6FSP_M_CONFIG
UserBdFSP_M_CONFIG
UserBudgetEnableFSP_M_CONFIG
UserPowerWeightsEnFSP_M_CONFIG
UserThresholdEnableFSP_M_CONFIG
VddVoltageFSP_M_CONFIG
VmxEnableFSP_M_CONFIG
WarmBudgetCh0Dimm0FSP_M_CONFIG
WarmBudgetCh0Dimm1FSP_M_CONFIG
WarmBudgetCh1Dimm0FSP_M_CONFIG
WarmBudgetCh1Dimm1FSP_M_CONFIG
WarmThresholdCh0Dimm0FSP_M_CONFIG
WarmThresholdCh0Dimm1FSP_M_CONFIG
WarmThresholdCh1Dimm0FSP_M_CONFIG
WarmThresholdCh1Dimm1FSP_M_CONFIG
WRDSEQTFSP_M_CONFIG
WRDSUDTFSP_M_CONFIG
WrEnergyCh0Dimm0FSP_M_CONFIG
WrEnergyCh0Dimm1FSP_M_CONFIG
WrEnergyCh1Dimm0FSP_M_CONFIG
WrEnergyCh1Dimm1FSP_M_CONFIG
WRSRTFSP_M_CONFIG
WRTC1DFSP_M_CONFIG
WRTC2DFSP_M_CONFIG
WRVC1DFSP_M_CONFIG
WRVC2DFSP_M_CONFIG
Generated on Wed Aug 22 2018 17:48:56 for CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide by   doxygen 1.8.10
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