Registers

Registers

Registers hold data for use by the pixel shader. Registers are fully described in the following sections.

• Register Types. Describes the four types of registers available and their purposes.
• Read Port Count. Details the restrictions on using multiple registers in a single instruction.
• Read-only, Read/Write. Describes which registers can be used for reading, writing, or both.
• Range. Details the range of the component data.

Register Types

Registers transfer data to the shader ALU and store temporary results. The table below identifies the four types of registers and the number available in each shader version.

• Constant registers contain constant data organized in four fixed-point values. Data can be loaded into a constant register using SetPixelShaderConstant or it can be defined using the def shader instruction. Constant registers are not usable by texture address instructions. The only exception is the texm3x3spec instruction, which uses a constant register to supply an eye-ray vector.

• Temporary registers are used to store intermediate results, as four fixed-point values. r0 additionally serves as the pixel shader output. The value in r0 at the end of the shader is the pixel color for the shader.

Shader pre-processing will fail CreatePixelShader on any shader that attempts to read from a temporary register that has not been written by a previous instruction. D3DXAssembleShader will fail similarly, assuming validation is enabled (do not use D3DXASM_SKIPVALIDATION).

• Texture registers
• Pixel shader version 1.1 to 1.3

For pixel shader version 1.1 to 1.3, texture registers contain texture data, organized in four fixed-point values. Texture data is loaded into a texture register when a texture is sampled. Texture sampling uses texture coordinates to look up, or sample, a color value at the specified (u,v,w,q) coordinates while taking into account the texture stage state attributes. The texture coordinate data is interpolated from the vertex texture coordinate data and is associated with a specific texture stage. There is a default one-to-one association between texture stage number and texture coordinate declaration order. By default, the first set of texture coordinates defined in the vertex format is associated with texture stage 0.

For these pixel shader versions, texture registers behave just like temporary registers when used by arithmetic instructions. For pixel shader version 1.0, texture registers are read-only to arithmetic instructions.

• Pixel shader version 1.4

For pixel shader version 1.4, texture registers (t#) contain read-only texture coordinate data. This means that the texture coordinate set and the texture stage number are independent from each other. The texture stage number (from which to sample a texture) is determined by the destination register number (r0 to r5). For the texld instruction, the texture coordinate set is determined by the source register (t0 to t5), so the texture coordinate set can be mapped to any texture stage. In addition, the source register (specifying texture coordinates) for texld can also be a temporary register (r#), in which case the contents of the temporary register are used as texture coordinates.

For this pixel shader version, texture registers contain texture coordinate data and are also available to texture addressing instructions as source parameters.

• Color registers contain per-pixel color values. The values are obtained by per-pixel iteration of the diffuse and specular color values in the vertex data. Color registers store data in four fixed-point values. For pixel shader version 1.4 shaders, color registers are available only during the second phase.

  If the shade mode is set to D3DSHADE_FLAT, the application iteration of both vertex colors (diffuse and specular) is disabled. Regardless of the shade mode, fog will still be iterated by the pipeline if pixel fog is enabled. Keep in mind that fog is applied later in the pipeline than the pixelshader.

It is common to load the v0 register with the vertex diffuse color data. It is also common to load the v1 register with the vertex specular color data.

Input color data values are clamped (saturated) to the range 0 through 1 because this is the valid input range for color registers in the pixel shader.

Pixel shaders have read only access to color registers. The contents of these registers are iterated values, but iteration is performed at much lower precision than texture coordinates.

Read Port Limit

The read port limit specifies the number of different registers of each register type that can be used as a source register in a single instruction.

For example, the color registers for almost all versions have a read port limit of two. This means that a single instruction can use a maximum of two different color registers (v0 and v1 for instance) as source registers. This example shows two color registers being used in the same instruction. As shown in the table, two color registers can be used in every version except 1.0.

mad r0, v0, v1, v1  // This is valid for versions 1.1, 1.2, 1.3, 1.4.

Any valid destination register can be used in the same instruction because read port count restrictions do not affect destination registers.

Destination registers are independent of the read port count restrictions.

For co-issued instructions, the maximum number of different registers (of the same type) that can be used across two co-issued instructions is three. This is true for all shader versions.

Read-only, Read/Write

The register types are identified according to read-only (RO) capability or read/write (RW) capability in the following table. Read-only registers can be used only as source registers in an instruction; they can never be used as a destination register.

Registers that are RW capable can be used to store intermediate results. This includes the temporary registers and texture registers for some of the shader versions.

Note  

• For pixel shader version 1.0, texture registers are RW for texture addressing instructions, but RO for arithmetic instructions.
• For pixel shader version 1.4, texture registers are RO for texture addressing instructions, and texture registers can be neither read from nor written to by arithmetic instructions. Also, because texture registers have become texture coordinate registers, having RO access is not a regression of previous functionality.

Range

Early pixel shader hardware represents data in registers using a fixed-point number. This limits precision to a maximum of approximately eight bits for the fractional part of a number. Keep this in mind when designing a shader.