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STM32756G_EVAL BSP User Manual
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stm32756g_eval_sdram.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32756g_eval_sdram.c 00004 * @author MCD Application Team 00005 * @version V1.0.0 00006 * @date 22-May-2015 00007 * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory 00008 * device mounted on STM32756G-EVAL and STM32746G-EVAL evaluation boards. 00009 @verbatim 00010 How To use this driver: 00011 ----------------------- 00012 - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted 00013 on STM32756G-EVAL evaluation board. 00014 - This driver does not need a specific component driver for the SDRAM device 00015 to be included with. 00016 00017 Driver description: 00018 ------------------ 00019 + Initialization steps: 00020 o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This 00021 function includes the MSP layer hardware resources initialization and the 00022 FMC controller configuration to interface with the external SDRAM memory. 00023 o It contains the SDRAM initialization sequence to program the SDRAM external 00024 device using the function BSP_SDRAM_Initialization_sequence(). Note that this 00025 sequence is standard for all SDRAM devices, but can include some differences 00026 from a device to another. If it is the case, the right sequence should be 00027 implemented separately. 00028 00029 + SDRAM read/write operations 00030 o SDRAM external memory can be accessed with read/write operations once it is 00031 initialized. 00032 Read/write operation can be performed with AHB access using the functions 00033 BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions 00034 BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA(). 00035 o The AHB access is performed with 32-bit width transaction, the DMA transfer 00036 configuration is fixed at single (no burst) word transfer (see the 00037 SDRAM_MspInit() static function). 00038 o User can implement his own functions for read/write access with his desired 00039 configurations. 00040 o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler() 00041 is called in IRQ handler file, to serve the generated interrupt once the DMA 00042 transfer is complete. 00043 o You can send a command to the SDRAM device in runtime using the function 00044 BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between 00045 the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure. 00046 @endverbatim 00047 ****************************************************************************** 00048 * @attention 00049 * 00050 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00051 * 00052 * Redistribution and use in source and binary forms, with or without modification, 00053 * are permitted provided that the following conditions are met: 00054 * 1. Redistributions of source code must retain the above copyright notice, 00055 * this list of conditions and the following disclaimer. 00056 * 2. Redistributions in binary form must reproduce the above copyright notice, 00057 * this list of conditions and the following disclaimer in the documentation 00058 * and/or other materials provided with the distribution. 00059 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00060 * may be used to endorse or promote products derived from this software 00061 * without specific prior written permission. 00062 * 00063 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00064 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00065 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00066 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00067 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00068 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00069 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00070 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00071 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00072 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00073 * 00074 ****************************************************************************** 00075 */ 00076 00077 /* Includes ------------------------------------------------------------------*/ 00078 #include "stm32756g_eval_sdram.h" 00079 00080 /** @addtogroup BSP 00081 * @{ 00082 */ 00083 00084 /** @addtogroup STM32756G_EVAL 00085 * @{ 00086 */ 00087 00088 /** @defgroup STM32756G_EVAL_SDRAM 00089 * @{ 00090 */ 00091 00092 /** @defgroup STM32756G_EVAL_SDRAM_Private_Types_Definitions 00093 * @{ 00094 */ 00095 /** 00096 * @} 00097 */ 00098 00099 /** @defgroup STM32756G_EVAL_SDRAM_Private_Defines 00100 * @{ 00101 */ 00102 /** 00103 * @} 00104 */ 00105 00106 /** @defgroup STM32756G_EVAL_SDRAM_Private_Macros 00107 * @{ 00108 */ 00109 /** 00110 * @} 00111 */ 00112 00113 /** @defgroup STM32756G_EVAL_SDRAM_Private_Variables 00114 * @{ 00115 */ 00116 static SDRAM_HandleTypeDef sdramHandle; 00117 static FMC_SDRAM_TimingTypeDef Timing; 00118 static FMC_SDRAM_CommandTypeDef Command; 00119 /** 00120 * @} 00121 */ 00122 00123 /** @defgroup STM32756G_EVAL_SDRAM_Private_Function_Prototypes 00124 * @{ 00125 */ 00126 /** 00127 * @} 00128 */ 00129 00130 /** @defgroup STM32756G_EVAL_SDRAM_Private_Functions 00131 * @{ 00132 */ 00133 00134 /** 00135 * @brief Initializes the SDRAM device. 00136 * @retval SDRAM status 00137 */ 00138 uint8_t BSP_SDRAM_Init(void) 00139 { 00140 static uint8_t sdramstatus = SDRAM_ERROR; 00141 /* SDRAM device configuration */ 00142 sdramHandle.Instance = FMC_SDRAM_DEVICE; 00143 00144 /* Timing configuration for 100Mhz as SDRAM clock frequency (System clock is up to 200Mhz) */ 00145 Timing.LoadToActiveDelay = 2; 00146 Timing.ExitSelfRefreshDelay = 7; 00147 Timing.SelfRefreshTime = 4; 00148 Timing.RowCycleDelay = 7; 00149 Timing.WriteRecoveryTime = 2; 00150 Timing.RPDelay = 2; 00151 Timing.RCDDelay = 2; 00152 00153 sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; 00154 sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9; 00155 sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; 00156 sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; 00157 sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; 00158 sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; 00159 sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; 00160 sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; 00161 sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; 00162 sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; 00163 00164 /* SDRAM controller initialization */ 00165 00166 BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */ 00167 00168 if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) 00169 { 00170 sdramstatus = SDRAM_ERROR; 00171 } 00172 else 00173 { 00174 sdramstatus = SDRAM_OK; 00175 } 00176 00177 /* SDRAM initialization sequence */ 00178 BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); 00179 00180 return sdramstatus; 00181 } 00182 00183 /** 00184 * @brief DeInitializes the SDRAM device. 00185 * @retval SDRAM status 00186 */ 00187 uint8_t BSP_SDRAM_DeInit(void) 00188 { 00189 static uint8_t sdramstatus = SDRAM_ERROR; 00190 /* SDRAM device de-initialization */ 00191 sdramHandle.Instance = FMC_SDRAM_DEVICE; 00192 00193 if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK) 00194 { 00195 sdramstatus = SDRAM_ERROR; 00196 } 00197 else 00198 { 00199 sdramstatus = SDRAM_OK; 00200 } 00201 00202 /* SDRAM controller de-initialization */ 00203 BSP_SDRAM_MspDeInit(&sdramHandle, NULL); 00204 00205 return sdramstatus; 00206 } 00207 00208 /** 00209 * @brief Programs the SDRAM device. 00210 * @param RefreshCount: SDRAM refresh counter value 00211 * @retval None 00212 */ 00213 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) 00214 { 00215 __IO uint32_t tmpmrd = 0; 00216 00217 /* Step 1: Configure a clock configuration enable command */ 00218 Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; 00219 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00220 Command.AutoRefreshNumber = 1; 00221 Command.ModeRegisterDefinition = 0; 00222 00223 /* Send the command */ 00224 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00225 00226 /* Step 2: Insert 100 us minimum delay */ 00227 /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */ 00228 HAL_Delay(1); 00229 00230 /* Step 3: Configure a PALL (precharge all) command */ 00231 Command.CommandMode = FMC_SDRAM_CMD_PALL; 00232 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00233 Command.AutoRefreshNumber = 1; 00234 Command.ModeRegisterDefinition = 0; 00235 00236 /* Send the command */ 00237 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00238 00239 /* Step 4: Configure an Auto Refresh command */ 00240 Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; 00241 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00242 Command.AutoRefreshNumber = 8; 00243 Command.ModeRegisterDefinition = 0; 00244 00245 /* Send the command */ 00246 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00247 00248 /* Step 5: Program the external memory mode register */ 00249 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ 00250 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ 00251 SDRAM_MODEREG_CAS_LATENCY_3 |\ 00252 SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ 00253 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; 00254 00255 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; 00256 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; 00257 Command.AutoRefreshNumber = 1; 00258 Command.ModeRegisterDefinition = tmpmrd; 00259 00260 /* Send the command */ 00261 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT); 00262 00263 /* Step 6: Set the refresh rate counter */ 00264 /* Set the device refresh rate */ 00265 HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); 00266 } 00267 00268 /** 00269 * @brief Reads an amount of data from the SDRAM memory in polling mode. 00270 * @param uwStartAddress: Read start address 00271 * @param pData: Pointer to data to be read 00272 * @param uwDataSize: Size of read data from the memory 00273 * @retval SDRAM status 00274 */ 00275 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00276 { 00277 if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00278 { 00279 return SDRAM_ERROR; 00280 } 00281 else 00282 { 00283 return SDRAM_OK; 00284 } 00285 } 00286 00287 /** 00288 * @brief Reads an amount of data from the SDRAM memory in DMA mode. 00289 * @param uwStartAddress: Read start address 00290 * @param pData: Pointer to data to be read 00291 * @param uwDataSize: Size of read data from the memory 00292 * @retval SDRAM status 00293 */ 00294 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00295 { 00296 if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00297 { 00298 return SDRAM_ERROR; 00299 } 00300 else 00301 { 00302 return SDRAM_OK; 00303 } 00304 } 00305 00306 /** 00307 * @brief Writes an amount of data to the SDRAM memory in polling mode. 00308 * @param uwStartAddress: Write start address 00309 * @param pData: Pointer to data to be written 00310 * @param uwDataSize: Size of written data from the memory 00311 * @retval SDRAM status 00312 */ 00313 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00314 { 00315 if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00316 { 00317 return SDRAM_ERROR; 00318 } 00319 else 00320 { 00321 return SDRAM_OK; 00322 } 00323 } 00324 00325 /** 00326 * @brief Writes an amount of data to the SDRAM memory in DMA mode. 00327 * @param uwStartAddress: Write start address 00328 * @param pData: Pointer to data to be written 00329 * @param uwDataSize: Size of written data from the memory 00330 * @retval SDRAM status 00331 */ 00332 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize) 00333 { 00334 if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK) 00335 { 00336 return SDRAM_ERROR; 00337 } 00338 else 00339 { 00340 return SDRAM_OK; 00341 } 00342 } 00343 00344 /** 00345 * @brief Sends command to the SDRAM bank. 00346 * @param SdramCmd: Pointer to SDRAM command structure 00347 * @retval SDRAM status 00348 */ 00349 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd) 00350 { 00351 if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK) 00352 { 00353 return SDRAM_ERROR; 00354 } 00355 else 00356 { 00357 return SDRAM_OK; 00358 } 00359 } 00360 00361 /** 00362 * @brief Handles SDRAM DMA transfer interrupt request. 00363 * @retval None 00364 */ 00365 void BSP_SDRAM_DMA_IRQHandler(void) 00366 { 00367 HAL_DMA_IRQHandler(sdramHandle.hdma); 00368 } 00369 00370 /** 00371 * @brief Initializes SDRAM MSP. 00372 * @param hsdram: SDRAM handle 00373 * @retval None 00374 */ 00375 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params) 00376 { 00377 static DMA_HandleTypeDef dma_handle; 00378 GPIO_InitTypeDef gpio_init_structure; 00379 00380 /* Enable FMC clock */ 00381 __HAL_RCC_FMC_CLK_ENABLE(); 00382 00383 /* Enable chosen DMAx clock */ 00384 __DMAx_CLK_ENABLE(); 00385 00386 /* Enable GPIOs clock */ 00387 __HAL_RCC_GPIOD_CLK_ENABLE(); 00388 __HAL_RCC_GPIOE_CLK_ENABLE(); 00389 __HAL_RCC_GPIOF_CLK_ENABLE(); 00390 __HAL_RCC_GPIOG_CLK_ENABLE(); 00391 __HAL_RCC_GPIOH_CLK_ENABLE(); 00392 __HAL_RCC_GPIOI_CLK_ENABLE(); 00393 00394 /* Common GPIO configuration */ 00395 gpio_init_structure.Mode = GPIO_MODE_AF_PP; 00396 gpio_init_structure.Pull = GPIO_PULLUP; 00397 gpio_init_structure.Speed = GPIO_SPEED_FAST; 00398 gpio_init_structure.Alternate = GPIO_AF12_FMC; 00399 00400 /* GPIOD configuration */ 00401 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\ 00402 GPIO_PIN_14 | GPIO_PIN_15; 00403 00404 00405 HAL_GPIO_Init(GPIOD, &gpio_init_structure); 00406 00407 /* GPIOE configuration */ 00408 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ 00409 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ 00410 GPIO_PIN_15; 00411 00412 HAL_GPIO_Init(GPIOE, &gpio_init_structure); 00413 00414 /* GPIOF configuration */ 00415 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ 00416 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ 00417 GPIO_PIN_15; 00418 00419 HAL_GPIO_Init(GPIOF, &gpio_init_structure); 00420 00421 /* GPIOG configuration */ 00422 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ 00423 GPIO_PIN_15; 00424 HAL_GPIO_Init(GPIOG, &gpio_init_structure); 00425 00426 /* GPIOH configuration */ 00427 gpio_init_structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_9 |\ 00428 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ 00429 GPIO_PIN_15; 00430 HAL_GPIO_Init(GPIOH, &gpio_init_structure); 00431 00432 /* GPIOI configuration */ 00433 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\ 00434 GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10; 00435 HAL_GPIO_Init(GPIOI, &gpio_init_structure); 00436 00437 /* Configure common DMA parameters */ 00438 dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; 00439 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; 00440 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; 00441 dma_handle.Init.MemInc = DMA_MINC_ENABLE; 00442 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; 00443 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; 00444 dma_handle.Init.Mode = DMA_NORMAL; 00445 dma_handle.Init.Priority = DMA_PRIORITY_HIGH; 00446 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; 00447 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; 00448 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; 00449 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; 00450 00451 dma_handle.Instance = SDRAM_DMAx_STREAM; 00452 00453 /* Associate the DMA handle */ 00454 __HAL_LINKDMA(hsdram, hdma, dma_handle); 00455 00456 /* Deinitialize the stream for new transfer */ 00457 HAL_DMA_DeInit(&dma_handle); 00458 00459 /* Configure the DMA stream */ 00460 HAL_DMA_Init(&dma_handle); 00461 00462 /* NVIC configuration for DMA transfer complete interrupt */ 00463 HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); 00464 HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); 00465 } 00466 00467 /** 00468 * @brief DeInitializes SDRAM MSP. 00469 * @param hsdram: SDRAM handle 00470 * @retval None 00471 */ 00472 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params) 00473 { 00474 static DMA_HandleTypeDef dma_handle; 00475 00476 /* Disable NVIC configuration for DMA interrupt */ 00477 HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn); 00478 00479 /* Deinitialize the stream for new transfer */ 00480 dma_handle.Instance = SDRAM_DMAx_STREAM; 00481 HAL_DMA_DeInit(&dma_handle); 00482 00483 /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications 00484 by surcharging this __weak function */ 00485 } 00486 00487 /** 00488 * @} 00489 */ 00490 00491 /** 00492 * @} 00493 */ 00494 00495 /** 00496 * @} 00497 */ 00498 00499 /** 00500 * @} 00501 */ 00502 00503 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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