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STM32412G-Discovery BSP User Manual
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stm32412g_discovery_qspi.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32412g_discovery_qspi.c 00004 * @author MCD Application Team 00005 * @version V2.0.0 00006 * @date 27-January-2017 00007 * @brief This file includes a standard driver for the N25Q128A QSPI 00008 * memory mounted on STM32412G-DISCOVERY board. 00009 @verbatim 00010 ============================================================================== 00011 ##### How to use this driver ##### 00012 ============================================================================== 00013 [..] 00014 (#) This driver is used to drive the N25Q128A QSPI external 00015 memory mounted on STM32412G-DISCOVERY board. 00016 00017 (#) This driver need a specific component driver (N25Q128A) to be included with. 00018 00019 (#) Initialization steps: 00020 (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This 00021 function includes the MSP layer hardware resources initialization and the 00022 QSPI interface with the external memory. 00023 00024 (#) QSPI memory operations 00025 (++) QSPI memory can be accessed with read/write operations once it is 00026 initialized. 00027 Read/write operation can be performed with AHB access using the functions 00028 BSP_QSPI_Read()/BSP_QSPI_Write(). 00029 (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory. 00030 (see the QSPI memory data sheet) 00031 (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by 00032 specifying the block address. You can perform an erase operation of the whole 00033 chip by calling the function BSP_QSPI_Erase_Chip(). 00034 (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory. 00035 (see the QSPI memory data sheet) 00036 @endverbatim 00037 ****************************************************************************** 00038 * @attention 00039 * 00040 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00041 * 00042 * Redistribution and use in source and binary forms, with or without modification, 00043 * are permitted provided that the following conditions are met: 00044 * 1. Redistributions of source code must retain the above copyright notice, 00045 * this list of conditions and the following disclaimer. 00046 * 2. Redistributions in binary form must reproduce the above copyright notice, 00047 * this list of conditions and the following disclaimer in the documentation 00048 * and/or other materials provided with the distribution. 00049 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00050 * may be used to endorse or promote products derived from this software 00051 * without specific prior written permission. 00052 * 00053 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00054 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00055 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00056 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00057 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00058 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00059 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00060 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00061 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00062 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00063 * 00064 ****************************************************************************** 00065 */ 00066 00067 /* Includes ------------------------------------------------------------------*/ 00068 #include "stm32412g_discovery_qspi.h" 00069 00070 /** @addtogroup BSP 00071 * @{ 00072 */ 00073 00074 /** @addtogroup STM32412G_DISCOVERY 00075 * @{ 00076 */ 00077 00078 /** @defgroup STM32412G_DISCOVERY_QSPI STM32412G-DISCOVERY QSPI 00079 * @{ 00080 */ 00081 00082 /** @defgroup STM32412G_DISCOVERY_QSPI_Private_Variables STM32412G Discovery QSPI Private Variables 00083 * @{ 00084 */ 00085 QSPI_HandleTypeDef QSPIHandle; 00086 00087 /** 00088 * @} 00089 */ 00090 00091 /** @defgroup STM32412G_DISCOVERY_QSPI_Private_FunctionPrototypes STM32412G Discovery QSPI Private FunctionPrototypes 00092 * @{ 00093 */ 00094 static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi); 00095 static uint8_t QSPI_DummyCyclesCfg (QSPI_HandleTypeDef *hqspi); 00096 static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi); 00097 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 00098 00099 /** 00100 * @} 00101 */ 00102 00103 /** @defgroup STM32412G_DISCOVERY_QSPI_Private_Functions STM32412G Discovery QSPI Private Functions 00104 * @{ 00105 */ 00106 00107 /** 00108 * @brief Initializes the QSPI interface. 00109 * @retval QSPI memory status 00110 */ 00111 uint8_t BSP_QSPI_Init(void) 00112 { 00113 QSPIHandle.Instance = QUADSPI; 00114 00115 /* Call the DeInit function to reset the driver */ 00116 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK) 00117 { 00118 return QSPI_ERROR; 00119 } 00120 00121 /* System level initialization */ 00122 BSP_QSPI_MspInit(&QSPIHandle, NULL); 00123 00124 /* QSPI initialization */ 00125 QSPIHandle.Init.ClockPrescaler = 0; /* QSPI freq = 100 MHz/(0+1) = 100 Mhz */ 00126 QSPIHandle.Init.FifoThreshold = 4; 00127 QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; 00128 QSPIHandle.Init.FlashSize = POSITION_VAL(N25Q128A_FLASH_SIZE) - 1; 00129 QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE; /* Min 50ns for nonRead command */ 00130 QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0; 00131 QSPIHandle.Init.FlashID = QSPI_FLASH_ID_1; 00132 QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_DISABLE; 00133 00134 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK) 00135 { 00136 return QSPI_ERROR; 00137 } 00138 00139 /* QSPI memory reset */ 00140 if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK) 00141 { 00142 return QSPI_NOT_SUPPORTED; 00143 } 00144 00145 /* Configuration of the dummy cycles on QSPI memory side */ 00146 if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK) 00147 { 00148 return QSPI_NOT_SUPPORTED; 00149 } 00150 00151 return QSPI_OK; 00152 } 00153 00154 /** 00155 * @brief De-Initializes the QSPI interface. 00156 * @retval QSPI memory status 00157 */ 00158 uint8_t BSP_QSPI_DeInit(void) 00159 { 00160 QSPIHandle.Instance = QUADSPI; 00161 00162 /* Call the DeInit function to reset the driver */ 00163 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK) 00164 { 00165 return QSPI_ERROR; 00166 } 00167 00168 /* System level De-initialization */ 00169 BSP_QSPI_MspDeInit(&QSPIHandle, NULL); 00170 00171 return QSPI_OK; 00172 } 00173 00174 /** 00175 * @brief Reads an amount of data from the QSPI memory. 00176 * @param pData: Pointer to data to be read 00177 * @param ReadAddr: Read start address 00178 * @param Size: Size of data to read 00179 * @retval QSPI memory status 00180 */ 00181 uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size) 00182 { 00183 QSPI_CommandTypeDef s_command; 00184 00185 /* Initialize the read command */ 00186 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; 00187 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD; 00188 s_command.AddressMode = QSPI_ADDRESS_4_LINES; 00189 s_command.AddressSize = QSPI_ADDRESS_24_BITS; 00190 s_command.Address = ReadAddr; 00191 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; 00192 s_command.DataMode = QSPI_DATA_4_LINES; 00193 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD; 00194 s_command.NbData = Size; 00195 s_command.DdrMode = QSPI_DDR_MODE_DISABLE; 00196 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 00197 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 00198 00199 /* Configure the command */ 00200 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00201 { 00202 return QSPI_ERROR; 00203 } 00204 00205 /* Set S# timing for Read command: Min 20ns for N25Q128A memory */ 00206 MODIFY_REG(QSPIHandle.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_2_CYCLE); 00207 00208 /* Reception of the data */ 00209 if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00210 { 00211 return QSPI_ERROR; 00212 } 00213 00214 /* Restore S# timing for nonRead commands */ 00215 MODIFY_REG(QSPIHandle.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_5_CYCLE); 00216 00217 return QSPI_OK; 00218 } 00219 00220 /** 00221 * @brief Writes an amount of data to the QSPI memory. 00222 * @param pData: Pointer to data to be written 00223 * @param WriteAddr: Write start address 00224 * @param Size: Size of data to write 00225 * @retval QSPI memory status 00226 */ 00227 uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size) 00228 { 00229 QSPI_CommandTypeDef s_command; 00230 uint32_t end_addr, current_size, current_addr; 00231 00232 /* Calculation of the size between the write address and the end of the page */ 00233 current_size = N25Q128A_PAGE_SIZE - (WriteAddr % N25Q128A_PAGE_SIZE); 00234 00235 /* Check if the size of the data is less than the remaining place in the page */ 00236 if (current_size > Size) 00237 { 00238 current_size = Size; 00239 } 00240 00241 /* Initialize the adress variables */ 00242 current_addr = WriteAddr; 00243 end_addr = WriteAddr + Size; 00244 00245 /* Initialize the program command */ 00246 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; 00247 s_command.Instruction = EXT_QUAD_IN_FAST_PROG_CMD; 00248 s_command.AddressMode = QSPI_ADDRESS_4_LINES; 00249 s_command.AddressSize = QSPI_ADDRESS_24_BITS; 00250 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; 00251 s_command.DataMode = QSPI_DATA_4_LINES; 00252 s_command.DummyCycles = 0; 00253 s_command.DdrMode = QSPI_DDR_MODE_DISABLE; 00254 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 00255 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 00256 00257 /* Perform the write page by page */ 00258 do 00259 { 00260 s_command.Address = current_addr; 00261 s_command.NbData = current_size; 00262 00263 /* Enable write operations */ 00264 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) 00265 { 00266 return QSPI_ERROR; 00267 } 00268 00269 /* Configure the command */ 00270 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00271 { 00272 return QSPI_ERROR; 00273 } 00274 00275 /* Transmission of the data */ 00276 if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00277 { 00278 return QSPI_ERROR; 00279 } 00280 00281 /* Configure automatic polling mode to wait for end of program */ 00282 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) 00283 { 00284 return QSPI_ERROR; 00285 } 00286 00287 /* Update the address and size variables for next page programming */ 00288 current_addr += current_size; 00289 pData += current_size; 00290 current_size = ((current_addr + N25Q128A_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : N25Q128A_PAGE_SIZE; 00291 } while (current_addr < end_addr); 00292 00293 return QSPI_OK; 00294 } 00295 00296 /** 00297 * @brief Erases the specified block of the QSPI memory. 00298 * @param BlockAddress: Block address to erase 00299 * @retval QSPI memory status 00300 */ 00301 uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress) 00302 { 00303 QSPI_CommandTypeDef s_command; 00304 00305 /* Initialize the erase command */ 00306 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; 00307 s_command.Instruction = SUBSECTOR_ERASE_CMD; 00308 s_command.AddressMode = QSPI_ADDRESS_1_LINE; 00309 s_command.AddressSize = QSPI_ADDRESS_24_BITS; 00310 s_command.Address = BlockAddress; 00311 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; 00312 s_command.DataMode = QSPI_DATA_NONE; 00313 s_command.DummyCycles = 0; 00314 s_command.DdrMode = QSPI_DDR_MODE_DISABLE; 00315 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 00316 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 00317 00318 /* Enable write operations */ 00319 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) 00320 { 00321 return QSPI_ERROR; 00322 } 00323 00324 /* Send the command */ 00325 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00326 { 00327 return QSPI_ERROR; 00328 } 00329 00330 /* Configure automatic polling mode to wait for end of erase */ 00331 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK) 00332 { 00333 return QSPI_ERROR; 00334 } 00335 00336 return QSPI_OK; 00337 } 00338 00339 /** 00340 * @brief Erases the entire QSPI memory. 00341 * @retval QSPI memory status 00342 */ 00343 uint8_t BSP_QSPI_Erase_Chip(void) 00344 { 00345 QSPI_CommandTypeDef s_command; 00346 00347 /* Initialize the erase command */ 00348 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; 00349 s_command.Instruction = BULK_ERASE_CMD; 00350 s_command.AddressMode = QSPI_ADDRESS_NONE; 00351 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; 00352 s_command.DataMode = QSPI_DATA_NONE; 00353 s_command.DummyCycles = 0; 00354 s_command.DdrMode = QSPI_DDR_MODE_DISABLE; 00355 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 00356 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 00357 00358 /* Enable write operations */ 00359 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) 00360 { 00361 return QSPI_ERROR; 00362 } 00363 00364 /* Send the command */ 00365 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00366 { 00367 return QSPI_ERROR; 00368 } 00369 00370 /* Configure automatic polling mode to wait for end of erase */ 00371 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_BULK_ERASE_MAX_TIME) != QSPI_OK) 00372 { 00373 return QSPI_ERROR; 00374 } 00375 00376 return QSPI_OK; 00377 } 00378 00379 /** 00380 * @brief Reads current status of the QSPI memory. 00381 * @retval QSPI memory status 00382 */ 00383 uint8_t BSP_QSPI_GetStatus(void) 00384 { 00385 QSPI_CommandTypeDef s_command; 00386 uint8_t reg; 00387 00388 /* Initialize the read flag status register command */ 00389 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; 00390 s_command.Instruction = READ_FLAG_STATUS_REG_CMD; 00391 s_command.AddressMode = QSPI_ADDRESS_NONE; 00392 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; 00393 s_command.DataMode = QSPI_DATA_1_LINE; 00394 s_command.DummyCycles = 0; 00395 s_command.NbData = 1; 00396 s_command.DdrMode = QSPI_DDR_MODE_DISABLE; 00397 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 00398 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 00399 00400 /* Configure the command */ 00401 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00402 { 00403 return QSPI_ERROR; 00404 } 00405 00406 /* Reception of the data */ 00407 if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00408 { 00409 return QSPI_ERROR; 00410 } 00411 00412 /* Check the value of the register */ 00413 if ((reg & (N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR)) != 0) 00414 { 00415 return QSPI_ERROR; 00416 } 00417 else if ((reg & (N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS)) != 0) 00418 { 00419 return QSPI_SUSPENDED; 00420 } 00421 else if ((reg & N25Q128A_FSR_READY) != 0) 00422 { 00423 return QSPI_OK; 00424 } 00425 else 00426 { 00427 return QSPI_BUSY; 00428 } 00429 } 00430 00431 /** 00432 * @brief Return the configuration of the QSPI memory. 00433 * @param pInfo: pointer on the configuration structure 00434 * @retval QSPI memory status 00435 */ 00436 uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo) 00437 { 00438 /* Configure the structure with the memory configuration */ 00439 pInfo->FlashSize = N25Q128A_FLASH_SIZE; 00440 pInfo->EraseSectorSize = N25Q128A_SUBSECTOR_SIZE; 00441 pInfo->EraseSectorsNumber = (N25Q128A_FLASH_SIZE/N25Q128A_SUBSECTOR_SIZE); 00442 pInfo->ProgPageSize = N25Q128A_PAGE_SIZE; 00443 pInfo->ProgPagesNumber = (N25Q128A_FLASH_SIZE/N25Q128A_PAGE_SIZE); 00444 00445 return QSPI_OK; 00446 } 00447 00448 /** 00449 * @brief Configure the QSPI in memory-mapped mode 00450 * @retval QSPI memory status 00451 */ 00452 uint8_t BSP_QSPI_EnableMemoryMappedMode(void) 00453 { 00454 QSPI_CommandTypeDef s_command; 00455 QSPI_MemoryMappedTypeDef s_mem_mapped_cfg; 00456 00457 /* Configure the command for the read instruction */ 00458 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; 00459 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD; 00460 s_command.AddressMode = QSPI_ADDRESS_4_LINES; 00461 s_command.AddressSize = QSPI_ADDRESS_24_BITS; 00462 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; 00463 s_command.DataMode = QSPI_DATA_4_LINES; 00464 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD; 00465 s_command.DdrMode = QSPI_DDR_MODE_DISABLE; 00466 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 00467 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 00468 00469 /* Configure the memory mapped mode */ 00470 s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_DISABLE; 00471 00472 if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK) 00473 { 00474 return QSPI_ERROR; 00475 } 00476 00477 return QSPI_OK; 00478 } 00479 00480 00481 /** 00482 * @brief QSPI MSP Initialization 00483 * This function configures the hardware resources used in this example: 00484 * - Peripheral's clock enable 00485 * - Peripheral's GPIO Configuration 00486 * - NVIC configuration for QSPI interrupt 00487 * @param hqspi: QSPI handle 00488 * @param Params : pointer on additional configuration parameters, can be NULL. 00489 */ 00490 __weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params) 00491 { 00492 GPIO_InitTypeDef gpio_init_structure; 00493 00494 /*##-1- Enable peripherals and GPIO Clocks #################################*/ 00495 /* Enable the QuadSPI memory interface clock */ 00496 QSPI_CLK_ENABLE(); 00497 /* Reset the QuadSPI memory interface */ 00498 QSPI_FORCE_RESET(); 00499 QSPI_RELEASE_RESET(); 00500 /* Enable GPIO clocks */ 00501 QSPI_CS_GPIO_CLK_ENABLE(); 00502 QSPI_CLK_GPIO_CLK_ENABLE(); 00503 QSPI_Dx_GPIO_CLK_ENABLE(); 00504 00505 /*##-2- Configure peripheral GPIO ##########################################*/ 00506 /* QSPI CS GPIO pin configuration */ 00507 gpio_init_structure.Pin = QSPI_CS_PIN; 00508 gpio_init_structure.Mode = GPIO_MODE_AF_PP; 00509 gpio_init_structure.Pull = GPIO_PULLUP; 00510 gpio_init_structure.Speed = GPIO_SPEED_HIGH; 00511 gpio_init_structure.Alternate = GPIO_AF10_QSPI; 00512 HAL_GPIO_Init(QSPI_CS_GPIO_PORT, &gpio_init_structure); 00513 00514 /* QSPI CLK GPIO pin configuration */ 00515 gpio_init_structure.Pin = QSPI_CLK_PIN; 00516 gpio_init_structure.Pull = GPIO_NOPULL; 00517 gpio_init_structure.Alternate = GPIO_AF9_QSPI; 00518 HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure); 00519 00520 /* QSPI D0 GPIO pin configuration */ 00521 gpio_init_structure.Pin = QSPI_D0_PIN; 00522 gpio_init_structure.Alternate = GPIO_AF10_QSPI; 00523 HAL_GPIO_Init(QSPI_D0_GPIO_PORT, &gpio_init_structure); 00524 00525 /* QSPI D1 GPIO pin configuration */ 00526 gpio_init_structure.Pin = QSPI_D1_PIN; 00527 gpio_init_structure.Alternate = GPIO_AF10_QSPI; 00528 HAL_GPIO_Init(QSPI_D1_GPIO_PORT, &gpio_init_structure); 00529 00530 /* QSPI D2 GPIO pin configuration */ 00531 gpio_init_structure.Pin = QSPI_D2_PIN; 00532 gpio_init_structure.Alternate = GPIO_AF9_QSPI; 00533 HAL_GPIO_Init(QSPI_D2_GPIO_PORT, &gpio_init_structure); 00534 00535 /* QSPI D3 GPIO pin configuration */ 00536 gpio_init_structure.Pin = QSPI_D3_PIN; 00537 gpio_init_structure.Alternate = GPIO_AF9_QSPI; 00538 HAL_GPIO_Init(QSPI_D3_GPIO_PORT, &gpio_init_structure); 00539 00540 /*##-3- Configure the NVIC for QSPI #########################################*/ 00541 /* NVIC configuration for QSPI interrupt */ 00542 HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0x00); 00543 HAL_NVIC_EnableIRQ(QUADSPI_IRQn); 00544 } 00545 00546 00547 /** 00548 * @brief QSPI MSP De-Initialization 00549 * This function frees the hardware resources used in this example: 00550 * - Disable the Peripheral's clock 00551 * - Revert GPIO and NVIC configuration to their default state 00552 * @param hqspi: QSPI handle 00553 * @param Params : pointer on additional configuration parameters, can be NULL. 00554 */ 00555 __weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params) 00556 { 00557 /*##-1- Disable the NVIC for QSPI ###########################################*/ 00558 HAL_NVIC_DisableIRQ(QUADSPI_IRQn); 00559 00560 /*##-2- Disable peripherals and GPIO Clocks ################################*/ 00561 /* De-Configure QSPI pins */ 00562 HAL_GPIO_DeInit(QSPI_CS_GPIO_PORT, QSPI_CS_PIN); 00563 HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN); 00564 HAL_GPIO_DeInit(QSPI_D0_GPIO_PORT, QSPI_D0_PIN); 00565 HAL_GPIO_DeInit(QSPI_D1_GPIO_PORT, QSPI_D1_PIN); 00566 HAL_GPIO_DeInit(QSPI_D2_GPIO_PORT, QSPI_D2_PIN); 00567 HAL_GPIO_DeInit(QSPI_D3_GPIO_PORT, QSPI_D3_PIN); 00568 00569 /*##-3- Reset peripherals ##################################################*/ 00570 /* Reset the QuadSPI memory interface */ 00571 QSPI_FORCE_RESET(); 00572 QSPI_RELEASE_RESET(); 00573 00574 /* Disable the QuadSPI memory interface clock */ 00575 QSPI_CLK_DISABLE(); 00576 } 00577 00578 /*********************** Static functions *************************************/ 00579 /** 00580 * @brief This function reset the QSPI memory. 00581 * @param hqspi: QSPI handle 00582 */ 00583 static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi) 00584 { 00585 QSPI_CommandTypeDef s_command; 00586 00587 /* Initialize the reset enable command */ 00588 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; 00589 s_command.Instruction = RESET_ENABLE_CMD; 00590 s_command.AddressMode = QSPI_ADDRESS_NONE; 00591 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; 00592 s_command.DataMode = QSPI_DATA_NONE; 00593 s_command.DummyCycles = 0; 00594 s_command.DdrMode = QSPI_DDR_MODE_DISABLE; 00595 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 00596 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 00597 00598 /* Send the command */ 00599 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00600 { 00601 return QSPI_ERROR; 00602 } 00603 00604 /* Send the reset memory command */ 00605 s_command.Instruction = RESET_MEMORY_CMD; 00606 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00607 { 00608 return QSPI_ERROR; 00609 } 00610 00611 /* Configure automatic polling mode to wait the memory is ready */ 00612 if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) 00613 { 00614 return QSPI_ERROR; 00615 } 00616 00617 return QSPI_OK; 00618 } 00619 00620 /** 00621 * @brief This function configure the dummy cycles on memory side. 00622 * @param hqspi: QSPI handle 00623 */ 00624 static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi) 00625 { 00626 QSPI_CommandTypeDef s_command; 00627 uint8_t reg; 00628 00629 /* Initialize the read volatile configuration register command */ 00630 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; 00631 s_command.Instruction = READ_VOL_CFG_REG_CMD; 00632 s_command.AddressMode = QSPI_ADDRESS_NONE; 00633 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; 00634 s_command.DataMode = QSPI_DATA_1_LINE; 00635 s_command.DummyCycles = 0; 00636 s_command.NbData = 1; 00637 s_command.DdrMode = QSPI_DDR_MODE_DISABLE; 00638 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 00639 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 00640 00641 /* Configure the command */ 00642 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00643 { 00644 return QSPI_ERROR; 00645 } 00646 00647 /* Reception of the data */ 00648 if (HAL_QSPI_Receive(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00649 { 00650 return QSPI_ERROR; 00651 } 00652 00653 /* Enable write operations */ 00654 if (QSPI_WriteEnable(hqspi) != QSPI_OK) 00655 { 00656 return QSPI_ERROR; 00657 } 00658 00659 /* Update volatile configuration register (with new dummy cycles) */ 00660 s_command.Instruction = WRITE_VOL_CFG_REG_CMD; 00661 MODIFY_REG(reg, N25Q128A_VCR_NB_DUMMY, (N25Q128A_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(N25Q128A_VCR_NB_DUMMY))); 00662 00663 /* Configure the write volatile configuration register command */ 00664 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00665 { 00666 return QSPI_ERROR; 00667 } 00668 00669 /* Transmission of the data */ 00670 if (HAL_QSPI_Transmit(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00671 { 00672 return QSPI_ERROR; 00673 } 00674 00675 return QSPI_OK; 00676 } 00677 00678 /** 00679 * @brief This function send a Write Enable and wait it is effective. 00680 * @param hqspi: QSPI handle 00681 */ 00682 static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi) 00683 { 00684 QSPI_CommandTypeDef s_command; 00685 QSPI_AutoPollingTypeDef s_config; 00686 00687 /* Enable write operations */ 00688 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; 00689 s_command.Instruction = WRITE_ENABLE_CMD; 00690 s_command.AddressMode = QSPI_ADDRESS_NONE; 00691 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; 00692 s_command.DataMode = QSPI_DATA_NONE; 00693 s_command.DummyCycles = 0; 00694 s_command.DdrMode = QSPI_DDR_MODE_DISABLE; 00695 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 00696 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 00697 00698 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00699 { 00700 return QSPI_ERROR; 00701 } 00702 00703 /* Configure automatic polling mode to wait for write enabling */ 00704 s_config.Match = N25Q128A_SR_WREN; 00705 s_config.Mask = N25Q128A_SR_WREN; 00706 s_config.MatchMode = QSPI_MATCH_MODE_AND; 00707 s_config.StatusBytesSize = 1; 00708 s_config.Interval = 0x10; 00709 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; 00710 00711 s_command.Instruction = READ_STATUS_REG_CMD; 00712 s_command.DataMode = QSPI_DATA_1_LINE; 00713 00714 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) 00715 { 00716 return QSPI_ERROR; 00717 } 00718 00719 return QSPI_OK; 00720 } 00721 00722 /** 00723 * @brief This function read the SR of the memory and wait the EOP. 00724 * @param hqspi: QSPI handle 00725 * @param Timeout 00726 */ 00727 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) 00728 { 00729 QSPI_CommandTypeDef s_command; 00730 QSPI_AutoPollingTypeDef s_config; 00731 00732 /* Configure automatic polling mode to wait for memory ready */ 00733 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; 00734 s_command.Instruction = READ_STATUS_REG_CMD; 00735 s_command.AddressMode = QSPI_ADDRESS_NONE; 00736 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; 00737 s_command.DataMode = QSPI_DATA_1_LINE; 00738 s_command.DummyCycles = 0; 00739 s_command.DdrMode = QSPI_DDR_MODE_DISABLE; 00740 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; 00741 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; 00742 00743 s_config.Match = 0; 00744 s_config.Mask = N25Q128A_SR_WIP; 00745 s_config.MatchMode = QSPI_MATCH_MODE_AND; 00746 s_config.StatusBytesSize = 1; 00747 s_config.Interval = 0x10; 00748 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; 00749 00750 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK) 00751 { 00752 return QSPI_ERROR; 00753 } 00754 00755 return QSPI_OK; 00756 } 00757 /** 00758 * @} 00759 */ 00760 00761 /** 00762 * @} 00763 */ 00764 00765 /** 00766 * @} 00767 */ 00768 00769 /** 00770 * @} 00771 */ 00772 00773 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 00774
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