NI PXI-7842R Reference
R Series Reconfigurable I/O Module (AI, AO, DIO)
8 AI channels, 8 AO channels, 96 DIO lines, LX50, 200 kS/s AI Sample Rate
FPGA I/O Node
You can use an FPGA I/O Node, configured for reading and writing, with this device.
Note FPGA I/O Nodes cannot be configured to write to R Series digital output channels as both ports and lines. You must write digital outputs as either a port or a line. |
Terminals in Software
You can select the following terminals for this device.
Terminal | Description | ||
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AIx | Analog input channel x, where x is the channel number. Use an FPGA I/O Node configured for reading to access this channel. | ||
AOx | Analog output channel x, where x is the channel number. Use an FPGA I/O Node configured for writing to access this channel. | ||
Connectorx/DIOy | Digital input/output channel y on connector x, where y is the channel number and x is the connector number. Use an FPGA I/O Node configured for reading or writing, or use the Set Data Output or Set Data Enable method to access this channel. | ||
Connectorx/DIOPORTy | Digital input/output port y on connector x, where y is the port number and x is the connector number. A port is made up of eight digital channels. Use an FPGA I/O Node configured for reading or writing, or use the Set Data Output or Set Data Enable method to access this port. | ||
PXI/CLK10 | 10 MHz clock in the PXI chassis that you can use to synchronize multiple PXI modules. Use an FPGA I/O Node configured for reading to access this channel.
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PXI/STAR | Star trigger bus. Use an FPGA I/O Node configured for reading or writing, or use the Set Data Output or Set Data Enable method to access this channel.
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PXI/TRIGx | Trigger channel x, where x is the channel number. Use an FPGA I/O Node configured for reading or writing, or use the Set Data Output or Set Data Enable method to access this channel. Follow the guidelines for using PXI triggers with the LabVIEW FPGA Module. |
Arbitration
This device supports arbitration. Configure the arbitration settings for the channels of this device in the FPGA I/O Properties dialog box for the FPGA I/O item you are using.
I/O Methods
Use the FPGA I/O Method Node to invoke methods. You can use the following methods with this device.
Note FPGA I/O Method Nodes cannot be configured to write to R Series digital output channels as both ports and lines. You must write digital outputs as either a port or a line. |
Method | Description |
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Set Output Data | Refer to the FPGA I/O Method Node (FPGA Module) topic for a description of this method. |
Set Output Enable | Refer to the FPGA I/O Method Node (FPGA Module) topic for a description of this method. |
Wait on Any Edge | Pauses the execution of the I/O Method Node until the next falling or rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Any Edge method waits for the next falling or rising edge. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out. |
Wait on Falling Edge | Pauses the execution of the I/O Method Node until the next falling edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Falling Edge method waits for the next falling edge. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out. |
Wait on High Level | Pauses the execution of the I/O Method Node until the digital signal is high. The Timeout input specifies in FPGA clock ticks how long the Wait on High Level method waits for the next high level. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out. |
Wait on Low Level | Pauses the execution of the I/O Method Node until the digital signal is low. The Timeout input specifies in FPGA clock ticks how long the Wait on Low Level method waits for the next low level. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out. |
Wait on Rising Edge | Pauses the execution of the I/O Method Node until the next rising edge of the digital signal. The Timeout input specifies in FPGA clock ticks how long the Wait on Rising Edge method waits for the next rising edge. A value of 0 causes the method to timeout immediately, a negative value causes the method to wait indefinitely, and a positive value causes the method to wait for that number of clock ticks before timing out. |
I/O Properties
This device does not support any properties.
Single-Cycle Timed Loop
This device supports the Single-Cycle Timed Loop for digital I/O only.