SPI_MASTER: SPI_MASTER.h Source File

SPI_MASTER

previous page next page

SPI_MASTER

Home

Code

88 #ifndef SPI_MASTER_H

89 #define SPI_MASTER_H

90 /***********************************************************************************************************************

91 * HEADER FILES

92 **********************************************************************************************************************/

93 #include <xmc_gpio.h>

94 #include <xmc_scu.h>

95 #include <xmc_spi.h>

96 #include <DAVE_Common.h>

97 #include "spi_master_conf.h"

99 #if((SPI_MASTER_DMA_TRANSMIT_MODE == 1U) || (SPI_MASTER_DMA_RECEIVE_MODE == 1U))

100 #include "./GLOBAL_DMA/global_dma.h"

101 #endif

102

103 /**********************************************************************************************************************

104 * MACROS

105 **********************************************************************************************************************/

106 #if (!((XMC_LIB_MAJOR_VERSION == 2U) && \

107 (XMC_LIB_MINOR_VERSION >= 1U) && \

108 (XMC_LIB_PATCH_VERSION >= 6U)))

109 #error "SPI_MASTER requires XMC Peripheral Library v2.1.6 or higher"

110 #endif

111

112

113 /*

114 * @brief Represents the maximum data size for DMA transaction*/

115 #define SPI_MASTER_DMA_MAXCOUNT (4095U)

116 /**********************************************************************************************************************

117 * ENUMS

118 **********************************************************************************************************************/

126 typedef enum SPI_MASTER_STATUS

127 {

128 SPI_MASTER_STATUS_SUCCESS = 0U,

129 SPI_MASTER_STATUS_FAILURE,

130 SPI_MASTER_STATUS_BUSY,

131 SPI_MASTER_STATUS_BUFFER_INVALID,

132 SPI_MASTER_STATUS_MODE_MISMATCH

136 } SPI_MASTER_STATUS_t;

137

141 typedef enum SPI_MASTER_SR_ID

142 {

143 SPI_MASTER_SR_ID_0 = 0U,

144 SPI_MASTER_SR_ID_1,

145 SPI_MASTER_SR_ID_2,

146 SPI_MASTER_SR_ID_3,

147 SPI_MASTER_SR_ID_4,

148 SPI_MASTER_SR_ID_5

149 } SPI_MASTER_SR_ID_t;

150

154 typedef enum SPI_MASTER_SS_SIGNAL

155 {

156 SPI_MASTER_SS_SIGNAL_0 = 0U,

157 SPI_MASTER_SS_SIGNAL_1,

158 SPI_MASTER_SS_SIGNAL_2,

159 SPI_MASTER_SS_SIGNAL_3,

160 SPI_MASTER_SS_SIGNAL_4,

161 SPI_MASTER_SS_SIGNAL_5,

162 SPI_MASTER_SS_SIGNAL_6,

163 SPI_MASTER_SS_SIGNAL_7

164 } SPI_MASTER_SS_SIGNAL_t;

165

169 typedef enum SPI_MASTER_INPUT

170 {

171 SPI_MASTER_INPUT_A = 0U,

172 SPI_MASTER_INPUT_B,

173 SPI_MASTER_INPUT_C,

174 SPI_MASTER_INPUT_D,

175 SPI_MASTER_INPUT_E,

176 SPI_MASTER_INPUT_F,

177 SPI_MASTER_INPUT_G,

178 SPI_MASTER_INPUT_INVALID

179 } SPI_MASTER_INPUT_t;

180

184 typedef enum SPI_MASTER_TRANSFER_MODE

185 {

186 SPI_MASTER_TRANSFER_MODE_INTERRUPT,

187 SPI_MASTER_TRANSFER_MODE_DMA,

188 SPI_MASTER_TRANSFER_MODE_DIRECT

189 } SPI_MASTER_TRANSFER_MODE_t;

194 typedef void (*SPI_MASTER_functionhandler)(void);

195 typedef SPI_MASTER_STATUS_t (*SPI_MASTER_lInit_functionhandler)(void);

196

197 /***********************************************************************************************************************

198 * DATA STRUCTURES

199 ***********************************************************************************************************************/

208 typedef struct SPI_MASTER_GPIO

209 {

210 XMC_GPIO_PORT_t* port;

211 uint8_t pin;

212 } SPI_MASTER_GPIO_t;

213

217 typedef struct SPI_MASTER_GPIO_CONFIG

218 {

219 XMC_GPIO_CONFIG_t port_config;

220 XMC_GPIO_HWCTRL_t hw_control;

221 XMC_SPI_CH_SLAVE_SELECT_t slave_select_ch;

222 } SPI_MASTER_GPIO_CONFIG_t;

223

227 typedef struct SPI_MASTER_CONFIG

228 {

229 XMC_SPI_CH_CONFIG_t * const channel_config;

230 SPI_MASTER_lInit_functionhandler fptr_spi_master_config;

232 /* Port configuration */

233 const SPI_MASTER_GPIO_t* const mosi_0_pin;

234 const SPI_MASTER_GPIO_CONFIG_t* const mosi_0_pin_config;

235 const SPI_MASTER_GPIO_t* const mosi_1_pin;

236 const SPI_MASTER_GPIO_CONFIG_t* const mosi_1_pin_config;

237 const SPI_MASTER_GPIO_t* const mosi_2_pin;

238 const SPI_MASTER_GPIO_CONFIG_t* const mosi_2_pin_config;

239 const SPI_MASTER_GPIO_t* const mosi_3_pin;

240 const SPI_MASTER_GPIO_CONFIG_t* const mosi_3_pin_config;

241 const SPI_MASTER_GPIO_t* const sclk_out_pin;

242 const SPI_MASTER_GPIO_CONFIG_t* const sclk_out_pin_config;

243 const SPI_MASTER_GPIO_t* const slave_select_pin[8];

244 const SPI_MASTER_GPIO_CONFIG_t* const slave_select_pin_config[8];

245 SPI_MASTER_functionhandler tx_cbhandler;

246 SPI_MASTER_functionhandler rx_cbhandler;

247 SPI_MASTER_functionhandler parity_cbhandler;

248 /* FIFO configuration */

249 XMC_USIC_CH_FIFO_SIZE_t tx_fifo_size;

250 XMC_USIC_CH_FIFO_SIZE_t rx_fifo_size;

252 /* Clock Settings */

253 XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t shift_clk_passive_level;

254 SPI_MASTER_TRANSFER_MODE_t transmit_mode;

255 SPI_MASTER_TRANSFER_MODE_t receive_mode;

256 XMC_SPI_CH_MODE_t spi_master_config_mode;

257 uint8_t slave_select_lines;

258 uint8_t leading_trailing_delay;

259 SPI_MASTER_SR_ID_t tx_sr;

260 SPI_MASTER_SR_ID_t rx_sr;

261 SPI_MASTER_SR_ID_t parity_sr;

262 } SPI_MASTER_CONFIG_t;

263

267 typedef struct SPI_MASTER_RUNTIME

268 {

269 uint32_t word_length;

270 uint32_t tx_data_count;

271 volatile uint32_t tx_data_index;

273 uint32_t rx_data_count;

274 volatile uint32_t rx_data_index;

276 uint8_t* rx_data;

277 uint8_t* tx_data;

278 volatile XMC_SPI_CH_MODE_t spi_master_mode;

279 SPI_MASTER_INPUT_t dx0_input;

281 SPI_MASTER_INPUT_t dx0_input_half_duplex;

283 volatile bool rx_busy;

284 volatile bool tx_busy;

285 volatile bool tx_data_dummy;

286 volatile bool rx_data_dummy;

288 } SPI_MASTER_RUNTIME_t;

289

290

294 typedef struct SPI_MASTER

295 {

296 XMC_USIC_CH_t* const channel;

297 const SPI_MASTER_CONFIG_t * const config;

298 SPI_MASTER_RUNTIME_t * const runtime;

299 #if ((SPI_MASTER_DMA_TRANSMIT_MODE == 1U) || (SPI_MASTER_DMA_RECEIVE_MODE == 1U))

300 const GLOBAL_DMA_t * const global_dma;

301 #endif

302 #if (SPI_MASTER_DMA_TRANSMIT_MODE == 1U)

303 const XMC_DMA_CH_CONFIG_t * const dma_ch_tx_config;

304 #endif

305 #if (SPI_MASTER_DMA_RECEIVE_MODE == 1U)

306 const XMC_DMA_CH_CONFIG_t * const dma_ch_rx_config;

307 const GLOBAL_DMA_t * const global_dma_rx;

308 const uint8_t dma_ch_rx_number;

309 #endif

310 #if (SPI_MASTER_DMA_TRANSMIT_MODE == 1U)

311 const uint8_t dma_ch_tx_number;

312 #endif

313 } SPI_MASTER_t;

314

318 /***********************************************************************************************************************

319 * API Prototypes

320 ***********************************************************************************************************************/

321 #ifdef __cplusplus

322 extern "C" {

323 #endif

324

360 DAVE_APP_VERSION_t SPI_MASTER_GetAppVersion(void);

361

402 SPI_MASTER_STATUS_t SPI_MASTER_Init(SPI_MASTER_t* const handle);

403

466 SPI_MASTER_STATUS_t SPI_MASTER_SetMode(SPI_MASTER_t* const handle, const XMC_SPI_CH_MODE_t mode);

467

524 SPI_MASTER_STATUS_t SPI_MASTER_SetBaudRate(SPI_MASTER_t* const handle, const uint32_t baud_rate);

525

610 SPI_MASTER_STATUS_t SPI_MASTER_Transmit(const SPI_MASTER_t *const handle, uint8_t* dataptr, uint32_t count);

611

696 SPI_MASTER_STATUS_t SPI_MASTER_Receive(const SPI_MASTER_t *const handle, uint8_t* dataptr, uint32_t count);

697

755 SPI_MASTER_STATUS_t SPI_MASTER_Transfer(const SPI_MASTER_t *const handle,

756 uint8_t* tx_dataptr,

757 uint8_t* rx_dataptr,

758 uint32_t count);

759

760 #if (SPI_MASTER_INTERRUPT_RECEIVE_MODE == 1U)

761

816 SPI_MASTER_STATUS_t SPI_MASTER_StartReceiveIRQ(const SPI_MASTER_t *const handle, uint8_t* dataptr, uint32_t count);

817 #endif

818

819 #if(SPI_MASTER_INTERRUPT_TRANSMIT_MODE == 1U)

820

885 SPI_MASTER_STATUS_t SPI_MASTER_StartTransmitIRQ(const SPI_MASTER_t *const handle, uint8_t *addr, uint32_t count);

886 #endif

887

888

889 #if(SPI_MASTER_DMA_RECEIVE_MODE == 1U)

890

955 SPI_MASTER_STATUS_t SPI_MASTER_StartReceiveDMA(const SPI_MASTER_t *const handle, uint8_t *addr, uint32_t block_size);

956 #endif

957

958 #if(SPI_MASTER_DMA_TRANSMIT_MODE == 1U)

959

1025 SPI_MASTER_STATUS_t SPI_MASTER_StartTransmitDMA(const SPI_MASTER_t *const handle, uint8_t *addr, uint32_t block_size);

1026 #endif

1027

1074 __STATIC_INLINE uint32_t SPI_MASTER_GetFlagStatus(const SPI_MASTER_t* handle, const uint32_t flag)

1075 {

1076 XMC_ASSERT("SPI_MASTER_GetFlagStatus:handle NULL" , (handle != NULL));

1077 return (XMC_SPI_CH_GetStatusFlag(handle->channel) & flag);

1078 }

1079

1124 __STATIC_INLINE void SPI_MASTER_ClearFlag(const SPI_MASTER_t* handle, const uint32_t flag_mask)

1125 {

1126 XMC_ASSERT("SPI_MASTER_ClearFlag:handle NULL" , (handle != NULL));

1127 XMC_SPI_CH_ClearStatusFlag(handle->channel, flag_mask);

1128 }

1129

1179 __STATIC_INLINE bool SPI_MASTER_IsTxBusy(const SPI_MASTER_t* const handle)

1180 {

1181 XMC_ASSERT("SPI_MASTER_IsTxBusy:handle NULL", (handle != NULL))

1182 return (handle->runtime->tx_busy);

1183 }

1184

1231 __STATIC_INLINE bool SPI_MASTER_IsRxBusy(const SPI_MASTER_t* const handle)

1232 {

1233 XMC_ASSERT("SPI_MASTER_IsTxBusy:handle NULL", (handle != NULL))

1234 return (handle->runtime->rx_busy);

1235 }

1236

1237

1285 __STATIC_INLINE void SPI_MASTER_EnableSlaveSelectSignal(const SPI_MASTER_t* handle, const SPI_MASTER_SS_SIGNAL_t slave)

1286 {

1287 XMC_ASSERT("SPI_MASTER_EnableSlaveSelectSignal:handle NULL" , (handle != NULL));

1288 XMC_ASSERT("SPI_MASTER_EnableSlaveSelectSignal:Invalid Slave selection" , ((slave == SPI_MASTER_SS_SIGNAL_0) ||

1289 (slave == SPI_MASTER_SS_SIGNAL_1) ||

1290 (slave == SPI_MASTER_SS_SIGNAL_2) ||

1291 (slave == SPI_MASTER_SS_SIGNAL_3) ||

1292 (slave == SPI_MASTER_SS_SIGNAL_4) ||

1293 (slave == SPI_MASTER_SS_SIGNAL_5) ||

1294 (slave == SPI_MASTER_SS_SIGNAL_6) ||

1295 (slave == SPI_MASTER_SS_SIGNAL_7))

1296 );

1297 XMC_SPI_CH_EnableSlaveSelect(handle->channel, handle->config->slave_select_pin_config[slave]->slave_select_ch);

1298 }

1299

1344 __STATIC_INLINE void SPI_MASTER_DisableSlaveSelectSignal(const SPI_MASTER_t* handle)

1345 {

1346 XMC_ASSERT("SPI_MASTER_Transmit:handle NULL" , (handle != NULL));

1347 XMC_SPI_CH_DisableSlaveSelect(handle->channel);

1348 }

1349

1365 __STATIC_INLINE uint16_t SPI_MASTER_GetReceivedWord(const SPI_MASTER_t *const handle)

1366 {

1367 XMC_ASSERT("SPI_MASTER_GetReceivedWord:handle NULL" , (handle != NULL));

1368 return XMC_SPI_CH_GetReceivedData(handle->channel);

1369 }

1370

1384 __STATIC_INLINE void SPI_MASTER_TransmitWord(const SPI_MASTER_t *const handle, const uint16_t data)

1385 {

1386 XMC_ASSERT("SPI_MASTER_TransmitWord:handle NULL" , (handle != NULL));

1387 XMC_SPI_CH_Transmit(handle->channel, data, handle->runtime->spi_master_mode);

1388 }

1389

1405 __STATIC_INLINE void SPI_MASTER_EnableEvent(const SPI_MASTER_t *const handle, const uint32_t event_mask)

1406 {

1407 XMC_ASSERT("SPI_MASTER_EnableEvent:handle NULL" , (handle != NULL));

1408 XMC_SPI_CH_EnableEvent(handle->channel, event_mask);

1409 }

1410

1423 __STATIC_INLINE void SPI_MASTER_DisableEvent(const SPI_MASTER_t *const handle, const uint32_t event_mask)

1424 {

1425 XMC_ASSERT("SPI_MASTER_DisableEvent:handle NULL" , (handle != NULL));

1426 XMC_SPI_CH_DisableEvent(handle->channel, event_mask);

1427 }

1428

1443 __STATIC_INLINE void SPI_MASTER_SetTXFIFOTriggerLimit(const SPI_MASTER_t *const handle, const uint32_t limit)

1444 {

1445 XMC_ASSERT("SPI_MASTER_SetTXFIFOTriggerLimit:handle NULL" , (handle != NULL));

1446 XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit(handle->channel, handle->config->tx_fifo_size, limit);

1447 }

1448

1464 __STATIC_INLINE void SPI_MASTER_SetRXFIFOTriggerLimit(const SPI_MASTER_t *const handle, const uint32_t limit)

1465 {

1466 XMC_ASSERT("SPI_MASTER_SetRXFIFOTriggerLimit:handle NULL" , (handle != NULL));

1467 XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit(handle->channel, handle->config->rx_fifo_size, limit);

1468 }

1469

1481 __STATIC_INLINE void SPI_MASTER_TXFIFO_EnableEvent(const SPI_MASTER_t *const handle, const uint32_t event)

1482 {

1483 XMC_ASSERT("SPI_MASTER_TXFIFO_EnableEvent:handle NULL" , (handle != NULL));

1484 XMC_USIC_CH_TXFIFO_EnableEvent(handle->channel, event);

1485 }

1486

1500 __STATIC_INLINE void SPI_MASTER_TXFIFO_DisableEvent(const SPI_MASTER_t *const handle, const uint32_t event)

1501 {

1502 XMC_ASSERT("SPI_MASTER_TXFIFO_DisableEvent:handle NULL" , (handle != NULL));

1503 XMC_USIC_CH_TXFIFO_DisableEvent(handle->channel, event);

1504 }

1505

1519 __STATIC_INLINE uint32_t SPI_MASTER_TXFIFO_GetEvent(const SPI_MASTER_t *const handle)

1520 {

1521 XMC_ASSERT("SPI_MASTER_TXFIFO_GetEvent:handle NULL" , (handle != NULL));

1522 return XMC_USIC_CH_TXFIFO_GetEvent(handle->channel);

1523 }

1524

1540 __STATIC_INLINE void SPI_MASTER_TXFIFO_ClearEvent(const SPI_MASTER_t *const handle, const uint32_t event)

1541 {

1542 XMC_ASSERT("SPI_MASTER_TXFIFO_ClearEvent:handle NULL" , (handle != NULL));

1543 XMC_USIC_CH_TXFIFO_ClearEvent(handle->channel, event);

1544 }

1545

1559 __STATIC_INLINE bool SPI_MASTER_IsTxFIFOFull(const SPI_MASTER_t* const handle)

1560 {

1561 XMC_ASSERT("SPI_MASTER_IsTxFIFOFull:handle NULL", (handle != NULL))

1562 return XMC_USIC_CH_TXFIFO_IsFull(handle->channel);

1563 }

1564

1577 __STATIC_INLINE void SPI_MASTER_RXFIFO_EnableEvent(const SPI_MASTER_t *const handle, const uint32_t event)

1578 {

1579 XMC_ASSERT("SPI_MASTER_RXFIFO_EnableEvent:handle NULL" , (handle != NULL));

1580 XMC_USIC_CH_RXFIFO_EnableEvent(handle->channel, event);

1581 }

1582

1595 __STATIC_INLINE void SPI_MASTER_RXFIFO_DisableEvent(const SPI_MASTER_t *const handle, const uint32_t event)

1596 {

1597 XMC_ASSERT("SPI_MASTER_RXFIFO_DisableEvent:handle NULL" , (handle != NULL));

1598 XMC_USIC_CH_RXFIFO_DisableEvent(handle->channel, event);

1599 }

1600

1613 __STATIC_INLINE uint32_t SPI_MASTER_RXFIFO_GetEvent(const SPI_MASTER_t *const handle)

1614 {

1615 XMC_ASSERT("SPI_MASTER_RXFIFO_GetEvent:handle NULL" , (handle != NULL));

1616 return XMC_USIC_CH_RXFIFO_GetEvent(handle->channel);

1617 }

1618

1632 __STATIC_INLINE void SPI_MASTER_RXFIFO_ClearEvent(const SPI_MASTER_t *const handle, const uint32_t event)

1633 {

1634 XMC_ASSERT("SPI_MASTER_RXFIFO_ClearEvent:handle NULL" , (handle != NULL));

1635 XMC_USIC_CH_RXFIFO_ClearEvent(handle->channel, event);

1636 }

1637

1650 __STATIC_INLINE bool SPI_MASTER_IsRxFIFOEmpty(const SPI_MASTER_t* const handle)

1651 {

1652 XMC_ASSERT("SPI_MASTER_IsRxFIFOEmpty:handle NULL", (handle != NULL))

1653 return XMC_USIC_CH_RXFIFO_IsEmpty(handle->channel);

1654 }

1655

1703 SPI_MASTER_STATUS_t SPI_MASTER_AbortTransmit(const SPI_MASTER_t *const handle);

1704

1758 SPI_MASTER_STATUS_t SPI_MASTER_AbortReceive(const SPI_MASTER_t *const handle);

1759

1763 #include "spi_master_extern.h"

1764

1765 #ifdef __cplusplus

1766 }

1767 #endif

1768

1769 #endif /* SPI_MASTER_H */

previous page start next page