STATus:ALARm:ENABle

From Keysight 34970A/34972A

STATus:ALARm:ENABle

Syntax

STATus:ALARm:ENABle <enable_val>

STATus:ALARm:ENABle?

Description

This command enables bits in the enable register for the Alarm Register group. The selected bits are then reported to the Status Byte.

Used With:

  • 34901A   20 Channel Multiplexer (2/4-wire) Module
  • 34902A   16 Channel Multiplexer (2/4-wire) Module
  • 34907A   Multifunction Module (digital input and totalizer channels only)
  • 34908A   40 Channel Single-Ended Multiplexer Module

Parameters

Name Type Range of Values Default Value
<enable_val> Numeric An integer from 0 to 65535, specifying the alarms to enable as a bit sum. This is a required parameter.

Remarks

  • The following table lists the bit definitions for the alarm enable register.
  • Bit # Bit Name Decimal Value Definition
    0 Alarm 1 1 An event has occurred on Alarm 1.
    1 Alarm 2 2 An event has occurred on Alarm 2.
    2 Alarm 3 4 An event has occurred on Alarm 3.
    3 Alarm 4 8 An event has occurred on Alarm 4.
    4 Queue Not Empty 16 The alarm queue is not empty.
    5 Queue Overflow 32

    An alarm queue overflow event has occurred.

    6 Alarm 1 64 Alarm 1 is triggered.
    7 Alarm 2 128 Alarm 2 is triggered.
    8 Alarm 3 256 Alarm 3 is triggered.
    9 Alarm 4 512 Alarm 4 is triggered.
    10-11 Not Used 1024-2048 0 is returned.
    12 Lower Limit 4096

    A lower limit alarm has occurred.

    13 Upper Limit 8192 An upper limit alarm has occurred.
    14-15 Not Used 16384-32768 0 is returned.

Return Format

The query reads the enable register and returns a decimal value that corresponds to the binary-weighted sum of all bits set in the register. For example, if bit 1 (decimal value = 2) and bit 2 (decimal value = 4) are enabled, the query will return +6.

Examples

The following command enables alarm registers 0 through 3.

STAT:ALAR:ENAB 15

 

The following query returns a the binary sum equivalent to the enabled registers.

STAT:ALAR:ENAB?

Typical Response: +15

See Also

STATus Subsystem Introduction