CPU_CTRL_XMC4: CPU_CTRL_XMC4.c Source File

CPU CTRL XMC4

CPU_CTRL_XMC4
CPU_CTRL_XMC4.c
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1 
55 /***********************************************************************************************************************
56  * HEADER FILES
57  **********************************************************************************************************************/
58 #include "cpu_ctrl_xmc4.h"
59 /***********************************************************************************************************************
60  * MACROS
61  **********************************************************************************************************************/
62 
63 /***********************************************************************************************************************
64  * LOCAL DATA
65  **********************************************************************************************************************/
66 
67 /***********************************************************************************************************************
68  * LOCAL ROUTINES
69  **********************************************************************************************************************/
70 
71 /**********************************************************************************************************************
72 * API IMPLEMENTATION
73 **********************************************************************************************************************/
74 /*
75  * API to retrieve the version of the CPU_CTRL_XMC4 APP
76  */
77 DAVE_APP_VERSION_t CPU_CTRL_XMC4_GetAppVersion(void)
78 {
79  DAVE_APP_VERSION_t version;
80 
81  version.major = CPU_CTRL_XMC4_MAJOR_VERSION;
82  version.minor = CPU_CTRL_XMC4_MINOR_VERSION;
83  version.patch = CPU_CTRL_XMC4_PATCH_VERSION;
84 
85  return (version);
86 }
87 /* Dummy Init API to maintain backward compatibility */
88 CPU_CTRL_XMC4_STATUS_t CPU_CTRL_XMC4_Init(CPU_CTRL_XMC4_t *const handler)
89 {
90  (void)handler;
92 }
93 
94 /*
95  * API to enable the MPU
96  */
97 void CPU_CTRL_XMC4_MPU_Enable(uint32_t options)
98 {
99  MPU->CTRL = MPU_CTRL_ENABLE_Msk | options;
100  __DSB(); /* Ensure MPU settings take effect */
101  __ISB(); /* Sequence instruction fetches using updated settings */
102 }
103 
104 /*
105  * API to disable the MPU
106  */
108 {
109  __DMB(); /* make sure all transfers are done */
110  MPU->CTRL = 0;
111 }
112 
113 #if (HARDFAULT_ENABLED == 1)
114 
115 volatile uint32_t stacked_r0;
116 volatile uint32_t stacked_r1;
117 volatile uint32_t stacked_r2;
118 volatile uint32_t stacked_r3;
119 volatile uint32_t stacked_r12;
120 volatile uint32_t stacked_lr;
121 volatile uint32_t stacked_pc;
122 volatile uint32_t stacked_psr;
123 volatile uint32_t _CFSR;
124 volatile uint32_t _HFSR;
125 volatile uint32_t _DFSR;
126 volatile uint32_t _AFSR;
127 volatile uint32_t _BFAR;
128 volatile uint32_t _MMAR;
129 
139 #if defined(__GNUC__)
140 #pragma GCC diagnostic ignored "-Wunused-but-set-variable"
141 #endif
142 __attribute__((naked)) void __HardFault_Handler(uint32_t args[])
143 {
144 
145  // Configurable Fault Status Register
146  // Consists of MMSR, BFSR and UFSR
147  _CFSR = SCB->CFSR;
148 
149  // Hard Fault Status Register
150  _HFSR = SCB->HFSR;
151 
152  // Debug Fault Status Register
153  _DFSR = SCB->DFSR;
154 
155  // Auxiliary Fault Status Register
156  _AFSR = SCB->AFSR;
157 
158  // Read the Fault Address Registers. These may not contain valid values.
159  // Check BFARVALID/MMARVALID to see if they are valid values
160  // MemManage Fault Address Register
161  _MMAR = SCB->MMFAR;
162 
163  // Bus Fault Address Register
164  _BFAR = SCB->BFAR;
165 
166  stacked_r0 = ((uint32_t)args[0]);
167  stacked_r1 = ((uint32_t)args[1]);
168  stacked_r2 = ((uint32_t)args[2]);
169  stacked_r3 = ((uint32_t)args[3]);
170  stacked_r12 = ((uint32_t)args[4]);
171  stacked_lr = ((uint32_t)args[5]);
172  stacked_pc = ((uint32_t)args[6]);
173  stacked_psr = ((uint32_t)args[7]);
174 
175  __asm("BKPT 0\n") ; // Break into the debugger
176 
177 }
178 
179 
180 /*KEIL*/
181 #if defined(__CC_ARM)
182 __asm void HardFault_Handler(void)
183 {
184  EXTERN __HardFault_Handler [CODE]
185 
186  TST LR, #4
187  ITE EQ
188  MRSEQ R0, MSP
189  MRSNE R0, PSP
190  B __HardFault_Handler
191 }
192 #endif
193 
194 /*IAR*/
195 #if defined(__ICCARM__)
196 void HardFault_Handler(void)
197 {
198  asm(" TST LR, #4 \n"
199  " ITE EQ \n"
200  " MRSEQ R0, MSP \n"
201  " MRSNE R0, PSP \n"
202  " B __HardFault_Handler\n");
203 }
204 #endif
205 
206 /*TASKING*/
207 #if defined(__TASKING__)
208 void HardFault_Handler(void)
209 {
210 __asm(" TST LR, #4 \n"
211  " ITE EQ \n"
212  " MRSEQ R0, MSP \n"
213  " MRSNE R0, PSP \n"
214  " B __HardFault_Handler\n");
215 }
216 
217 #endif
218 
219 /*GCC*/
220 #if defined(__GNUC__)
221 __attribute__((naked)) void HardFault_Handler(void)
222 {
223 __asm(" TST LR, #4 \n"
224  " ITE EQ \n"
225  " MRSEQ R0, MSP \n"
226  " MRSNE R0, PSP \n"
227  " B __HardFault_Handler\n");
228 }
229 #endif
230 #endif